Processor Complex
Model 90/95 Processor Board

Complex Identification (outlines)

Complex FCC ID, Release Dates, Announcement Letters
Complex Sub-Model Matrix (What is the complex in my machine?)
Complex Capabilities (summary by Roger Dodson, IBM)
Complexes, Planars, and ADF Definitions
Complex Benchmarks Unscientific comparison. Some unusual results.

Processor Complex Pinout

Japanese PS/55 Processor Complexes

US5162979 Personal computer processor card interconnect system
US5355489 BIOS load for a personal computer system having a removable processor card
US5381541 Computer system having planar board with single interrupt controller and processor card with plural processors and interrupt director (Multi-processor Complex?!)

Overview of Complex Features
Reason for the Processor Complex
Complex Features
   L1 or Processor Cache
   L2 Cache
   Memory Controller
   Dual Path to Memory
   Two-Way Interleaved Memory Banks
   DMA Controller
   40 MB/s Data Streaming
Complex Compatibility
Difference Between Complex Types
16-bit Busmasters
Can't See >16MB Under W95

Overview of Complex Features

Complex Processor Max. RAM
L2 Cache
Base 0 / Type 0
0- 386DX-20 ?P 24b - 10M No No No No
0 386DX-20 ?P 24b - 10M 64 WT No No No
Base 1 / Type 1
G 486SX-20 64P 24b - 10M No Y4 No No
J 486DX-25 64P 24b - 10M 0 / 256 WT1 Y4 No No
K 486DX-33 64P 24b - 10M 0 / 256 WT1 Y4 No No
Upg 50 486DX-50 64P 24b - 10M 256 WT2 Y4 No No
Upg 66 486DX2-66 64P 24b - 10M 0 / 256 WT1 Y4 No Y5
Base 2 / Type 2
H 486SX-25 64P3 24b - 25M No No No No
L 486DX2-50 64P3 24b - 25M No No No No
Base 3 / Type 3
M 486DX-50 64P / 64E 32b - 20M 256 WT Y Y No
Base 4 / Type 4
N 486DX2-66 64P / 256E 32b - 20M 128 WB Y Y Y
P Pentium 60 64P / 256E 32b - 20M 256 WB Y Y Y
Q Pentium 66 64P / 256E 32b - 20M 256 WB Y Y Y
Y Pentium 90 64P / 256E 32b - 20M 256 WB Y Y Y


Processor  Processor type and clock frequency (MHz)
Max. RAM  Maximum supported memory (P - parity SIMMs, E - ECC SIMMs)
DMA Ctrl.  DMA Controller (b - bits - width, M - MHz - clock frequency)
L2 Cache  Level 2 Cache size and type (WT - write-through, WB - write-back)
Dual Path  Dual Path to Memory
Adv. MCA  Advanced MCA features: Streaming Data Mode (40 MB/s), Synchronous Channel Check, Data Bus Parity, Subsystem Control Block


  1. 256 KB 17 ns daughterboard, optional
  2. 256 KB 15 ns daughterboard, comes standard with the complex
  3. Complex supports non-paired SIMMs
  4. Base 1 complexes also support this feature, but do not have buffers
  5. The Upg. 66 complex features Flash BIOS, but no updates were ever released

Reason for the Processor Complex

In the first PS/2 models, most components were integrated into the planar of the system. This severely limited upgrade options and upgrade flexibility. While one component was upgraded, for example the processor, the other components such as the I/O controller and the memory controller were not. This created combinations of fast and slow components, which created unbalanced systems. Unbalanced systems are not as efficient as balanced systems where every components' performance is matched against other components' performances.

With this in mind, the server key components have been grouped together on a separate card known as a processor complex. Now the processor is contained on a removable processor complex board, which also holds the processor/memory bus, the memory controller, DMA controller, and Micro Channel bus interface. Placing the processor on a complex together with key components means that when a system is upgraded, balanced systems performance can be maintained.

IBM has provided an upgrade path for existing and future file servers that allows network design engineers to replace the system processor complex with a faster and more efficient system processor complex at a later date. This policy of upgrading allows the server to accommodate increased server CPU utilization without the need to buy a complete new machine. Within the processor complex there are many features that are capable of providing more efficient data transfer. They may consist of:

  • Cache
  • Dual Path to Memory
  • Two-Way Interleaved Memory Banks
  • 32-bit DMA Controller
  • 40 MB/s Data Streaming

Complex Features

The processor complex consists of the devices and features in the computer that perform logical operations and calculations, control access to memory, and manage data-transfer operations. The following devices and features make up the processor complex:

  • The microprocessor
  • The memory subsystem
  • The direct memory access (DMA) controller

If your computer contains a processor complex, it is connected to the system board by two 164-pin, 82-position connectors, known as the processor interface connection. The processor interface connection provides:

  • The Micro Channel interface, which allows data to be transferred between the processor complex and the adapters in the Micro Channel expansion slots.
  • The system board interface, which allows the transfer of data between the processor complex and devices on the system board, such as the parallel, serial, keyboard, and auxiliary-device ports (for an explanation of these devices, see Input/Output Connectors and Ports).
  • Two memory interfaces (Dual Path), systems M-Y, which the processor complex uses to read from and write to system memory. All access to system memory is through the memory controller in the processor complex.

L1 or Processor Cache

There are two levels of cache. The cache incorporated into the main system processor is known as Level 1 (L1) cache. The 486 incorporates a single 8 KB cache (Overdrive chips can have 16 KB). Pentium CPUs have two 8 KB caches, one for instructions and one for data. These caches act as temporary storage places for instructions and data obtained from slower, main memory. When a system uses data, it will be likely to use it again, and getting it from an on-chip cache is much faster than getting it from main memory.

L2 Cache

The external cache is called Level 2 (L2) cache and it provides additional high speed memory to the Level 1 cache. This additional cache memory works together with the cache memory native to the main processor (L1). If the processor cannot find what it needs in the processor cache (a first-level cache miss), it then looks in the additional cache memory. If it finds the code or data there (a second-level cache hit), the processor will use it, and continue. If the data is in neither of the caches, an access to planar memory must occur. (G, H, and L complexes do NOT have L2 cache, nor do they have a cache socket).

L2 cache can be accessed 5 to 10 times faster than standard memory. Cache memory uses Static Random Access Memory (SRAM) which is much faster than the Dynamic Random Access Memory (DRAM) used for system memory. SRAM is more expensive and requires more power, which is why it is not used for all memory.

Note: The J/K/UPG 66 complexes use 17 ns 256 KB cache daughtercard. The UPG 50 uses a 15 ns 256 KB cache daughtercard.

Memory Controller

The memory controller is a device on the processor board that controls access to system memory by the microprocessor and I/O devices. Registers in the memory controller contain information about the amount and type of memory that is installed in the computer. During a system reset, the power-on self-test (POST) routine writes this information into the registers.

The functions of the memory controller vary among PS/2 models. They can include:

  • Dual-bus capability, which allows the microprocessor to read from and write to system memory while a bus master is controlling the Micro Channel bus. (See the Three Types of Overlapped Access.)
  • Memory timing control, which coordinates data-transfer operations involving single inline memory modules that operate at different speeds.
  • Cache control, which ensures the validity of the contents of the cache. The cache controller (or, in some PS/2 models, the memory controller) identifies the instructions and data that are most likely to be needed while a specific program (or part of a program) is running and copies them from system memory into the cache. During processing, as requirements change, the cache controller copies other data and instructions into the cache, replacing data and instructions that are no longer needed in the cache. Computer performance is improved each time the microprocessor finds what it needs in the cache (a cache hit). If it does not find what it needs in the cache (a cache miss), the cache controller must locate the data or instruction in system memory and copy it into the cache, while one or more wait states are imposed on the microprocessor. The cache controller manages the use of the cache so that the number of cache hits far exceeds the number of cache misses.
       In some PS/2 models, the microprocessor has only a built-in L1 cache, but it supports an optional 256 KB L2 cache. This 256 KB cache option increases the amount of cache memory in the computer, which increases the probability of cache hits.
  • Bus-width allocation, which supports 8-, 16-, and 32-bit data-transfer operations.
  • Memory interleaving, which is a method of reducing the time the microprocessor has to wait for system memory to respond during memory I/O operations.

Dual Path to Memory

When bus masters were implemented on Micro Channel servers, it was found that there was often contention for memory access between the processor and the bus masters, and that the processor was being delayed waiting for bus masters to release the path into memory. The new design of the processor complexes addresses these issues by providing a dual-path into memory, effectively providing two paths to system memory, one from the processor and one from the Micro Channel. These two separate paths to system memory allow overlapping of processor and bus master cycles. (M-Y complexes)

Note: Dual Path memory is also known as Dual Bus Interleave. Base 1 complexes also support this feature, but do not have buffers. Base 2 complexes do not support Dual Path Memory. Packet Data Transfers are used by the I/O buffer for writes to memory. This means that 16 bytes are written to memory in one processor cycle. In unbuffered systems, a write to memory is performed every four bytes.

Three kinds of overlapped cycles can occur:

CPU reads to L2 cache simultaneously with bus master I/O
   When the microprocessor is reading from or writing to its internal cache or to the optional 256 KB cache, the bus master that is controlling the Micro Channel bus has exclusive access to system memory.

CPU reads to L2 cache simultaneously with bus master memory access
   The microprocessor and the bus master that is controlling the Micro Channel bus can use the system memory at the same time, provided that they do not try to use the same memory locations.

CPU reads to memory simultaneously with bus master I/O
   When a bus master is reading from or writing to an I/O device or an adapter in a Micro Channel expansion slot, the microprocessor has exclusive access to system memory.

Both processor and Micro Channel cycles are buffered into 16 byte blocks, further alleviating the contention for memory by reducing the frequency of the accesses. Implementing dual-path access to memory and the buffering of cycles can give a system throughput of up to three times that of a server without it.

In computers that do not have a dual bus, the microprocessor is the default master, which means that it has to wait until no other masters are controlling the Micro Channel bus before it can have access to system memory.

Two-Way Interleaved Memory Banks

Another performance advantage is gained when the processor is accessing memory in burst mode. Memory is split into two banks, and data or code is stored sequentially across these banks; for example addresses 0 and 2 are held in bank 1, and addresses 1 and 3 are held in bank 2. The reason for this arrangement is that when a 486 burst mode request is made, the accesses to memory will be sequential. When the memory controller detects such a burst request from, for example, bank 0, it also pre-fetches the next 32 bits of data from bank 1. This way, the processor is not kept waiting while the information is being retrieved from memory.

DMA Controller

DMA controllers are a dedicated unit with the ability to move data between system memory and a device on the Micro Channel.

More information about DMA and DMA Controllers HERE.

It's used by simple adapters, and also by the parallel and serial ports. Earlier versions of the Model 95 (G-L complexes) implemented a 24-bit DMA, limiting DMA memory transfers to below 16 MB (whereas the 486 processor was able to address up to 4GB of memory). On 32-bit systems with more than 16 MB of memory, this could cause problems if a DMA access was for memory above 16 MB. The operating system could work around the problem by ensuring that DMA buffers were always below 16 MB when a DMA transfer was done, but this imposes a performance penalty.

40 MB/s Data Streaming

The 40 MB/s data streaming transfer (M through Y complexes) offers considerably improved I/O performance. As in many cases, blocks transferred to and from memory are stored in sequential addresses, so repeatedly sending the address for each four bytes is unnecessary. With data streaming transfer the initial address is sent, then the blocks of data are sent and it is then assumed that the data requests are sequential.

Note: The M complex supports Streaming, but lacks SynchroStream Controller.

List of adapter that support this transfer mode can be found HERE.

Complex Compatibility

Complexes work in all 8590 / 8595 / 9590 / 9595 / 500.

Any existing Model 90, Model 95, or PC Server 500 can be upgraded to a new Processor Complex. For example, Base 1 to Base 2 or Base 3 or Base 4; Base 2 to Base 4, etc.

However the T1/T2/T3 complexes will NOT work in the newer 95A (dual serial/dual parallel) planar. This is due to the fact that the older T1/T2/T3 BIOS and refdisks lack support for the revised 95A planar (different layout of the POS registers, different NVRAM implementation etc.).

Note: The power supply in the Model 90 case is supposedly a little small for the DX50, P60, P66, and P90 complexes. And in addition, the air baffle in the Model 90 may have to be removed if a processor with a big heat sink or heatsink / fan combination is installed. But I have to wonder, it's rated for 215 Watts. That's not THAT weak... Hell, the 9577 PS is only 194 Watts.

Difference Between Complex Types

Hi Louis!
> Peter, what are the differences in the G, J, K, and M class boards?

Obviously not only the speed...
   As far as I can see IBM followed different "evolutionary stages" with these boards. The first being presented was the 33 MHz Type 1 (64F0198), which was offered as 64F0201 with only 25 MHz almost at the same time. The 33 MHz model had been the "top line" model with cache and all that. I got a "handwired" platform from Charles Lassiter, which has still 64F0198 printed on the *card* but a 25.00 MHz oscillator and "handstamped" ASICs. Looks a lot like a pre-production sample - and proves that the 25 MHz is derived from the 33 MHz - not other way round. The earliest HRM for the 95 however (dated March 1990 IIRC) mentions both of them.

Mentions "optional 256K cache" - which makes clear that no other board than 64F0198 and 64F0210 is meant. The 486DX2-33/66 board 92F0145 is then a much later development out of the Non-SOD 64F0198 - intended to use Flash-BIOS, but not fully developed or supported. (That's the board with the odd bank-select jumper in the top/right corner)

(Ed. based on personal inspection of a 92F0048) - The 92F0048 appears to be also based on the Non-SOD 64F0198, with a DX50 CPU, a 50 MHz oscillator, and some decoding circuitry mounted in the area that on the SOD would go on. The matching 12 ns cache module is 92F0050.

The smaller Type 1 platforms had been offered to form "entry models" - focused on the Model 90 (92F0065 - 486SX-20 and 92F0049 - 486DX-20). The 92F0065, which I call "Kiddies CPUs", is the only one which has a 487SX-presence" Jumper.

A totally different thread are the Type 2 platforms, which all base on the 92F0079. The Type 2 platforms have been developed to make memory selection a bit easier - for the cost of some performance as a cost-efficient solution.

The Type 3 platform of the -M- class has been intended for high-end servers: paired memory *and* ECC support. Only few Model 90 systems saw this platform as far as I know. Don't know if IBM ever offered it officially in the 90. I remember having seen 2 or 3 9590-AMF machines at a customer - but they had the [PA]-sticker close to the Serial-number decal... which identifies them as "upgraded machines".

The -M- platform even survived the change from the 8595 to the 9595 (with the old planar and LED-panel however) along with the 92F0161 486DX2-25/50 -L- platform. Strange enough.

The final stage of the 486-line was reached with the Type 4 -N- class board 61G2343 - which was the processor to the 5 V Pentium (P5) platform. This however is a totally new development, at a time when 486 processors were already a bit dusted.

The Type 4 platforms are all very similar with the integrated Intel Cache chipset. I think there has been a lot experience used from the -M- class DX-50 board. But this time everything fits on *one* PCB and make the funny shielded hi-density connectors obsolete for the "second floor" PCB.

> Are there any ECAs related to any specific FRUs?
   No. The "classical" -K-type board went through several "technical changes without notice" and that was all (S.O.D. - still unclear which chip should fit in there ...).
   So did the "92F0079-family" Type 2 boards. IBM never announced any technical changes on these boards. As far as I can recall there was no common ECA at anytime on any of the complexes. Only "withdrawn from marketing" notices...
   There had been some traffic on the IBM BBS in 1991 - 1993 when people found out that they could not use over 1GB harddisks with the Type 1 & 2 platforms, but IBM offered the upgrade EPROMs (for free !) until the deadline of December 1992, which was then stretched out to December 1993 at last.

16-bit Busmasters

When installed with the 486SX/25 Processor Upgrade Option, 16-bit bus masters (for example, PS/2 Micro Channel SCSI Adapter (#1005, 6451109)) that support 32-bits of addressing will cause system malfunction and/or potential loss of data when the user installs greater than 16 MB of system memory.

Can't See >16 MB Under W95

HIMEMUPD.EXE is the cure!

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