SynchroStream Controller
"Mad River"?

SynchroStream Function
Systems with SynchroStream
SynchroStream Advantages
Chip Package
Supply Voltage

SynchroStream Function (source HERE, page 43 physical; edited)

The SynchroStream Controller (SSC) uses IBM's most advanced technology packaging (1992/1993) to integrate the following 5 major chips into a single device:

  • Memory controller (interleaved)
  • Micro Channel controller (BIU)
  • DMA controller (32-bit, PIO/SCB)
  • FIFO buffers
  • ECC logic

Ed. The SSC is a direct evolution of the Type 3 processor complex logic. What was once implemented using 5+ individual chips now coexists on the same die. Despite the strikingly different levels of integration, the two solutions are very similar feature-wise, and even the register map remained largely the same.

This technology allows the high-speed interconnects and large streaming pipes that form the SynchroStream Engine to provide state-of-the-art performance.

The SSC synchronizes data traveling between major subsystems and allows it to stream in parallel, at full bandwidth, to each subsystem concurrently.

At the heart of the computer, data is moving continually between processor, cache, main memory and the Micro Channel. Typically there is a single path to memory, so fast devices like processors have to wait for much slower I/O devices, slowing down the performance of the entire system to the speed of the slowest device. The SSC was designed to overcome this problem. It synchronizes the operation of fast and slow devices and streams data to these devices to ensure all devices work at their data at their optimum levels of performance.

SSC is an intelligent device in that it predicts what data the devices will need and loads it from memory before it is requested. When the device wants the data, it is presented to it from the SSC and the device can continue working immediately, as it does not have to wait for the data to be collected from memory. When devices are moving data into memory, the SSC holds the data, and writes it to memory when it is most efficient to do so. Since devices are not moving data to and from memory directly, but to the SSC, each device has its own logical path to memory. Devices do not have to wait for other slower devices.

The SynchroStream engine operates by using a spinning valve that continuously forms different connections between pipes. Once a connection is made, data is streamed to the Micro Channel or processor at the highest possible rates. Parallel paths allow data to stream to multiple sources at the same time. The pipes even continue to stream after the connection is changed. Data is always streaming to the Micro Channel and processor, allowing them to operate at full bandwidth.

SynchroStream Advantages (source HERE, page 44 physical; marketing blurb)

Fast single chip implementation - Competitive designs are multi-chip and have the performance overhead of moving information between chips. SynchroStream technology provides a Zero Wait State Pentium implementation.

Intelligence - SSC is intelligent in that it predictively loads data from memory so that requesting devices are not kept waiting. In addition, writes to memory are stored within the SSC and written to memory to optimize memory utilization. (Ed. "Intelligent" is probably overselling it a little. The SSC most likely just buffers more data than was requested.)

RISC-like architecture - Pipelines are used to move data in a fast, efficient manner between memory and the requesting device. (Ed. And that makes it RISC-like?)

Stream data to Micro Channel devices - SSC can stream data to Micro Channel devices at 40 MB/s.

Upgradable system implementation - Competitive system designs do not have the unique Upgradable Processor Complex design so you cannot upgrade to SynchroStream-like functions from earlier models. (Ed. Other vendors also had their own upgradable processor complexes. However, it's true that the bus logic was usually located on the motherboard/backplane and therefore wasn't easily upgradable.)

Systems with SynchroStream

The SynchroStream controller can be found on the following boards:

The SSC is located on all Type 4 processor complexes, in the Server 95, 95 Array, and 500 systems. Implementation on the processor complex means that current PS/2 Server 95 and PS/2 Model 90 users can easily upgrade their machines to have SSC functions.

The part number of the chip used on the Type 4 boards is either 50G8192 (older?) or 8190587 (newer?). The two variants seems to be interchangeable and the only obvious difference is a slightly different packaging. It's unknown whether there are any internal changes. Register-wise, the two variants are fully compatible.

The SSC can be also found on the Reply TurboProcessor 60/80 planar and on the Olivetti M6-520/540/560 system board (on a daughter board called "Mad River Module"). The used part has a different P/N - 50G6871, but seems to be mostly (or perhaps completely) register compatible with the variant(s) used on the Type 4 platform. Pin compatibility is however unknown currently.

The later 9576 and 9577 systems with the Lacuna Planar have a different type of highly integrated system controller chip. There is a document that refers to it as the "SynchroStream Controller", but that's the only known instance to use that name. The chip uses a different package (CQFP-304), implements a subset of the Type 4 SSC functionality, and uses a drastically different register map.

Chip Package

The package used to encapsulate the SSC is called CCGA - "Ceramic Column Grid Array". It has 625 solder columns organized in a 25 x 25 grid - making it a CCGA-625. It's a SMT (Surface-Mount Technology) device.

P/N 50G8192
(Type 4 "N" Complex)

P/N 8190587
(Type 4 "Y" Complex)

P/N 50G6871
(Reply TurboProcessor 60/80)

The ceramic base holds multiple layers of interconnects going from the solder columns to the silicon die. The die itself is of the flip-chip design. The package is equipped with an IHS - "Integrated Heat Spreader" that protect the die and helps with heat dissipation.

The packaging slightly differs between some of the SSC variants. The 50G8192 and 50G6871 chips use a thick ceramic base (>3 mm) and an IHS with a notch close to one of the corners - indicating pin 1. The 8190587 part has a noticeably thinner base (~2 mm) and pin 1 is marked by a cut-off IHS corner.

Supply Voltage

The SSC uses a lower supply voltage of 3.7 - 3.75 V. This voltage is derived from the 5 V rail using a low dropout voltage regulator (LT1085CT in case of the Type 4 platform).

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