When multiple devices need to use the Micro Channel bus at the same
time, these devices participate in arbitration. Every device that
can arbitrate for control of the bus is assigned a priority level, known
as an arbitration level, that is used to determine which device should
control the bus next. The arbitration level for each device is contained
in a software file, known as an adapter description file (ADF).
Burst Data Transfer
In non-Micro Channel servers, transferring each byte of
data is a two-step process. First, the microprocessor signals that
it is going to send a byte of data. Then it sends the byte and signals
that it is going to send the next byte. The microprocessor cannot
perform any other tasks while it is managing a data-transfer operation
in this way. Micro Channel architecture supports burst data transfers,
in which data is sent in multiple bytes without intervention by the
microprocessor. This improves system performance and allows faster data
transfers between devices.
Bus Parity Checking
Bus parity checking is a method of verifying that data
has not been changed during a data-transfer operation. Bus parity
checking uses an extra bit, known as a parity bit, that is sent with each
byte of data as it is transferred across the bus. The parity bit
is set to 1 or 0 so that each byte has an odd number of 1's (if the server
uses odd parity) or an even number of 1's (if the server uses even parity).
If the parity (odd or even) of the received byte does not match the parity
of the byte as it was sent, an error occurred during transmission and the
receiving device can request that the data be sent again.
Channel Check Reporting and Error Logging
Errors can occur not only during data-transfer operations,
but also while data is stored in system memory. The contents of a
memory location can be changed accidentally, a memory module can be defective,
or other hardware failures can occur in the server.
Direct memory access (DMA)
Direct memory access (DMA) is a method of transferring
data between system memory and I/O devices without requiring intervention
by the microprocessor. DMA is more efficient than programmed I/O,
in which the microprocessor reads the data from the sending device and
then writes it to the receiving device. In DMA data transfers, data
can bypass the system microprocessor as it moves between system memory
and I/O devices. DMA improves server performance because the microprocessor
does not have to interrupt its processing activities to manage data transfers.
Data bus parity support
Provides for the verification of correct data as it is transferred between the processor and memory and over the Micro Channel. All data moved between individual components on the Processor Complex use this feature (processor, memory controller DMA, Micro Channel controller).
Dual Path Memory
Allows both the processor and busmasters to access memory concurrently though two paths.
Complexes use a a dual bus, meaning that it has one data bus from the microprocessor to the memory controller and another data bus from the Micro Channel devices to the memory controller. This allows the microprocessor to read from and write to system memory while a bus master is controlling the Micro Channel bus.
Without a dual path bus, there is often contention for system resources such as main memory. When contention between the processor and a bus master occurs, one has to wait for the other to finish its memory cycle before it can proceed. Thus, fast devices such as processors have to wait for much slower I/O devices, slowing down the performance of the entire system to the speed of the slowest device. This is very costly to the overall system performance.
The following list summarizes dual-bus operation:
In servers that do not have a dual bus, the microprocessor is the default master, which means that it has to wait until no other masters are controlling the Micro Channel bus before it can have access to system memory.
Enhanced Dual Path Memory
Although Base 1 and 2 complexes allow both the processor
and busmasters to access memory concurrently through two paths, the Base
3 and 4 has buffers at both paths to provide better performance. Also the
buffer on the adapter side (I/O buffer) uses packet data transfers for
writes. This means 16 Bytes are collected and this packet is written in
one cycle to memory as opposed to writing for every 4 bytes received (as
with unbuffered systems).
Memory controller which will automatically correct any single bit errors on the fly (98% of memory errors are single bit); all 2 bit errors are found which halt system; some 3 and 4 bit errors are found which halt system; single bit errors are logged with optional software (NetFinity?) and multiple bit errors are logged in NVRAM.
Vital Product Data (VPD)
Allows software (LAN Network Manager, LAN Mgmt Utilities/2) to obtain a unique serial number (identifier) on the processor complex which is in ROM (like Base 3). Also provides unique ID (model/submodel), type/model/ serial number, manufacturing ID, planar FRU number, and planar part number.
This system provides a means of storing and retrieving vital product data (VPD). Vital-product data contains product-specific information that describes various adapters and components within a system. This information can be used in inventory and asset management.
In contrast to system configuration information, which is related to
resource allocation, vital-product data contains information related to
the physical characteristics, such as part number, engineering level, and
product name. For example, the vital-product data for the Server
95 system consists of the model and submodel bytes, the system type number,
the system serial number. The vital-product data for the system board
includes the system board serial number, a
The VPD information for the system, system board, and any installed options that also provide vital-product data can be read using BIOS calls or operating-system utilities (if they are provided). For more information, refer to Interrupt 15H, Vital Product Data System Service ((AH)=D2H) in the IBM Personal System/2 and Personal Computer BIOS Interface Technical Reference.
40 MB/s Streamers
IBM 32-bit MCA busmasters that support 40 MB/s streaming:
A master is a device that can own the Micro Channel bus. When a master owns the bus, it can send data to or receive data from a slave (a device, an adapter, or system memory) without interrupting the microprocessor. There are three types of masters: the system master, bus masters, and the DMA controller.
The system master assigns system resources, manages the system configuration, issues the commands of the primary operating system, and can grant control of the Micro Channel bus to a bus master.
Your server supports up to 15 bus masters. Bus masters
take control of the Micro Channel bus and transfer data directly to and
from I/O devices and memory without requiring intervention by the system
microprocessor or DMA controller.
The DMA controller manages data transfers between DMA slaves and memory slaves. This type of transfer is often called a third-party DMA operation. See Direct Memory Access Controller and Direct Memory Access for more information.
A slave is a device that is selected by a controlling master as either the source or the target for a transfer. A slave can also begin a service request, such as an interrupt. There are three types of slaves: memory, I/O, and DMA.
A memory slave is a device that provides a block of system memory. Memory slaves respond to read and write operations by placing the requested data on the Micro Channel bus or by writing data from the bus to random access memory (RAM). A memory slave can be selected by any of the three types of Micro Channel masters.
An I/O slave is a device that communicates with or controls a separate piece of equipment, such as a printer. An I/O slave can be selected by the system master or by a bus master.
A DMA slave is the only type of slave that can initiate arbitration. DMA slaves require the DMA controller to manage data transfers. A DMA slave can be selected by the DMA controller or by a bus master.
Streaming data transfer
The streaming-data procedure allows high-speed transfer
of data between bus masters and slaves. This procedure supports high-speed
transfers of large blocks of data for devices such as hard disk drives
and network adapters.
More information about the various streaming transfer cycles can be found HERE.
Subsystem Control Block (SCB)
Provides for the enhanced transfer of command, data, and status information between busmasters (and between busmasters and the system processor) to give increased performance. Capabilities such as command chaining, data chaining, and block data moves frees the processor from waiting for command completion before issuing the next command and frees the processor for other tasks while a busmaster operates in parallel. Adapters and device drivers must support this feature (many do today).
More information about SCB can be found HERE.
Synchronous Channel Check
Support provides for the signaling of errors synchronously with the transfer in progress. Adapters and device drivers must be designed to support this feature (none do today).