The Processor Complex interface (also known as "Processor Interface Connection") consists of Micro Channel signals (some of which are shared with the planar I/O bus), memory signals, control signals, power supply lines, and some other connections.
The physical interface consists of two identical connectors. The connector type used here is an unique variant of the Micro Channel connector with 2x40 + 2x42 pins (164 usable pin positions, or 168 positions - including pin positions taken by the physical key). This gives us 328 usable pins total for both connectors. The connectors are placed in-line with no gap in between, touching each other by the shorter 2x40-pin section.
The interface is common to both the Model 90 and Model 95 (Server 500) planar boards.
The pinout map (oof, 328 pins!) and all drawings made by Tomas Slavotinek.
The "component side" (A) and "solder side" (B) refers to an installed processor card.
The "Rear" arrow points towards the back side of the planar/system unit.
Connector 1 (Rear)
Micro Channel (and planar I/O) bus connections + some memory signals.
Connector 2 (Front)
Almost exclusively memory signals.
The Processor Complex interface consists of:
Throughout this document, a minus sign (-) in front of a signal name indicates that the signal is active when it is at a low-voltage level. When no minus sign appears, the signal is active when it is at a high-voltage level. For example, -CMD specifies the signal is active low. Also, ARB/-GNT is in the ARB state when it is at a high level and is in the -GNT state when it is at a low level.
All of the logic signal lines are transistor-transistor logic (TTL) compatible.
The only voltage available on the Processor Complex interface is +5 V DC. Pins supplying this voltage are located on the A side of the connectors, together with some ground pins. A majority of the ground pins is then located on the B side.
Any other voltages are generated locally on the processor board, from the +5 V DC supply rail.
Micro Channel Signals
32-bit Micro Channel interface. All Micro Channel Signals are described HERE.
Note: Some of the channel data, address, and control signals are shared with the planar I/O bus. This bus interconnects all the on-planar features - external I/O ports, FDC, Op Panel interface, memory Presence Detect lines, etc.
Two 32-bit interfaces (64-bit total) between the memory controller on the processor card and the memory SIMMs on the planar. The memory is organized as two independent memory banks - Bank A and Bank B. Each bank then consists of two SIMM pairs:
Some signals are unique to each SIMM slot, some are shared within the individual SIMM pairs, and some are shared by the entire bank.
MA bp xx: Memory Address Bit xx for Bank b Pair p
MD b xx: Memory Data Bit xx for Bank b
MDP b x: Memory Data Parity Bit x for Bank b
BS b x: Block Select x for Bank b
WE bp: Write Enable for Bank b Pair p
CAS b x: Column Address Strobe x for Bank b
-CASP b: Column Address Strobe Parity for Bank b
RAS bs x/y: Row Address Strobe x and y for Bank b Slot s
ECC PD: Error-Correcting Code Presence Detect: This signal is driven by the planar logic and it's the negative AND of -ECC PD from each SIMM connector (pin 48). If any of the SIMM slots is occupied by a ECC memory module, this signal is driven high. Low otherwise.
-RESET: -System Reset: This signal is driven by the planar logic.
INTR: Interrupt Request: This signal is driven by the planar interrupt controller and is connected to the INTR pin of the main processor.
MMCR RTN: Matched Memory Cycle Request Return: This signal is driven by the planar logic and it's the AND of -MMCR from each channel connector.