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Compiled by Roger Dodson, IBM - May 1996, original HERE (page 4).
HTMLized by Louis Ohland. Edited and formatted by Tomáš Slavotínek.
The IBM Model 90, and Model 95, and PC Server 500 are unique in
providing a Processor Complex (adapter) that integrates the
(1) processor, (2) memory cache controller and L2 cache, (3)
memory controller, (4) DMA controller, and (5) I/O bus controller.
This provides the capability to upgrade to new technology by only
replacing the Processor Complex. Upgrading a processor along with
the memory and I/O controller have a significant effect on
performance via a balanced, tuned system. Vendors that do NOT
change memory and I/O controllers run the risk of having an
unbalanced system that is not as efficient. There are four types
of Processor Complexes for these systems: Base or Type 1, 2, 3,
and 4.
- Processor Complexes are interchangeable among Model 90's, Model
95's, and the PC Server 500. However, the refdisks for the Type
1-3 complexes lack the planar ADFs for the 95A planar.
- Any existing Model 90, Model 95, or PC Server 500 can be
upgraded to a new Processor Complex. For example, Base 1 to Base 2
or Base 3 or Base 4; Base 2 to Base 4, etc. If "Upgrade" is listed
above, then an upgrade option is available.
All Processor Complexes withdrawn as of June 1996.
"Base 0" / "Type 0" (not included in the original document; unofficial name)
| "T0-" | 386DX 20 MHz | (announced ?) |
| "T0+" | 386DX 20 MHz | (announced ?) |
- 64KB Level 2 memory cache (write-through) on "0" (Minus
complex has no L2 cache or controller).
- 80387DX-20 coprocessor socket
- 24 bit DMA; 10 MHz.
- Single path memory design Processor and busmasters must access
memory though same path.
- 20 MB per second data transfer support (for MCA bus).
Base 1 / Type 1
| "G" | 486SX 20 MHz | (announced Oct 1990) |
| "J" | 486DX 25 MHz | (announced Oct 1990) |
| "K" | 486DX 33 MHz | (announced Oct 1990) |
| Upgrade | 486DX 50 MHz | (announced June 1991) |
| Upgrade | 486DX2 66/33 MHz | (announced Aug 1992) |
- Level 2 memory cache socket for optional 256K 17 ns write-through
memory cache (256 KB 12 ns required for 486DX 50 MHz).
- No math coprocessor socket ("J", "K", and "Upgrade" models
already have a math coprocessor as part of 486DX).
- Type "G" accepts either 486SX or 487SX processor.
- 24 bit DMA; 10-12 MHz.
- Dual path memory design (Dual Bus Interleave). Allows processor
and busmasters to access memory concurrently though two paths.
- 20 MB per second data transfer support (for MCA bus).
Base 2 / Type 2
| "H" / Upgrade | 486SX 25 MHz | (announced Oct 1991) |
| "L" / Upgrade | 486DX2 50/25 MHz | (announced April 1992) |
- No Level 2 cache socket on complex.
- Math coprocessor socket on "H" model only to add 80487 math
coprocessor or to add a 486DX2 50/25 MHz upgrade chip which has an
integrated math coprocessor.
- 24 bit DMA. High speed 25 MHz DMA is now synchronous with the 486.
- Faster bus arbitration (than Base 1) for busmasters to increase
performance.
- Memory controller supports both interleaved (higher performance
-pairs of SIMMs) and non-interleaved memory (allows single SIMMs).
- 20 MB per second data transfer support (for MCA bus).
Base 3 / Type 3
| "M" / Upgrade | 486DX 50 MHz | (announced April 1992) |
- 40 MB per second streaming data transfer support. This is an
advanced Micro Channel I/O controller that provides faster data
transfer rates to increase performance.
- Error Checking and Correcting (ECC) memory controller which will
automatically correct any single bit errors on the fly (98% of
memory errors are single bit); all 2 bit errors are found which
halt system; some 3 and 4 bit errors are found which halt system;
single bit errors are logged with optional software (NetFinity)
and multiple bit errors are logged in NVRAM.
- 256KB Level 2 memory cache (write-through) is standard.
- High speed 20 MHz DMA; 32 bit DMA so it can use DMA to directly
address all memory; DMA supports Subsystem Control Block.
- Faster bus arbitration (than Base 1) for busmaster performance.
- Enhanced dual path memory design (Dual Bus Interleave). Although
Base 1 allows both the processor and busmasters to access memory
concurrently through two paths, the Base 3 and 4 has
buffers at both paths to provide better performance. Also the
buffer on the adapter side (I/O buffer) uses packet data transfers
for writes. This means 16 bytes are collected and this packet is
written in one cycle to memory as opposed to writing for every 4
bytes received (as with unbuffered systems).
- Subsystem Control Block enabled (see definition).
- Vital Product Data support. Allows software (LAN Network
Manager, LAN Mgmt Utilities/2) to obtain a unique serial number
(identifier) on the processor complex which is in ROM.
- Synchronous Channel Check support (see definition).
- Data bus parity support (see definition).
- A logging facility is provided (for ECC or system errors).
Base 4 / Type 4
| "N" / Upgrade | 486DX2 66/33 MHz | (announced Sept 1993) |
| "P" / Upgrade | Pentium 60 MHz | (announced Aug 1993) |
| "Q" / Upgrade | Pentium 66 MHz | (announced Sept 1993) |
| "Y" / Upgrade | Pentium 90/60 MHz | (announced Oct 1994) |
- SynchroStreamTM controller which
uses IBM's most advanced technology packaging to integrate 5 major chips
(memory, I/O, DMA controllers, FIFO buffers, ECC logic) into one chip.
This technology allows the high-speed interconnects and large
streaming pipes that form the SynchroStream engine to provide
state-of-the-art performance. The SynchroSteam controller
synchronizes data traveling between major subsystems and allows it
to stream in parallel, at full bandwidth, to each subsystem
concurrently.
- 40 MB per second streaming data transfer support.
- Error Checking and Correcting (ECC) memory controller which will
automatically correct any single bit errors on the fly (98% of
memory errors are single bit); all 2 bit errors are found which
halt system; some 3 and 4 bit errors are found which halt system;
single bit errors are logged with optional software (NetFinity)
and multiple bit errors are logged in NVRAM.
- 256 MB memory addressability (Base 1, 2, and 3 is 64 MB memory
addressability).
- 256 KB Level 2 memory cache (write-back) is standard on Pentium
models. 128 KB Level 2 memory cache (write-back) is standard on
486DX2 models.
- High speed 20 MHz DMA; 32 bit DMA so it can use DMA to directly
address all memory; DMA supports Subsystem Control Block.
- Faster bus arbitration (than Base 1) for busmaster performance.
Enhanced dual path memory design (Dual Bus Interleave).
- Although Base 1 allows both the processor and busmasters to
access memory concurrently through two paths, the Base 3 and 4 has
buffers at both paths to provide better performance. Also the
buffer on the adapter side (I/O buffer) uses packet data transfers
for writes. This means 16 Bytes are collected and this packet is
written in one cycle to memory as opposed to writing for every 4
bytes received (as with unbuffered systems).
- Subsystem Control Block enabled (see definition)
- Enhanced Vital Product Data support. Allows software (LAN
Network Manager, LAN Mgmt Utilities/2) to obtain a unique serial
number (identifier) on the processor complex which is in ROM (like
Base 3). Also provides unique ID (model/submodel),
type/model/serial number, manufacturing ID, planar FRU number, and
planar part number.
- Synchronous Channel Check support (see definition).
- Data bus parity support (definition below).
- A logging facility is provided (for ECC or system errors).
Definitions
Subsystem Control Block provides for the enhanced transfer of
command, data, and status information between busmasters (and
between busmasters and the system processor) to give increased
performance. Capabilities such as command chaining, data chaining,
and block data moves frees the processor from waiting for command
completion before issuing the next command and frees the processor
for other tasks while a busmaster operates in parallel. Adapters
and device drivers must support this feature (many do today).
Synchronous Channel Check support provides for the signaling of
errors synchronously with the transfer in progress. Adapters and
device drivers must be designed to support this feature (none do
today).
Data bus parity support provides for the verification of correct
data as it is transferred between the processor and memory and
over the Micro Channel. All data moved between individual
components on the Processor Complex use this feature (processor,
memory controller DMA, Micro Channel controller).
Adapters that support this feature:
IBM 32 bit MCA busmasters that support 40 MB/sec streaming:
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