Group 3 POS Registers

Group 3 POS Register 2 (Hex 0102)
Group 3 POS Register 3 (Hex 0103)
Group 3 POS Register 4 (Hex 0104)
Group 3 POS Register 5 (Hex 0105)


Group 3 POS Register 2 (Hex 0102)

This register is used to configure the high-speed parallel port (LPT A).

+-----------------------------------------------+
|  7  |  6  |  5  |  4  |  3  |  2  |  1  |  0  |
|-----+-----+-----+-----+-----+-----+-----+-----|
|  R  |  R  | DIA |  R  |  P  | DP  |  F  | ENA |
+-----------------------------------------------+
 DIA: Diagnostic mode
 P:   Port parity enable
 DP:  Channel data-parity enable
 F:   Fairness enable
 ENA: Enable
 R:   Reserved

DIA The diagnostic-mode bit is used in testing the high-speed parallel port. When the bit is set to 1, the parallel port is placed in the diagnostic mode. When the bit is set to 0, the parallel port is in the normal operating mode.

P The port-parity-enable bit controls whether the parallel port uses parity checking across the parallel port connector. When the bit is set to 1, the parallel port uses parity checking; when the bit is set to 0, parity checking is not performed and the parity bit is not generated.

DP The channel-data-parity-enable bit controls whether the parallel port uses data parity across the system channel. When the bit is set to 1, the parallel port uses data-parity procedures for all transfers across the system channel; when the bit is set to 0, data parity is not used.

F The fairness bit determines how controller for parallel port A participates in the arbitration process on the system channel. When fairness is enabled, the controller goes to the inactive state, when preempted, to allow other bus masters an equitable amount of bus time. When this bit is set to 1, fairness is enabled; when this bit is set to 0, fairness is disabled.

Note: Fairness should be enabled to prevent the controller from monopolizing the system bus.

ENA The enable bit enables and disables the parallel port A. When this bit and bit 4 of POS Register 4 (in group 3) are set to 1, parallel port A is enabled; when this bit is set to 0, the parallel port is disabled.


Group 3 POS Register 3 (Hex 0103)

This register is reserved.

+-----------------------------------------------+
|  7  |  6  |  5  |  4  |  3  |  2  |  1  |  0  |
|-----------------------------------------------|
|                  Reserved                     |
+-----------------------------------------------+

Group 3 POS Register 4 (Hex 0104)

This read/write register is used to configure the high-speed parallel port.

+-----------------------------------------------+
|  7  |  6  |  5  |  4  |  3  |  2  |  1  |  0  |
|-----+-----------+-----+-----------------------|
| BID |    SEL    | PP  |       Arb Level       |
+-----------------------------------------------+
 BID: Bidirectional disable
 SEL: Address select
 PP:  Parallel port A enable

BID The disable-bidirectional-mode fit controls whether parallel port A is configured as a bidirectional parallel port (extended mode) or unidirectional parallel port (sometimes called the compatible mode). When this bit is set to 1, the parallel port is a output only. When the bit is set to 0, the parallel port is bidirectional. The default is bidirectional mode.

SEL The parallel-port-select bits configure parallel port A on the system board.

Parallel Port A Select Bits

Bits
6 5
AssignmentAddress
(hex)
Int.
Level
0 0Parallel 103BC-03BF*7
0 1Parallel 20378-037D7
1 0Parallel 30278-027D7
1 1Parallel 41378-137D7
* For DMA operations, the addresses are hex 1278-127D.

PP The enable-parallel-port bit enables and disables parallel port A on the system board. When this bit and the enable bit (bit 0 in POS Register 2 of group 3) are set to 1, parallel port A is enabled. When either bit is set to 0, the parallel port is disabled.

Note: Disabling the system board functions does not disable their interrupt request signals. Therefore, the interrupts must be disabled individually before the device is disabled.

Arb Level This four-bit field determines the arbitration level used by parallel port A.


Group 3 POS Register 5 (Hex 0105)

This register is used to manage channel checks caused by the high-speed parallel port.

+-----------------------------------------------+
|  7  |  6  |  5  |  4  |  3  |  2  |  1  |  0  |
|-----+-----------------------------------------|
| CHK |                Reserved                 |
+-----------------------------------------------+
 CHK: Channel check

CHK The channel-check bit is set to 0 by the parallel port to indicate that it has generated a channel check. The condition is reset by setting this bit to 1.

Content created and/or collected by:
Louis Ohland, Peter Wendt, William Walsh, David Beem, Tatsuo Sunagawa, Jim Shorney, Tim Clarke, Kevin Bowling, Tomáš Slavotínek, and many others.

Ardent Tool of Capitalism - MAD Edition! is maintained by Tomáš Slavotínek.
Last update: 23 May 2022 - Changes & Credits | Legal Info & Contact