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Disclaimer
Intro
PCI (and ISA) for Desktop Systems
PCI (and Micro Channel) for Server Systems
Differences Between PCI and Micro Channel at the Card Connector
Similar Features Supported by PCI and MicroChannel
PCI Strengths
Micro Channel Strengths
Copyright © International Business Machines Corporation 1995.
First edition (April 1995)
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PCI/Micro Channel White Paper
A group of companies led by Compaq, Digital, Intel, IBM and NCR developed
the PCI Local Bus. The goal was to provide a common system board bus that could
be used in personal computers from laptops to servers. It was envisioned as a
local system board bus that would serve as a common design point, supporting
different system processors as the various processors evolved over time. This
is much like operating systems, which have defined Application Program
Interfaces (APIs) so that applications need not change with each generation of
the operating system. The PCI Local Bus would serve as a common hardware
interface that would not change with different versions of microprocessors.
The group defined PCI to support the high-performance basic system I/O
devices such as a graphics adapter, hardfile controller, and/or LAN adapter. In
the original definition these would be mounted on the planar, and communicate
through the PCI bus. Current I/O buses (ISA, EISA, and Micro Channel) would be
used to attach pluggable features to configure the system for the desired use.
The first release of the PCI specification was made available in June of
1992.
The PCI Special Interest Group (SIG) soon realized that the PCI bus needed
the capability of supporting connectors. For example, display controller
evolution doesn't necessarily match planar development, so providing for an
upgrade of the display controller became a requirement. The next release of the
PCI specification (revision 2.0 in April of 1993) included upgrade capability
through expansion connectors. The expansion board design, drawing heavily on
Micro Channel technology, was a size that would be least disruptive to the
physical package of systems containing ISA, EISA, or Micro Channel I/O
boards.
The PCI Bus operates on 32 or 64 bits of data at a clock speed of 33 MHz.
This yields a local bus performance of 132MB per second for 4-byte transfers
and 264MB per second for 8-byte transfers.
The PCI bus has been widely accepted in the PC industry in the three years
since its first release. There are now over 300 companies in the PCI SIG that
produce over 300 products as either direct connections or expansion cards for
the PCI bus.
In contrast, IBM developed the Micro Channel in the mid 80's as a technology
revolution from the ISA bus. Limited performance, lack of bus-master
capability, rows of jumpers and switches for setup, and poor electrical
characteristics all made an alternative to the ISA bus necessary. IBM announced
the Personal System/2 machines using Micro Channel technology in April of 1987.
The first release of Micro Channel technology supported basic 8-, 16-, and
32-bit data transfers operating at 10 MHz . This yielded a 20MB-per-second
throughput for 4-byte transfers. In addition, the data transfers could be
initiated by the system processor or by bus-master I/O devices that offload
work from the system processor. IBM added data streaming to the Micro Channel
architecture when higher data rates were required. With performance of up to
80MB per second, Micro Channel technology is more than just a viable
alternative to ISA. There are instances where it is the only alternative
capable of doing the job.
PCI (and ISA) for Desktop Systems
With the wide acceptance of the PCI bus, we anticipate that the majority of
PCI desktop systems shipped in 1995 will use PCI as their local bus and ISA or
MC as the I/O expansion bus. A typical desktop system can benefit from a PCI
local bus, particularly when compared to an ISA system. PCI offers improved
display performance by completing a 4-byte write in two bus clocks (when the
bus is parked at the host bridge). With both the display controller and the
hardfile controller attached to the PCI bus, the remaining I/O bus traffic can
be supported on an ISA bus. A wide selection of inexpensive ISA I/O cards are
available. There will be exceptions, but PCI and ISA can handle the majority of
desktop system I/O requirements.
PCI (and Micro Channel) for Server Systems
Most servers will support the PCI bus because of its performance and wide
industry acceptance. In addition, most servers will support an existing bus
(ISA, EISA, or Micro Channel). The bandwidth of 40MB-per-second streaming Micro
Channel cards has been a valuable asset in existing PC servers. It's desirable
to continue support of this capability in addition to the PCI bus. As an
example, a server may need to connect to a number of local area networks. Each
adapter will require high bandwidth, but the limited expansion capability of
PCI means that an alternative high-performance bus -- the Micro Channel bus --
is required. The combination of PCI and Micro Channel is a natural fit in
systems that require not only high processor performance but also extensive I/O
efficiency.
Differences Between PCI and Micro Channel at the Card Connector
| Item |
PCI |
Micro Channel |
| Address/Data |
multiplexed |
separate buses |
| Address size |
32- & 64-bit |
32-bit |
| Data size |
32- & 64-bit |
32-bit for basic cycle
64-bit data streaming |
| Interrupts |
4 (one per device) |
11 |
| Arbitration |
central (Req/Gnt) |
distributed (assignable lvl) |
| Bus signals |
47 for a target
49 for a master |
117 for a slave
124 for a master |
| Pluggable boards per bus |
4 (at 33 MHz) |
8 max. |
| Extendible to identical bus |
yes |
no |
| Synchronous/asynchronous |
synchronous |
asynchronous for basic x-fer
synchronous for streaming |
| Voltages |
+5, +3.3, +12, -12 |
+5, +12, -12 |
| Maximum data rate |
132 MB (32-bit)
264 MB (64-bit) |
80 MB (32-bit streaming)
160 MB (64-bit streaming) |
| Retry termination |
yes |
no |
| DMA slave support |
no |
yes |
| Lock support |
yes |
no |
| Caching of bus memory |
yes |
no |
| Multiple arb. levels per device |
no |
yes |
Similar Features Supported by PCI and Micro Channel
Parity: PCI has a single parity bit that covers the address/data bus
plus the command or byte enables. Micro Channel has parity per byte on both the
address and data bus.
Multiple masters: PCI supports bus masters with a REQ/GNT signal pair
for each master and expansion connector. The number of masters supported is
system-arbiter-dependent. Micro Channel architecture supports 16 arbitration
levels with distributed arbitration.
Bus-master preemption: PCI masters have a latency timer that limits
their bus ownership time when another master is requesting bus usage. The
latency timer is set when the device is configured. Micro Channel allows the
master to use the bus for up to 7.8 microseconds after another device requests
use of the bus.
Auto-initialization of devices: PCI supports auto-configuring of
devices through a 256-byte configuration address space. Micro Channel supports
auto-configuration through the Programmable Option Select (POS) registers. The
base POS registers support 4 bytes. The extension supports up to 128KB of
device-specific space.
Block data transfers: Both buses support the transfer of a
contiguous block of data following an address. This improves the data-transfer
rate for the buses.
PCI Strengths
A bus master requires only 49 signals, which supports implementations on
small logic chips. The multiplexed address/data bus is a significant
contributor to the low number of signals.
The PCI connector supports 3.3-volt power to the card, making the migration
to higher-density and lower-power technologies easier.
The high data rate and low latency are a benefit to display updates. A
4-byte write can be completed in two clock periods when the bus is parked at
the host bridge. Fast processors can make use of Byte Merging and Combining of
consecutive write operations also.
The maximum number of pluggable boards on a PCI bus is limited to four when
the bus is running at 33 MHz. If the number of pluggable boards is more
important than bus data rate, the bus clock frequency can be reduced to
increase the number of pluggable boards. The 33-MHz clock period of 30
nanoseconds is divided into four parts (signal valid time - 11 ns, signal setup
time - 7 ns, clock skew - 2 ns, and signal propagation time - 10 ns). When the
clock frequency is reduced to 25 MHz the clock period increases from 30 ns to
40 ns. The 10-ns clock period increase can be added to the propagation delay to
provide a total propagation delay of 20 ns, which can be used to support more
pluggable boards. When lowering the clock frequency is unacceptable, additional
pluggable boards can be supported by adding a PCI-to-PCI bridge. The second PCI
bus can support four additional pluggable boards.
Most buses limit the signal loading on the board to one circuit (driver,
receiver, or transceiver). The same is true for PCI. If there is a need for
multiple devices on a board, a PCI-to-PCI bridge can be put on the board to
support multiple devices.
Micro Channel Strengths
Eleven interrupts are available to the I/O device. Micro Channel setup can
select the interrupt to be used by the device (devices usually support
selection from a group of four interrupts). The device has the option of using
more than one interrupt.
DMA slaves are supported. The centralized DMA controller function supports
reduced-cost I/O cards (DMA slaves), which reduce the load on the system
processor.
Distributed arbitration allows the device to access the bus on more than one
arbitration priority level. DMA slave devices have used this to support
multiple devices on a card.
A bus master can retain use of the bus (with BURST) to transfer data to
multiple targets or multiple transfers to the same target.
Micro Channel supports up to eight pluggable cards on the bus.
Low-cost simple I/O devices are supported. A simple 1-byte-wide device using
only I/O address space can be implemented using 32 of the Micro Channel bus
signals.
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