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Source: SA23-2647-00 RS/6000 Hardware Technical Reference - Micro Channel Architecture, 1st Ed., 1990
Note: Pat Bowld's book "Micro Channel
Architecture - Revolution in Personal Computing" is NOT on the Internet Archive
or Google Books. But... SA23-2647-00 looks to be the / a source document that
she pulled quite a bit of text from. The PS/2 and RS/6000 both use MCA, but the
RS/6000 system uses a byte-order that is the reverse of the PS/2, so it has to
reverse the byte order when using the MCA bus. BUT... once the poodle-faking is
done, both systems use the Holy Bus... v/r, LFO
The data transfer procedures are used to transfer data
between a controlling master and the selected slave. The
three types of data transfer procedures are:
Each procedure defines the signal sequences and the signal
timing specifications used in the procedure. Data transfer
occurs only during the data transfer cycle defined by the
procedure. A cycle is one or more data transfers, occurring
during the time between the leading edge of -CMD and the
trailing edge of -CMD. The data transfer cycle address
selects either an I/O-address-space address or a
memory-address-space address, under the control of M/-IO.
A controlling master or a DMA slave can drive -BURST, to
indicate to the central arbitration control point that one
or more data transfer cycles will be used before the EOT
occurs. Refer to "Burst Transfer" on page 1-25 for more
information. This section describes each procedure, the
signal sequence for each procedure and the signal timing
specifications.
The system technical manuals contain the signal sequence and
timing specifications for matched-memory signals and
auxiliary-video signals.
Exception condition handling and reporting descriptions are
contained in "Exception Condition Reporting and Handling" on
page 1-83.
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