Processor Complex Pinout

Introduction
Physical Interface
Connector Pinouts
   Connector 1 (Rear)
   Connector 2 (Front)
Signal Descriptions
   Micro Channel Signals
   Memory Signals
   Other Signals
   Power

The pinout reverse engineered (328 pins, oof!) and drawings created by Tomáš Slavotínek.


Introduction

The Processor Complex interface (also known as "Processor Interface Connection") consists of Micro Channel signals (some of which are shared with the planar I/O bus), memory signals, control signals, power supply lines, and some other connections.

A list of machines that use the Processor Complex interface can be found HERE.


Physical Interface

The physical interface consists of two identical connectors. The connector used is an unique variant of the Micro Channel connector with 2x40 + 2x42 pins (82 usable positions = 164 usable pins; or 84 positions including the space taken by the physical key). This gives a total of 328 usable pins for both connectors. The connectors are placed in-line with no gap in between, touching each other by the shorter 2x40-pin section (rotated by 180°).

Connector Type

Burndy Computerbus CEE2X82S-8Z14, CEE2X82SP-8Z14 (-V8Z14) or AMP 646215-1


Connector Pinouts

The "component side" (A) and "solder side" (B) refers to an installed processor card.
The "Rear" arrow points towards the back side of the planar/system unit.

Connector 1 (Rear)

Micro Channel (and planar I/O) bus connections + some memory signals.
Some signals still unknown.

PinSignalPinSignal
B01MA AB 0A01MA AB 1
B02MA AB 2A02MA AB 3
B03GNDA03MA AB 4
B04MA AB 5A04MA AB 6
B05MA AB 7A05+5 Vdc
B06MA AB 8A06MA AB 9
B07-DPARENA07RAS A4 1/3
B08DPAR(0)A08RAS A4 0/2
B09GNDA09RAS A3 1/3
B10DPAR(1)A10+5 Vdc
B11DPAR(2)A11RAS A3 0/2
B12Unknown (out)A12-RESET
B13UnknownA13Unknown
B14-CD DS 16A14CD CHRDY
B15GNDA15-CD DS 32
B1614.3 MHz OSCA16GND
B17GNDA17-CD SFDBK
B18MADE 24A18A 23
B19A 11A19A 22
B20A 10A20A 21
B21A 09A21+5 Vdc
B22GNDA22A 20
B23A 08A23A 19
B24A 07A24A 18
B25A 06A25A 17
B26GNDA26WE AB
B27A 05A27A 16
B28A 04A28A 15
B29A 03A29A 14
B30GNDA30+5 Vdc
B31A 02A31A 13
B32A 01A32A 12
B33A 00A33-PREEMPT
B34GNDA34-BURST
B35-ADLA35-CMD
B36-CHRDYRTNA36GND
B37ARB 00A37ARB 01
B38ARB 02A38ARB 03
B39GNDA39ARB/-GNT
B40-TCA40+5 Vdc
B41-S0A41-S1
B42M/-IOA42D 00
B43PHYSICAL KEYA43PHYSICAL KEY
B44PHYSICAL KEYA44PHYSICAL KEY
B45D 01A45D 02
B46D 03A46+5 Vdc
B47GNDA47D 04
B48D 05A48D 06
B49D 07A49D 08
B50D 09A50GND
B51D 10A51D 11
B52D 12A52D 13
B53GNDA53D 14
B54D 15A54-SDR(0)
B55-SDR(1)A55-SD STROBE
B56-DS 16 RTNA56+5 Vdc
B57-REFRESHA57-SBHE
B58-CHCKA58-MSDR
B59GNDA59DPAR(3)
B60D 16A60+5 Vdc
B61D 17A61D 18
B62D 19A62D 20
B63D 21A63D 22
B64D 23A64GND
B65GNDA65D 24
B66D 25A66D 26
B67D 27A67D 28
B68D 29A68+5 Vdc
B69D 30A69D 31
B70A 24A70A 25
B71GNDA71A 26
B72A 27A72A 28
B73A 29A73A 30
B74A 31A74+5 Vdc
B75-BE 0A75-BE 1
B76-BE 2A76-BE 3
B77GNDA77TR 32
B78WE BBA78-DS 32 RTN
B79UnknownA79-IRQ 05
B80INTRA80+5 Vdc
B81Unknown (in?)A81-MMC
B82-MMC CMDA82Unknown
B83GNDA83MA AA 0
B84MA AA 1A84MA AA 2

Note: All "unknown" pins serve a purpose. There are no unused positions.
(in/out) indicates the direction of the signal from the processor card's point of view.


Connector 2 (Front)

Almost exclusively memory signals.

PinSignalPinSignal
B01MA AA 3A01MA AA 4
B02MA AA 5A02MA AA 6
B03GNDA03MA AA 7
B04MA AA 8A04MA AA 9
B05MA BB 0A05GND
B06MA BB 1A06MA BB 2
B07MA BB 3A07MA BB 4
B08GNDA08MA BB 5
B09MA BB 6A09MA BB 7
B10MA BB 8A10+5 Vdc
B11MA BB 9A11MA BA 0
B12MA BA 1A12MA BA 2
B13GNDA13MA BA 3
B14MA BA 4A14+5 Vdc
B15MA BA 5A15MA BA 6
B16MA BA 7A16MA BA 8
B17GNDA17MA BA 9
B18MD A 0A18+5 Vdc
B19MD A 1A19MD A 2
B20MD A 3A20MD A 4
B21GNDA21MD A 5
B22MD A 6A22MD A 7
B23MD A 8A23MD A 9
B24MD A 10A24GND
B25MD A 11A25MD A 12
B26MD A 13A26MD A 14
B27GNDA27MD A 15
B28MD A 16A28MD A 17
B29MD A 18A29MD A 19
B30MD A 20A30+5 Vdc
B31MD A 21A31MD A 22
B32MD A 23A32MD A 24
B33GNDA33MD A 25
B34MD A 26A34MD A 27
B35MD A 28A35MD A 29
B36MD A 30A36GND
B37MD A 31A37MDP A 0
B38MDP A 1A38MDP A 2
B39GNDA39MDP A 3
B40BS A 0A40+5 Vdc
B41PHYSICAL KEYA41PHYSICAL KEY
B42PHYSICAL KEYA42PHYSICAL KEY
B43BS A 1A43BS A 2
B44BS A 3 / MA A 11 *A44WE AA
B45WE BAA45RAS A1 0/2
B46RAS A1 1/3A46+5 Vdc
B47GNDA47RAS B1 0/2
B48RAS B1 1/3A48RAS A2 0/2
B49RAS A2 1/3A49RAS B2 0/2
B50RAS B2 1/3A50GND
B51CAS A 0A51CAS A 1
B52CAS A 2A52CAS A 3
B53GNDA53CAS B 0
B54CAS B 1A54CAS B 2
B55CAS B 3A55-CASP A / MA A 10 *
B56-CASP B / MA B 10 *A56+5 Vdc
B57MD B 0A57MD B 1
B58MD B 2A58MD B 3
B59GNDA59MD B 4
B60MD B 5A60+5 Vdc
B61MD B 6A61MD B 7
B62MD B 8A62MD B 9
B63MD B 10A63MD B 11
B64MD B 12A64GND
B65GNDA65MD B 13
B66MD B 14A66MD B 15
B67MD B 16A67MD B 17
B68MD B 18A68+5 Vdc
B69MD B 19A69MD B 20
B70MD B 21A70MD B 22
B71GNDA71MD B 23
B72MD B 24A72MD B 25
B73MD B 26A73MD B 27
B74MD B 28A74GND
B75MD B 29A75MD B 30
B76MD B 31A76MDP B 0
B77GNDA77MDP B 1
B78MDP B 2A78MDP B 3
B79BS B 0A79BS B 1
B80BS B 2A80+5 Vdc
B81BS B 3 / MA B 11 *A81ECC PD
B82RAS B3 0/2A82RAS B4 1/3
B83GNDA83RAS B4 0/2
B84MMCR RTNA84RAS B3 1/3

Notes:
* The marked pins are multiplexed on the Type 4 complex to realize support for 16 and 32 MB ECC memory modules that require 11x11 or 12x10 addressing. SIMMs with a non-standard pinout are required!


Signal Descriptions

The Processor Complex interface consists of:

Throughout this page, a minus sign (-) in front of a signal name indicates that the signal is active when it is at a low-voltage level. When no minus sign appears, the signal is active when it is at a high-voltage level. For example, -CMD specifies the signal is active low. Also, ARB/-GNT is in the ARB state when it is at a high level and is in the -GNT state when it is at a low level.

All of the logic signal lines are transistor-transistor logic (TTL) compatible.

Micro Channel Signals

32-bit Micro Channel interface. All Micro Channel Signals are described HERE.

Note: Some of the channel data, address, and control signals are shared with the planar I/O bus. This bus interconnects all the on-planar features - external I/O ports, FDC, Op Panel interface, memory Presence Detect lines, etc.

Memory Signals

Two 32-bit interfaces (64-bit total) between the memory controller on the processor card and the memory SIMMs on the planar. The memory is organized as two independent memory banks - Bank A and Bank B. Each bank then consists of two SIMM pairs:

  • Pair A - SIMM slots 1 and 2
  • Pair B - SIMM slots 3 and 4

Some signals are unique to each SIMM slot, some are shared within the individual SIMM pairs, and some are shared by the entire bank.

MA bp xx: Memory Address Bit xx for Bank b Pair p

MD b xx: Memory Data Bit xx for Bank b

MDP b x: Memory Data Parity Bit x for Bank b

BS b x: Block Select x for Bank b

WE bp: Write Enable for Bank b Pair p

CAS b x: Column Address Strobe x for Bank b

-CASP b: Column Address Strobe Parity for Bank b

RAS bs x/y: Row Address Strobe x and y for Bank b Slot s

ECC PD: Error-Correcting Code Presence Detect: This signal is driven by the planar logic and it's the negative AND of -ECC PD from each SIMM connector (pin 48). If any of the SIMM slots is occupied by a ECC memory module, this signal is driven high. Low otherwise.

Other Signals

-RESET: -System Reset: This signal is driven by the planar logic.

INTR: Interrupt Request: This signal is driven by the planar interrupt controller and is connected to the INTR pin of the main processor.

MMCR RTN: Matched Memory Cycle Request Return: This signal is driven by the planar logic and it's the AND of -MMCR from each channel connector.

Power

The only voltage available on the Processor Complex interface is +5 V DC. Pins supplying this voltage are located on the A side of the connectors, together with some ground pins. A majority of the ground pins is then located on the B side.

Any other voltages are generated locally on the processor board, from the +5 V DC supply rail.

Content created and/or collected by:
Louis F. Ohland, Peter H. Wendt, David L. Beem, William R. Walsh, Tatsuo Sunagawa, Tomáš Slavotínek, Jim Shorney, Tim N. Clarke, Kevin Bowling, and many others.

Ardent Tool of Capitalism is maintained by Tomáš Slavotínek.
Last update: 07 Dec 2024 - Changelog | About | Legal & Contact