8642 Processor Cards

SMP 166 MHz Processor Card
Processor Upgrades
Cache Architecture


Up to six processor cards can be installed onto the multiprocessor bus on the Server 720. Each processor card has the following functions:

  • Intel Pentium processor. Currently announced are 100, 133, and 166 MHz options.
  • 512 KB of write-back L2 cache
  • 192 byte of L3 (victim) cache
  • Bus interface and control logic

Processor card types:

  • 100 MHz (P/N 94G2724) - For all OS other than NW 4.1 SMP
  • 100 MHz (P/N 94G6054) - For NetWare 4.1 SMP only
  • 133 MHz (P/N 94G6055) - For all OS other than NW 4.1 SMP
  • 133 MHz (P/N 94G6056) - For NetWare 4.1 SMP only

Note: Of a maximum of six processors in the 720, the number of earlier 166 MHz standard processor boards is limited to two. This only applies to processor boards delivered as standard processors. This limit of two 166 MHz standard processors is due to a limitation of the power supply. These 166 MHz boards draw current from the 5 V power supply and not the 3.3 V supply as do the other processor boards. All 166 MHz optional processors boards (P/N 94G6057) are 3.3 V. They may be added without a restriction.

SMP 166 MHz Processor Card FRU P/N 76H3545 (or 76H3248?), P/N 94G6057(R)

J2-5 test header pads?
P1 2x10-pin header pads
P2 JTAG connector pads
U1,2 Corollary DPX 94C101B
U3 Corollary CBC 94C102B
U4 MCM62995AFN15 16Kx16 SRAM (TAG?)
U6-9 64Kx16 SRAM (L2 cache)
U10 unknown
U14 66.6667? MHz osc
? 3x5-pin jumper block

U6-9 MCM67C618FN9 or IBM 041813PPL-12 64G2525 64Kx16 SRAM (L2 cache)

Note: Some component types and reference designators were taken from processor cards other than the SMP 166 MHz variant. More data and verification needed!

Processor Upgrades

Important: Please understand Where/what is the difference between FRU - OPT - MKT P/Ns

MKT P/N FRU P/N Product Name
94G5352 76H7147 Server 720 200 MHz Processor Option II
94G6054 75H9684 Server 720 SMP 100 MHz Processor Option II
94G6054(R) 76H6850 Server 720 SMP 100 MHz Proc
94G6055 75H9686 Server 720 SMP 133 MHz Processor Option
94G6056 75H9688 Server 720 SMP 133 MHz Processor Option II
94G6056 75H9688 Server 720 SMP 133 MHz Processor Option II
94G6057 75H9690 Server 720 SMP 166 MHz Processor Option II
94G6057(R) 76H3545 Server 720 SMP 166 MHz Proc

Server 720 SMP 133 MHz Processor Opt. II (RETAIN: #H132301)

Important Information if you have installed the IBM PC Server 720 SMP Option II.

OBI Processor Card P/N
94G6054 PC Server 720 SMP 100 MHz Proc. Option II
94G6056 PC Server 720 SMP 133 MHz Proc. Option II
94G6057 PC Server 720 SMP 166 MHz Proc. Option II

The above Options are only supported with 'Novell NetWare V-3.12 V-4.1' or SMP operating system.

The origin 100 MHz processor card (or cards) installed in the server must be removed before installing a server option. If you are not sure if one or more of the processor cards inside the server are one of the original 100 MHz processor cards, do the following:

  1. Remove a processor card from the server and locate the FRU P/N printed on a label on the card.
  2. If the FRU P/N is 71G0692, the processor card is not compatible with the new processor option and must be removed before installing the new processor option. see Note 1.)
  3. If the FRU P/N is not 71G0692, reinstall the processor card.
  4. Repeat steps 1 and 2 with all of the other processor cards currently in the server.

Once you have completed steps 1 through 4 for all of the processor cards currently installed in the server, then you can install the new processor option.

Note 1.) The processor card 76H6852 (71G0692) should be exchanged with FRU P/N 76H6850 (75H9648) if NetWare SMP is installed. Do not replace the card if OS/2 or any other Operating System is installed, because this processor card FRU P/N 76H6850 (75H9684) is designed to work with NetWare SMP only!


System Unit (PC Server 720 - Type 8642)
Micro Channel Models OZO, 1Z0, 2ZS, 4ZS

P54C-100/66 MHz Processor Card 76H6852
P54C-133 MHz Processor Card 75H9688
P54C-133 MHz Processor Card 75H9686
P54C-166 MHz Processor Card
   (Model 0EN, 0E1, 2E1) (75H9690)
   (all six jumpers are default set to NORM
   right side - outer position) 76H3545
P54C-200 MHz Processor Card 76H7147
SMP 200 MHz Processor Upgrade Opt-II 76H2572
   (Any combination 100-200 MHz up to 6
   proc./syst. possible.

Testing processors


If the performance has degraded on the PC Server 720 with more than one processor, or if the operating system does not detect all of the processors, then one or more processors may be failing.

  • Multiprocessor Error IP: 1xxDSxx or FP: 1xxDSxx on LCD panel.
  • Test Error EP: 106S appears on the LCD panel.
  • Error 0095xxxx appears on the display or the LCD panel.

Note: A Test Error EP: 106S, or Multiprocessor Error IP: 1xxDSxx or FP: 1xxDSxx, where (S) is the slot number of the processor card, indicates the slot number of the failing processor card or indicates the slot number of a good processor card that is reporting the error caused by the failing processor card.

Follow this procedure to isolate the failing processor:

  1. Power off the system and connect an ASCII terminal or laptop to the serial port. Use the serial port on the Server 720 which connects to the internal ribbon cable labeled P2.
  2. Reboot using the System Diagnostic Diskette.
  3. Select option 3: Extended ROM Resident Diagnostics.
  4. Note the slot number of the failing processor.
  5. Replace the failing processor and rerun the diagnostics.

Refer to the IBM PC Server HMM, publication number S30H-2501-01, page 377, for additional information on error codes.
The PC Server 720 Extended ROM Resident Diagnostics can isolate a failing processor card in any of the six(6) processor slots.

Cache Architecture

To ensure highest performance, the processor and cache are designed to operate with zero wait states. In addition, all processor cards are fully symmetrical for main memory access, I/O, and interrupts. This means that no single processor can be a bottleneck, for example, through having to process all the hardware interrupts in the system.

In an SMP system, some data might be held within multiple processor caches. If this data is modified by one processor, then it needs to be updated in the other caches before another processor operates on out-of-date information. This is called cache coherency and is handled by the MESI (Modified, Exclusive, Shared or Invalid) protocol.

Each of the PC Server 720 processor cards has three levels of private cache. Lower level caches are typically very fast but also very expensive. In general, the closer to the processor, the faster and more expensive the cache will be.

The first, or L1 cache, is built into the Pentium processor. This is th first place the processor will look when it needs its next instruction or piece of data to operate on. If this data is not contained in L1, the system next searches the second level, or L2 cache. If the information is found in either of these locations, the processor can continue without incurring wait states. However, if the information is still not available from the L1 cache or the L2 cache, the processor will need to obtain it from main memory. Depending on the speed of the memory subsystem, it may take a few clock cycles for this transaction to complete.

When the information is retrieved from main memory, it is stored in a free cache location. If there are no free locations, then the new data replaces the least frequently used information currently stored in the cache.

Since the Server 720 uses performance-boosting write-back cache, this least frequently used data may have already been modified by the CPU and must, therefore be evicted first or written back to memory. In most systems, the processor would have to wait for that data to be written out before it could bring in a new line of cache.

The Server 720 takes the unique approach of adding a small six-line L3 cache to each processor card. The 720's L3 or victim cache allows that data to be quickly cleared from L2 to L3 making room for new information and allowing modified data to be written to main memory later during free bus cycles. In addition, this information is still available to be quickly accessed if needed in future cycles.

This approach improves the overall cache hit ratio with little additional cost while saving significant clock cycles during the write back or eviction process. Access to data in any of these three caches can be accomplished with zero wait states so the processor continues work on its applications without wasting time.

It may seem more effective to simply make the L2 cache much larger to increase the cache-hit ratio directly. However, since the cache memory tends to be expensive, the size of the L2 cache is carefully chosen to provide a high cache-hit rate at reasonable cost. As it takes time to search the cache for the required information, it is also possible to have a cache that is too large and too slow to respond to each request.

The carefully balanced cache design of the 720, however, provides for a high percentage of zero-wait states processing resulting in excellent multiprocessor performance.

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Louis F. Ohland, Peter H. Wendt, David L. Beem, William R. Walsh, Tatsuo Sunagawa, Tomáš Slavotínek, Jim Shorney, Tim N. Clarke, Kevin Bowling, and many others.

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