Version 1.0.3
September, 1996
3.0 Miami Functional Description
Appendix E. Miami Errata and Pass 2 Changes
This document describes the function and implementation of the Miami Micro Channel Interface Controller
AIB application interface bus ADL address decode latch APIO appended i/o BCR byte count register BMAR bus master address register BMCDB bus master channel descriptor block BMCMD bus master command register CAR card address register CBSP command busy status port CCR channel control register CDB channel descriptor block CFE Common Front End CIO common input/output COR clear on read DCR design change request DMA direct memory access DPR dual ported RAM DRAM dynamic RAM ECC error correction code EI interrupt enable EOT end of transmission G giga- (1X10E_7) GAID gate array identification HSBR host-slave base address register ICT in-circuit test IDD I[dd], or Source Current IRQ interrupt request ISP interrupt status port IV interrupt vector L_AD local address bus LBBAR local bus base address register LBPE local bus parity/exception register LAP list address pointer LBI local bus interface LLC linked list chaining LSB least significant bit LSSD level sensitive scan design M mega- (1X10E+6) MCA Micro Channel Architecture MCI Micro Channel interface MSB most significant bit MSDR multiplexed streaming data request NMI nonmaskable interrupt NOP no operation POS programmable option select PMI processor memory interface PS post status PTR problem tracking report RAM random access memory ROM read only memory RSR reset status register SAR system address register SBHE system byte high enable SCB storage control block SCP subsystem control port SDR streaming data request SIMM single in-line memory module SIR source identification register SRAM static RAM VPD vital product data XPOS extended POS address register
The sections that follow give a general overview of Miami and its features.
The Micro Channel host accesses the Local Bus through the shared memory window or through a Micro Channel I/O location.
The Micro Channel Bus Master interface consists of two Bus Master channels addressable from the Local Bus. Each channel utilizes a 128-byte intermediate buffer between resident memory and the Micro Channel. Buffering of data allows the Bus Master channel to sustain 100-ns streaming data on the Micro Channel.
The Miami chip interfaces a high-speed, 80 MByte/sec Micro Channel interface to a high-speed Local Bus. This Local Bus is based on a 25 MHz 80960 processor bus, and has a maximum theoretical bandwidth of 100 MBytes. Data rates achieved by Miami on the Local Bus are dependent on size of the transfer and speed of the Local Bus slave. Assuming a 64-byte burst to a zero wait state slave, the data rate is 84 MBytes/sec. For memory or slaves requiring wait states, the data rate may be much lower.
The data rate sustained on the Micro Channel is also dependent on the speed of the Local Bus slave. With the intermediate data buffering provided internal to Miami, 80 MBytes/sec can be sustained for an absolute minimum of 128 bytes.
The following table shows the maximum throughput between the Local Bus and the Micro Channel for Bus Master accesses, assuming 40 or 80 Mbyte/sec streaming data on the Micro Channel, and 50 Mbyte/sec (1 wait state) or 100 Mbyte/sec (0 wait state) Local Bus accesses. Table 1
Table 1. Miami Bus Master Performance (in MBytes/sec)
+===========================+===========================+================+ | Micro Channel Speed | Local Bus Speed | Throughput | +===========================+===========================+================+ | 40 | 50 | 32 | +---------------------------+---------------------------+----------------+ | 80 | 50 | 41 | +---------------------------+---------------------------+----------------+ | 40 | 100 | 40 | +---------------------------+---------------------------+----------------+ | 80 | 100 | 55 | +---------------------------+---------------------------+----------------+
Miami provides the following RAS support:
Note that Miami does not generate and check parity internally, only at the chip boundaries.
The following documents provide supporting documentation to the Miami Component Description:
The following sections provide a description of the Miami chip:
Miami functions as an interface between two buses: the Micro Channel and a Local Bus. Miami acts both as a slave and as a master on each bus, transferring data in both directions between the two buses.
All data transactions between the two buses are subject to intermediate buffering within Miami Intermediate buffering of the data improves the efficiency of transfers on both buses. The master and slave functions for each bus, as well as the interface to intermediate buffering from either bus, are located in separate interfaces: the Micro Channel Interface and the Local Bus Interface. These interfaces and their relationship to intermediate buffering is shown in Figure 1
Figure 1. Functional Block Diagram
+-------------------------------+
| +---------+ |
| | | |
| | | |
+-------------+ | | CH1 | |
| +---------+ | | +----->| BUFFER |<------+ |
| | | | | | | | | |
| | MICRO | | | | | | | |
<--->| CHANNEL |<---------+ +---------+ | |
| | BUS | | | | | |
| | MASTER | | | | +---------+ | |
| | | | | | | | | |
M | +---------+ | | | | | | |
I | | | | | CH2 | | |
C | | | +----->| BUFFER |<------+ |
R | | | | | | |
O | | | | | | |
| MICRO | | +---------+ | |
C | CHANNEL | | | |
H | INTERFACE | | +---------+ | | +--------------+
A | (MCI) | | | |-+ | | | +--------+ |
N | | | | SLAVE | |-+ | | | | | |
N | | | | WRITE | | | +-------->| LOCAL | |
E | | | +----->| BUFFER +---------------->| BUS |<---->
L | | | | | 0, 1, 2 | | | +---------+ MASTER | | L
| +---------+ | | | | | | | | | | | | | O
| | | | | | +---------+ | | | | | +--------+ | C
| | MICRO | | | | +---------+ | | | | | A
<--->| CHANNEL +----------+ +---------+ | | | LOCAL | L
| | SLAVE | | | | | | BUS |
| | INTFC |<---------+ +---------+ | | | INTERFACE | B
| | | | | | | |-+ | | | (LIB) | U
| +---------+ | | | | SLAVE | |-+ | | | | S
+-------------+ | | | READ | | |-+ | | +--------------+
| +------+ BUFFER | | | | | |
| | 0-3 |<------+ |
| | | | | | |
| +---------+ | | | |
| +---------+ | | |
| +---------+ | |
| +---------+ |
| INTERNAL BUFFERS |
| |
+-------------------------------+
A brief description of each fundamental block in Miami is given below:
Table 2. Miami Pin Description--Micro Channel Signals (Alphabetical Order)
+==============+=========+===================================================+ | Name | Type | Description | +==============+=========+===================================================+ | A31-A0 | I/O | Address bits 31-0 are used by the Bus Master to | | | | address memory and I/O slaves. These signals are | | | | also used to select the Miami chip for slave | | | | operations. | +--------------+---------+---------------------------------------------------+ | -ADL | I/O | -Address Decode Latch is used by the slave | | | | interface to latch the Micro Channel address | | | | during a Micro Channel transfer. This signal is | | | | driven by the Bus Master interface as an address | | | | latching signal for a Micro Channel slave. | +--------------+---------+---------------------------------------------------+ | APAR3-APAR0 | I/O | Address Parity Bits 3-0 are used by the Bus | | | | Master to generate address parity on the Micro | | | | Channel. They are used by the slave interface to | | | | check address parity on the Micro Channel. | +--------------+---------+---------------------------------------------------+ | -APAREN | I/O | -Address Parity Enable is used by the slave | | | | interface to detect the presence of valid address | | | | parity on the Micro Channel. This signal is | | | | driven by the Bus Master interface to indicate | | | | the presence of valid address parity on the Micro | | | | Channel. | +--------------+---------+---------------------------------------------------+ | ARB3-ARB0 | I/O | Arbitration Bus is used by the Bus Master | | | | interface during arbitration to present its | | | | arbitration level to the Micro Channel. | +--------------+---------+---------------------------------------------------+ | ARB/-GNT | I | Arbitrate/-Grant is used by the Bus Master | | | | interface to determine if the Micro Channel is in | | | | an arbitration state or if the bus has been | | | | granted. | +--------------+---------+---------------------------------------------------+ | -BE3 - -BE0 | I/O | -Byte Enables 3-0 are used by the slave interface | | | | to detect which bytes are valid in the 32-bit | | | | Micro Channel data bus. This signal is driven by | | | | the Bus Master interface to indicate which bytes | | | | are valid on the 32-bit Micro Channel data bus. | +--------------+---------+---------------------------------------------------+ | -BURST | I/O | -Burst is driven by the Bus Master interface to | | | | indicate to the bus that the master will perform | | | | one or more consecutive data transfer cycles. | +--------------+---------+---------------------------------------------------+ | CD CHRDY | O | Channel Ready is driven inactive by the slave | | | | interface to allow additional time to complete | | | | the current data transfer. | +--------------+---------+---------------------------------------------------+ | -CD DS 16 | O | -Card Data Size 16 is driven by the slave | | | | interface together with -CD DS 32 to indicate a | | | | 16-bit or 32-bit data port. | +--------------+---------+---------------------------------------------------+ | -CD DS 32 | O | -Card Data Size 32 is driven by the slave | | | | interface together with -CD DS 16 to indicate a | | | | 32-bit data port. | +--------------+---------+---------------------------------------------------+ | -CD SETUP | I | -Card Setup is used together with A2-A0 to select | | | | the POS registers. | +--------------+---------+---------------------------------------------------+ | -CD SFDBK | O | -Card Selected Feedback is driven by the slave | | | | interface to acknowledge that it has received a | | | | valid address decode. | +--------------+---------+---------------------------------------------------+ | -CHCK | I/O | -Channel Check is used by the slave interface to | | | | notify the current Micro Channel Bus Master that | | | | an exception condition has occurred during the | | | | current transfer. This signal is used by the Bus | | | | Master interface to detect an exception condition | | | | on the Micro Channel. | +--------------+---------+---------------------------------------------------+ | CHRDYRTN | I | Channel Ready Return is received by the Bus | | | | Master interface to detect the need for | | | | additional time to complete the current data | | | | transfer. | +--------------+---------+---------------------------------------------------+ | CHRESET | I | Channel Reset is used to reset Miami from the | | | | Micro Channel. | +--------------+---------+---------------------------------------------------+ | -CMD | I/O | -Command is used by the Bus Master interface to | | | | define when data is valid on the Micro Channel | | | | for a basic transfer cycle. This signal indicates | | | | to the slave interface how long data is valid. | +--------------+---------+---------------------------------------------------+ | D31-D0 | I/O | Data bits 31-0 are used to transfer data between | | | | Miami and the Micro Channel. | +--------------+---------+---------------------------------------------------+ | DPAR3-DPAR0 | I/O | Data Parity Bits 3-0 are used by both the slave | | | | and Bus Master interface to generate and check | | | | data parity on the Micro Channel. | +--------------+---------+---------------------------------------------------+ | -DPAREN | I/O | -Data Parity Enable is used by the transmitting | | | | interface (master or slave) to indicate the | | | | presence of valid data parity on the Micro | | | | Channel. This signal is used by the receiving | | | | interface (master or slave) to detect the | | | | presence of valid data parity on the Micro | | | | Channel. | +--------------+---------+---------------------------------------------------+ | -DS 16 RTN | I | -Data Size 16 Return is received by the Bus | | | | Master interface to detect that a 16-bit data | | | | port has been selected. | +--------------+---------+---------------------------------------------------+ | -DS 32 RTN | I | -Data Size 32 Return is received by the bus | | | | master interface to detect that a 32-bit data | | | | port has been selected. | +--------------+---------+---------------------------------------------------+ | -IRQ A,B,C,D | O | -Interrupt Requests a,b,c,d One of these signals | | | | is used by Miami to interrupt the Micro Channel. | | | | The Interrupt Request signal is selected in POS. | +--------------+---------+---------------------------------------------------+ | MADE 24 | I/O | Memory Address Enable 24 is used by the slave | | | | interface to distinguish a Micro Channel address | | | | below 16 Mbytes. This signal is driven by the Bus | | | | Master interface to indicate that the current | | | | Micro Channel address is below 16 Mbytes. | +--------------+---------+---------------------------------------------------+ | M/-IO | I/O | Memory/-Input Output is used by both the slave | | | | and Bus Master interfaces to distinguish memory | | | | or I/O cycles on the Micro Channel. | +--------------+---------+---------------------------------------------------+ | -MSDR | I/O | -Multiplexed Streaming Data Request is driven by | | | | the slave interface to indicate the ability to do | | | | 64-bit streaming data. This signal is received by | | | | the Bus Master interface to detect the ability to | | | | do 64-bit streaming data. | +--------------+---------+---------------------------------------------------+ | -PREEMPT | I/O | -Preempt is used by the Bus Master interface to | | | | request an arbitration cycle on the Micro | | | | Channel. | +--------------+---------+---------------------------------------------------+ | -REFRESH | I | -Refresh is used to indicate that a memory | | | | refresh operation is in progress on the Micro | | | | Channel. | +--------------+---------+---------------------------------------------------+ | -S0,-S1 | I/O | -Status is used by the Bus Master interface to | | | | indicate a Bus Master read or write on the Micro | | | | Channel. Status is used by the slave interface to | | | | determine whether a read or write cycle is taking | | | | place on the Micro Channel. | +--------------+---------+---------------------------------------------------+ | -SBHE | I/O | -System Byte High Enable is used by the Bus | | | | Master interface to indicate and enable transfers | | | | on D8-D15 of the Micro Channel. This signal is | | | | used by the slave interface to determine whether | | | | data is enabled on D8-D15 of the Micro Channel. | +--------------+---------+---------------------------------------------------+ | -SDR(1,0) | I/O | -Streaming Data Requests 1,0 are used by the | | | | slave interface to request a streaming data | | | | transfer. These signals are received by the Bus | | | | Master interface to detect a request for | | | | streaming data. | +--------------+---------+---------------------------------------------------+ | -SD STROBE | I/O | -Streaming Data Strobe is received by the slave | | | | interface to clock data on and off the data bus | | | | during streaming data transfers. This signal is | | | | driven by the Bus Master interface. | +--------------+---------+---------------------------------------------------+ | -SFDBKRTN | I | -Selected Feedback Return is received by the Bus | | | | Master interface to detect that a slave device | | | | has been selected. | +--------------+---------+---------------------------------------------------+ | TR 32 | O | Translate 32 is driven inactive by the Bus Master | | | | interface to indicate that the Bus Master | | | | interface is performing data steering. | +--------------+---------+---------------------------------------------------+Table 3. Miami Pin Description--Local Bus Signals
+==============+=========+===================================================+ | Name | Type | Description | +==============+=========+===================================================+ | L_AD31:0 | I/O | Local Bus Address/Data bits 31-0 are used for | | | | both address generation and data transfer on the | | | | Local Bus. The address is driven by Miami when it | | | | owns the Local Bus, and by the resident processor | | | | when the processor owns the Local Bus. Data is | | | | driven by the device providing the data. | +--------------+---------+---------------------------------------------------+ | -L_ADS | I/O | -Address Strobe indicates valid address and the | | | | start of a new bus access. This signal is driven | | | | by Miami as a master and received by Miami as a | | | | slave. | +--------------+---------+---------------------------------------------------+ | L_ADP3:0 | I/O | Local Bus Parity Bits 3-0 are used to generate | | | | and check address and data parity on the Local | | | | Bus. | +--------------+---------+---------------------------------------------------+ | -L_BE3:0 | I/O | -Local Bus Byte Enables select which of the four | | | | bytes addressed are active during an access. | | | | These signals are driven by Miami as a master and | | | | received by Miami as a slave. | +--------------+---------+---------------------------------------------------+ | L_W/-R | I/O | Write/-Read is used for Local Bus transfers to | | | | establish the direction of data flow. This signal | | | | is driven by the current local Bus Master. | +--------------+---------+---------------------------------------------------+ | -L_READY | I/O | -L_READY indicates that data on the AD lines can | | | | be sampled or removed. If this signal is not | | | | asserted during the data cycle of a transfer, the | | | | data cycle is extended to the next cycle by | | | | inserting a wait state. This signal is driven by | | | | Miami as a slave and received by Miami as a | | | | master. | +--------------+---------+---------------------------------------------------+ | -L_BLAST | I/O | -Burst Last is driven by Miami as a master to | | | | indicate the last transfer of a burst access. | | | | This signal is received by Miami as a slave. | | | | Miami does not support burst transfers as a | | | | slave. | +--------------+---------+---------------------------------------------------+ | -MSTRREQ | O | -Master Request is driven by Miami to request use | | | | of the Local Bus for transfers to and from Bus | | | | Master Channels, 1 and 2. | +--------------+---------+---------------------------------------------------+ | -SLVEREQ | O | -Slave Request is driven by Miami to request use | | | | of the Local Bus for transfers to and from the | | | | Micro Channel slave buffers. | +--------------+---------+---------------------------------------------------+ | -MSTRACK | I | -Master Acknowledge is received by Miami to | | | | detect that a Master Request has been granted. | +--------------+---------+---------------------------------------------------+ | -SLVEACK | I | -Slave Acknowledge is received by Miami to detect | | | | that a Slave Request has been granted. | +--------------+---------+---------------------------------------------------+ | INT(3-0) | O | Interrupt lines 3-0 are driven by Miami to form | | | | an encoded interrupt to the Local Bus. | +--------------+---------+---------------------------------------------------+ | -L_EXCPT | I/O | -L_EXCPT signal is received by Miami when it is | | | | the Local Bus Master to detect Local Bus | | | | exceptions (e.g. ECC or Local Bus data parity | | | | error). This signal is driven by Miami as a local | | | | bus slave when a data parity error is detected. | +--------------+---------+---------------------------------------------------+ | -WDOG | I | -Watchdog Timeout signal is received by Miami | | | | asynchronously to detect watchdog timeout | | | | exceptions. | +--------------+---------+---------------------------------------------------+Table 4. Miami Pin Description--Clocks and Miscellaneous
+==============+=========+===================================================+ | Name | Type | Description | +==============+=========+===================================================+ | -16/32 | I | -16/32-Bit Detect is received by Miami to | | DETECT(1) | | determine whether it is operating in a 16- or | | | | 32-bit Micro Channel slot. | +--------------+---------+---------------------------------------------------+ | 25 MHz OSC | I | 25 MHZ Oscillator provides a 25 MHz clock to | | | | Miami | +--------------+---------+---------------------------------------------------+ | 40 MHz OSC | I | 40 MHZ Oscillator provides a 40 MHz clock to | | | | Miami | +--------------+---------+---------------------------------------------------+ | +BMSTREN | O | +Bus Master Enable is used by the Bus Master | | | | interface to turn around transceivers external to | | | | Miami during a Bus Master cycle. | +--------------+---------+---------------------------------------------------+ | -CMD CLK(1) | I | -Cmd Clock is a clock signal used in latching | | | | data on basic transfer cycles. This pin is tied | | | | directly to -CMD on the Miami side of the | | | | external control transceiver. | +--------------+---------+---------------------------------------------------+ | -CMDRSTOUT | O | -Command Reset Out is driven low by Miami to | | | | indicate that a reset is being performed. this | | | | signal is driven synchronous to the CFE clock. | +--------------+---------+---------------------------------------------------+ | COMP1,2 | I | Compensation Resistors 1 and 2 are used to | | | | compensate for process variance in the off-chip | | | | drivers. COMP1 compensates for the Micro Channel | | | | drivers; COMP2 for the Local Bus. These inputs | | | | should each be pulled up with a 909 ohm resistor | | | | (1% tolerance). | +--------------+---------+---------------------------------------------------+ | -ICT | I | -In-Circuit Test places the chip in I/O Mapping | | | | Mode for in-circuit testing. This pin should be | | | | pulled to Vcc (inactive) with a 1k ohm resistor. | +--------------+---------+---------------------------------------------------+ | +RAMTSTCLK(1)| I | +RAM Test Clock is used for testing internal RAM | | | | Macros. For normal operation, this pin should be | | | | pulled to GND (inactive) through an inverter with | | | | input pulled to Vcc. | +--------------+---------+---------------------------------------------------+ | -SDSTRCLK(1) | I | -Streaming Data Strobe Clock is a clock signal | | | | used in latching data on streaming data transfer | | | | cycles. This pin is tied directly to -SD STROBE | | | | on the Miami side of the external control | | | | transceiver. | +--------------+---------+---------------------------------------------------+ | TEST_A,B,C(1)| I | LSSD Test Clocks A,B,C are used by Miami to | | | | generate LSSD test clocks. These pins should be | | | | pulled to V[cc] (inactive) through 1K ohm | | | | resistors. | +--------------+---------+---------------------------------------------------+ | -TEST MODE(2)| I | Test Mode is used together with -MSTRACK AND | | | | -SLVEACK to put the chip in test mode. This mode | | | | is used for three mutually exclusive purposes: | | | | Static IDD testing, tristating the drivers, and | | | | RAM macro isolation. This pin should be pulled to | | | | Vcc through a 1K ohm resistor for normal | | | | operation. | +--------------+---------+---------------------------------------------------+ | Notes: | | | | See Figure 2 and Figure 3 | | See Appendix D, "Other Test Modes" | | | +----------------------------------------------------------------------------+Figure 2. Miami Hookup Diagram
+---------------------------------------+ +-----------------------------------------------+
| LOCAL BUS SIGNALS | | MICRO CHANNEL SIGNALS |
| +------------------|-|------------------+ |
| +-+ | | | +==============+ | +---+ |
| | | | | | | ARB/-GNT | | | | |
| |A| | +==============+ | | | -CD_SETUP | | | | |
| |R|<-----------------+ -MSTRREQ | | | | CHRDYRTN | | | | |
| |B| | | -SLVEREQ | | | | CHRESET | | | | |
| |I| | +==============+ | | | -DS 16 RTN |<-----------------------+ | |
| |T| | +==============+ | | | -DS 32 RTN | | | | |
| |E|----------------->| -MSTRACK | | | | -REFRESH | | | | |
| |R| | | -SLVEACK | | | | -SFDBKRTN | | | | |
| | | | +==============+ | | +==============+ | | | |
| +-+ 10Kohms | | | | A31-A0 | | | | |
| +5V +-/\/\/--+ | +==============+ | | | APAR3-0 | | | M | |
| +-+ (optional)| | | L_AD31:0 | | | | -APAREN | | | I | |
| | |<------------+--->| L_ADP3:0 | | | | ARB3-ARB0 | | | C | |
| | | | | -L_BE3:0 | | | | -BE3-BE0 | | | R | |
| | | | | -L_W/-R | | | | -BURST | | | O | |
| | | | +==============+ | | | -CHCK | | | | |
| | | | | | | D31-0 | | | C | |
| | |+5V +-/\/\/--+ | | | | DPAR3-0 |<---------------------->| H | |
| | | 5Kohms | | +==============+ | | | -DPAREN | | | A | |
| |L| | | | -L_BLAST | | | | MADE 24 | | | N | |
| |O|<------------+--->| -L_EXCPT | | | | M/-IO | | | N | |
| |C| | | | -L_ADS | | | | -MSDR | | | E | |
| |A| 10Kohms | | | -L_READY | | | | -PREEMPT | | | L | |
| |L|GND <-/\/\/--+ | +==============+ | | | -SBHE | | +--/\/\/-----+ +5V | | |
| | | | | | | -SDR(1,0) | | | 20Kohms | | |
| |B| | | | +==============+ | | | | |
| |U| | | | | -MSDR |<---+------------------>| | |
| |S| | | | | -SDR1 | | | | |
| | | | +==============+ | | | -SDR2 | | | | |
| | | | | INT(3) | | | +==============+ | +--/\/\/-----+ +5V | | |
| | |<-----------------+ INT(2) | | | | CD CHRDY | | | 10Kohms | | |
| | | | | INT(1) | | | | -CD DS 16 | | | | | |
| | | | | INT(0) | | | | -CD DS 32 +----+------------------>| | |
| | |<------------+ | +==============+ | | | -CD SFDBK | | +---+ |
| | | | | | | | -IRQ A,B,C,D | | +--/\/\/-----+ +5V |
| +-+ | | | | | TR 32 | | | 10Kohms +-----+ |
| | | | | +==============+ | +----------+ | | |
| +------------+ | | | | | -ADL |<--------------+----->| | |
| | | | | +==============+ | | | -S1-0 | | | | | |
| | INTERRUPT |--|--->| -WDOG | | | | -SD STROBE | | +--/\/\/---|-+ +5V| 7 | |
| | CONTROLLER | | | +==============+ | | +==============+ | | 10Kohms | | 4 | |
| | | | | | | | -CMD |<---+----------|----->| A | |
| +------------+ | | | | +==============+ | | | | L | |
+-----------------|--|------------------+ +------------------|--|----------|------| S |-+
| | | | | | 2 |
+-----------------|--|---------------------------------------|--|----------|------| 4 |-+
| | | +==============+ +==============+ | | | | 5 | |
| OSCILLATORS +----+ -CMDRSTOUT | | -CMD CLK +----+ | | | |
| +--------+ | +==============+ +==============+ | | | | |
| | 25 MHz +--/\/\/----+ 25 MHz OSC | | -SDSTRCLK +---------------+ | | |
| +--------+ | +==============+ +==============+ | | | |
| | 40 MHz +--/\/\/----+ 40 MHz OSC | | BMSTREN +--------------------->| DIR | |
| +--------+ | +==============+ +==============+ | +-----+ |
| | | 16/32 DETECT |<-----See Figure 3, 16/32 |
| | +==============+ | Bit Detect Diagram |
| 1Kohms | +==============+ | |
| +5V +--/\/\/---------+ TEST_A | | |
| 1Kohms | +==============+ | |
| +5V +--/\/\/---------+ TEST_B | | |
| 1Kohms | +==============+ | |
| +5V +--/\/\/---------+ TEST_C | | |
| 1Kohms |\ | +==============+ +==============+ | 909ohms |
| +5V +--/\/\/--+ >o---+ +RAMTSTCLK | | COMP1 +-------/\/\/--+ +5V |
| 1Kohms |/ | +==============+ +==============+ | 909ohms |
| +5V +--/\/\/---------+ -TESTMODE | | COMP2 +-------/\/\/--+ +5V |
| 1Kohms | +==============+ +==============+ | |
| +5v +--/\/\/---------+ -ICT | | |
| | +==============+ | |
| +---------------------------------------+ |
| CLOCK AND MISCELLANEOUS SIGNALS |
+-----------------------------------------------------------------------------------------+
Figure 3. 16/32 Bit Detect Hookup Diagram
+12V DETECT
(TO MICRO CHANNEL
PIN A77)
A
| +12V
| A
+----+ LM393 | 10K
10K | | +-------------+ | OHMS
OHMS | | | | | +---/\/\/---> +5V
+-/\/\/-+ | | + 8+---+ |
| | | |\ | |
V | 3| | \ | |
+-----------|+ \ 1 | | -16/32 DETECT
2| | >-----------------+----------->
+5V +-----------|- / | (See Figure 2, MIAMI
A | | | / | Hookup Diagram)
| 3.3K | | |/ |
| OHMS | | + 4+---+
+-/\/\/-+ | | | |
| | +-------------+ |
| | |
+----+ V
| GND
10K |
OHMS |
+-/\/\/-+
|
V
The following sections provide a description of each register in the Miami chip. A complete listing of Miami registers is available in Appendix B. "Miami Registers"
There are two different reset modes that affect the Miami registers.
Table 5. Local Bus Addressable Registers
+============+==========+=========+=======+=====+=============+=======+=====+ | Name | Section | Micro | Width | R/W | Local Bus | Data | R/W | | | | Channel | | | AddressBus | Field | | | | | Address | | | | Size | | +============+==========+=========+=======+=====+=============+=======+=====+ | POS_SETUP1 | 2.4.1 | - | - | - | 1FFA0000 | 32 | R | +------------+----------+---------+-------+-----+-------------+-------+-----+ | POS_SETUP2 | 2.4.2 | - | - | - | 1FFA0004 | 32 | R | +------------+----------+---------+-------+-----+-------------+-------+-----+ | GAID | 2.4.3 | 0A | 8 | R | 1FFA0008 | 8 | R | +------------+----------+---------+-------+-----+-------------+-------+-----+ | CRDID | 2.4.4 | - | - | - | 1FFA000C | 16 | R/W | +------------+----------+---------+-------+-----+-------------+-------+-----+ | PROC_CFG | 2.4.5 | - | - | - | 1FFA0010 | 14 | R/W | +------------+----------+---------+-------+-----+-------------+-------+-----+ | RSR | 2.4.6 | - | - | - | 1FFA0014 | 1 | R | +------------+----------+---------+-------+-----+-------------+-------+-----+ | XPOS | 2.4.7 | - | - | - | 1FFA0018 | 16 | R/W | +------------+----------+---------+-------+-----+-------------+-------+-----+ | NMI | 2.4.8 | 0B | 8 | R/W | 1FFA001C | 1 | R | +------------+----------+---------+-------+-----+-------------+-------+-----+ | LBPE | 2.4.9 | - | - | - | 1FFA0020 | 3 | R | +------------+----------+---------+-------+-----+-------------+-------+-----+ | LBBAR | 2.4.10 | - | - | - | 1FFA0024 | 12 | R/W | +------------+----------+---------+-------+-----+-------------+-------+-----+ | COMMAND | 2.4.11 | 00-03 | 32 | R/W | 1FFA2000 | 32 | R | +------------+----------+---------+-------+-----+-------------+-------+-----+ | ATTN | 2.4.12 | 04 | 8 | R/W | 1FFA2004 | 8 | R | +------------+----------+---------+-------+-----+-------------+-------+-----+ | SCP | 2.4.13 | 05 | 8 | R/W | 1FFA2008 | 8 | R | +------------+----------+---------+-------+-----+-------------+-------+-----+ | ISP | 2.4.14 | 06 | 8 | R | 1FFA200C | 8 | R/W | +------------+----------+---------+-------+-----+-------------+-------+-----+ | CBSP | 2.4.15 | 07 | 8 | R | 1FFA2010 | 8 | R/W | +------------+----------+---------+-------+-----+-------------+-------+-----+ | SIR | 2.4.16 | - | - | - | 1FFA2014 | 16 | R/W | +------------+----------+---------+-------+-----+-------------+-------+-----+ | BMCDB1 | 2.4.17 | - | - | - | 1FFA3000-14 | 32 | R/W | +------------+----------+---------+-------+-----+-------------+-------+-----+ | CAR1 | 2.4.17.1 | - | - | - | 1FFA3000 | 32 | R/W | +------------+----------+---------+-------+-----+-------------+-------+-----+ | SAR1 | 2.4.17.2 | - | - | - | 1FFA3004 | 32 | R/W | +------------+----------+---------+-------+-----+-------------+-------+-----+ | BCR1 | 2.4.17.3 | - | - | - | 1FFA3008 | 20 | R/W | +------------+----------+---------+-------+-----+-------------+-------+-----+ | CCR1 | 2.4.17.4 | - | - | - | 1FFA300C | 11 | R/W | +------------+----------+---------+-------+-----+-------------+-------+-----+ | BMAR1 | 2.4.17.5 | - | - | - | 1FFA3010 | 16 | R/W | +------------+----------+---------+-------+-----+-------------+-------+-----+ | LAP1 | 2.4.17.6 | - | - | - | 1FFA3014 | 32 | R/W | +------------+----------+---------+-------+-----+-------------+-------+-----+ | BMSTAT1 | 2.4.18 | - | - | - | 1FFA3018 | 10 | R | +------------+----------+---------+-------+-----+-------------+-------+-----+ | BMCMD1 | 2.4.19 | - | - | - | 1FFA301C | 2 | R/W | +------------+----------+---------+-------+-----+-------------+-------+-----+ | BMCDB2 | 2.4.17 | - | - | - | 1FFA4000-14 | 32 | R/W | +------------+----------+---------+-------+-----+-------------+-------+-----+ | CAR2 | 2.4.17.1 | - | - | - | 1FFA4000 | 32 | R/W | +------------+----------+---------+-------+-----+-------------+-------+-----+ | SAR2 | 2.4.17.2 | - | - | - | 1FFA4004 | 32 | R/W | +------------+----------+---------+-------+-----+-------------+-------+-----+ | BCR2 | 2.4.17.3 | - | - | - | 1FFA4008 | 20 | R/W | +------------+----------+---------+-------+-----+-------------+-------+-----+ | CCR2 | 2.4.17.4 | - | - | - | 1FFA400C | 11 | R/W | +------------+----------+---------+-------+-----+-------------+-------+-----+ | BMAR2 | 2.4.17.5 | - | - | - | 1FFA4010 | 16 | R/W | +------------+----------+---------+-------+-----+-------------+-------+-----+ | LAP2 | 2.4.17.6 | - | - | - | 1FFA4014 | 32 | R/W | +------------+----------+---------+-------+-----+-------------+-------+-----+ | BMSTAT2 | 2.4.18 | - | - | - | 1FFA4018 | 10 | R | +------------+----------+---------+-------+-----+-------------+-------+-----+ | BMCMD2 | 2.4.19 | - | - | - | 1FFA401C | 2 | R/W | +------------+----------+---------+-------+-----+-------------+-------+-----+
(Local Bus Address = 1FFA0000 h) 32-bit rd only
(POS Addresses = 2-5) 8-bit rd/wr
POS 2
(7)7 (0)0
+---+---+---+---+---+---+---+---+
| L1| L0| R3| R2| R1| R0| W1| CE|
+---+---+---+---+---+---+---+---+
POS 3
(15)7 (8)0
+---+---+---+---+---+---+---+---+
| SE| SF| PE| AS| B3| B2| B1| B0|
+---+---+---+---+---+---+---+---+
POS 4
(23)7 (16)0
+---+---+---+---+---+---+---+---+
|A31|A30|A29|A23|A22|A21|A20|CKE|
+---+---+---+---+---+---+---+---+
POS 5
(31)7 (24)0
+---+---+---+---+---+---+---+---+
| CK| CS|I15|I14|I13|MW2|MW1|MW0|
+---+---+---+---+---+---+---+---+
L1 L0 INTERRUPT LEVEL
_______ _________________
0 0 A
0 1 B
1 0 C
1 1 D
R3 R2 R1 R0 BASE ADDRESS
0 0 0 0 C0000 H
0 0 0 1 C2000 H *
0 0 1 0 C4000 H
0 0 1 1 C6000 H *
0 1 0 0 C8000 H << Default on Pwr Up
0 1 0 1 CA000 H *
0 1 1 0 CC000 H
0 1 1 1 CE000 H *
1 0 0 0 D0000 H
1 0 0 1 D2000 H *
1 0 1 0 D4000 H
1 0 1 1 D6000 H *
1 1 0 0 D8000 H
1 1 0 1 DA000 H *
1 1 1 0 DC000 H
1 1 1 1 DE000 H *
* 8 KByte window only
Power Up Reset: 0001 0010
Command Reset: SSSS SSSS
Power Up Reset: 0001 1100
Command Reset: SSSS SSSS
Power Up Reset: uuuu uuu0
Command Reset: SSSS SSSS
These bits are used together with POS 3A, Bits 7-5, to locate the I/O address on any 1 KByte boundary. More information on these additional bits is located in Section 2.4.2 , "POS Setup Register 2 (POS_SETUP2)"
MW2 MW1 MW0 MEMORY SIZE
0 0 0 512 Kbytes
0 0 1 1 Mbyte
0 1 0 2 Mbytes
0 1 1 4 Mbytes
1 0 0 8 Mbytes
1 0 1 16 Mbytes
1 1 0 32 Mbytes
1 1 1 64 Mbytes
Power Up Reset: 11uu uuuu
Command Reset: SSSS SSSS
POS 6 register also provides status for channel check conditions. This status is reset by writing this register to '00' hex. This resetting of the register can only be done through POS access.
(Local Bus Address = 1FFA0004 h) 32-bit rd only
(POS Addresses = Subaddr 100,101 h; POS 6,7) 8-bit rd/wr
POS 3A
(7)7 (0)0
+---+---+---+---+---+---+---+---+
|I12|I11|I10|A28|A27|A26|A25|A24|
+---+---+---+---+---+---+---+---+
POS 3B
(15)7 (8)0
+---+---+---+---+---+---+---+---+
|RSV|RSV|ADP|AL3|AL2|AL1|AL0| EN|
+---+---+---+---+---+---+---+---+
POS 6
(23)7 (16)0
+---+---+---+---+---+---+---+---+
| S7| S6| S5| S4| S3| S2| S1| S0|
+---+---+---+---+---+---+---+---+
POS 7
(31)7 (24)0
+---+---+---+---+---+---+---+---+
|S15|S14|S13|S12|S11|S10| S9| S8|
+---+---+---+---+---+---+---+---+
POS 6
(23)7 (16)0
+---+---+---+---+---+---+---+---+
|RSV|RSV|RSV|BDP|SDP|XST|CTO|IBE|
+---+---+---+---+---+---+---+---+
Power Up Reset: 1110 0000
Command Reset: SSSS SSSS
Power Up Reset: 000u uuu0
Command Reset: 00SS SSSS
Power Up Reset: uuuu uuuu
Command Reset: SSSS SSSS
Power Up Reset: uuuu uuuu
Command Reset: SSSS SSSS
(Local Bus Address = 1FFA0008 h) 32-bit rd only
(Micro Channel Address = Base + 0A h) 8-bit rd only
31 8 7 0
+-----------------------+-----------------------+
| RSVD | GATE ARRAY ID |
+-----------------------+-----------------------+
Revision Level 2.0 = 0000 0010
Power Up Reset: 0000 0010
Command Reset: 0000 0010
(Local Bus Address = 1FFA000C h) 32-bit rd/wr
31 16 15 0
+-----------------------+-----------------------+
| RSVD | CARD IDENTIFICATION |
+-----------------------+-----------------------+
Power Up Reset: 0000 0000 0000 0000
Command Reset: SSSS SSSS SSSS SSSS
(Local Bus Address = 1FFA0010 h) 32-bit rd/wr (bit 8 rd only)
15 14 13 8 7 5 0
+-----+---+---+---+---+---+---+-----------+---+---+---+---+---+
|RSVD | PT| CT|MSD| IE|LBP| 32| RSVD |MW2|MW1|MW0|EMW|E8K|
+-----+---+---+---+---+---+---+-----------+---+---+---+---+---+
MW2 MW1 MW0 WINDOW SIZE
0 0 0 512 Kbytes
0 0 1 1 Mbyte
0 1 0 2 Mbytes
0 1 1 4 Mbytes
1 0 0 8 Mbytes
1 0 1 16 Mbytes
1 1 0 32 Mbytes
1 1 1 64 Mbytes
Power Up Reset: 0000 0000 000u uu00
Command Reset: 0000 0000 000S SS00
(Local Bus Address = 1FFA0014 h) 32-bit rd only
31 1 0
+--------------------------------------------+---+
| RESERVED | RS|
+--------------------------------------------+---+
Power Up Reset: 0000 0000
Command Reset: 0000 0001
(Local Bus Address = 1FFA0018 h) 32-bit rd/wr
31 16 15 0
+-----------------------+-----------------------+
| POS EXTENDED ADDR | RSVD |
+-----------------------+-----------------------+
Power Up Reset: uuuu uuuu uuuu uuuu 0000 0000 0000 0000
Command Reset: SSSS SSSS SSSS SSSS 0000 0000 0000 0000
(Local Bus Address = 1FFA001C h) 32-bit rd only
(Micro Channel Address = Base + 0B h) 8-bit rd/wr
31 1 0
+--------------------------------------------+---+
| RESERVED |NMI|
+--------------------------------------------+---+
Power Up Reset: 0000 0000 0000 0000 0000 0000 0000 0000
Command Reset: 0000 0000 0000 0000 0000 0000 0000 0000
(Local Bus Address = 1FFA0020 h) 32-bit rd only
31 2 1 0
+--------------------------------------+--+--+--+
| RESERVED |MC|EX|LP|
+--------------------------------------+--+--+--+
Power Up Reset: 0000 0000 0000 0000 0000 0000 0000 0000
Command Reset: 0000 0000 0000 0000 0000 0000 0000 0000
(Local Bus Address = 1FFA0024 h) 32-bit rd/wr
31 20 19 0
+-----------------------+-----------------------+
| MEMORY ADDRESS | RESERVED |
+-----------------------+-----------------------+
Power Up Reset: uuuu uuuu uuuu 0000 0000 0000 0000 0000
Command Reset: SSSS SSSS SSSS 0000 0000 0000 0000 0000
(Local Bus Address = 1FFA2000 h) 32-bit rd only
(Micro Channel Address = Base + 00 h) 32-bit rd/wr
31 0
+------------------------------------------------+
| SCB COMMAND |
+------------------------------------------------+
Power Up Reset: uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu
Command Reset: SSSS SSSS SSSS SSSS SSSS SSSS SSSS SSSS
(Local Bus Address = 1FFA2004 h) 32-bit rd only
8-bit field defined
by SCB architecture
(Micro Channel Address = Base + 04 h) 8-bit rd/wr
7 4 3 0
+---------------+---------------+
| ATTN CODE | DEVICE NUMBER |
+---------------+---------------+
Valid attention codes are shown in Table 6
+==========+==========+==================+==================================+ | Attention| Device | Name | Description | | Code | Number | | | +==========+==========+==================+==================================+ | 0 | X | Reset Command | Request the subsystem to perform | | | | | Device Reset for the specified | | | | | device. | +----------+----------+------------------+----------------------------------+ | 1 | X | Immediate | Requests the subsystem to | | | | Command | execute the command contained in | | | | | the Command port. | +----------+----------+------------------+----------------------------------+ | 2 | X | | Reserved | +----------+----------+------------------+----------------------------------+ | 3 | X | Start Control | Requests the subsystem to | | | | Block Command | process the control block | | | | | pointed to by the address in the | | | | | Command port. | +----------+----------+------------------+----------------------------------+ | 4 | | Device Dependent | | +----------+----------+------------------+----------------------------------+ | 5-C | | | Reserved | +----------+----------+------------------+----------------------------------+ | D | 0-F | Move Mode | Used to signal request for Move | | | | Delivery | Mode command delivery. The | | | | | device number specifies the bit | | | | | to be set in the SIR. | +----------+----------+------------------+----------------------------------+ | E | 0 | End of Interrupt | Requests the subsystem to | | | | | perform one of the two interrupt | | | | | resetting commands. | +----------+----------+------------------+----------------------------------+ | F | | Device Dependent | | +----------+----------+------------------+----------------------------------+Note: 'X' = Don't Care. A blank in the Device Number equals unspecified
Power Up Reset: uuuu uuuu
Command Reset: SSSS SSSS
(Local Bus Address = 1FFA2008 h) 32-bit rd only
8-bit field defined
by SCB architecture
(Micro Channel Address = Base + 05 h) 8-bit rd/wr
7 0
+---+---+---+---+---+---+---+---+
|RST|COR| RR|RSV| SD| SD|DMA| EI|
+---+---+---+---+---+---+---+---+
Power Up Reset: 0000 0000
Command Reset: 1000 0000
(Local Bus Address = 1FFA200C h) 32-bit rd/wr
8-bit field defined
by SCB architecture
(Micro Channel Address = Base + 06 h) 8-bit rd only
7 4 3 0
+---------------+---------------+
| INT ID | DEVICE NUMBER |
+---------------+---------------+
Valid interrupt codes are shown in Table 7
Table 7. Interrupt Identifier Codes
+================+==========================================================+ | Hex Value | Interrupt Definition | +================+==========================================================+ | 0 | Reset Subsystem/Device Completed No Error | +----------------+----------------------------------------------------------+ | 1 | Control Block Command Completed No Error | +----------------+----------------------------------------------------------+ | 2 | Notify Event | +----------------+----------------------------------------------------------+ | 3 | Reserved | +----------------+----------------------------------------------------------+ | 4 | Reserved | +----------------+----------------------------------------------------------+ | 5 | Device Dependent | +----------------+----------------------------------------------------------+ | 6 | Inform Event | +----------------+----------------------------------------------------------+ | 7 | Hardware Failure Immediate Command or Hardware Control | +----------------+----------------------------------------------------------+ | 8 | Hardware Failure Control Block Command | +----------------+----------------------------------------------------------+ | 9 | Reserved | +----------------+----------------------------------------------------------+ | A | Immediate Command/Hardware Control Completed No Error | +----------------+----------------------------------------------------------+ | B | Reserved | +----------------+----------------------------------------------------------+ | C | Control Block Command Completed w/Error | +----------------+----------------------------------------------------------+ | D | Immediate Command/Hardware Control Completed w/Error | +----------------+----------------------------------------------------------+ | E | Command Rejected | +----------------+----------------------------------------------------------+ | F | Device Dependent | +----------------+----------------------------------------------------------+
Power Up Reset: uuuu uuuu
Command Reset: SSSS SSSS
(Local Bus Address = 1FFA2010 h) 32-bit rd/wr
8-bit field defined
by SCB architecture
(Micro Channel Address = Base + 07 h) 8-bit rd only
7 0
+---+---+---+---+---+---+---+---+
| ST| ST| ST|REJ| DD| DD| IV| B|
+---+---+---+---+---+---+---+---+
The resetting of this bit is under control of the Clear on Read Bit (Bit 6, SCP). The definition of this control bit is available in Section 2.4.13 , "Subsystem Control Port (SCP)" More information on the SCB and interrupt support is available in Section 3.3.2 , "Subsystem Control Block (SCB) Support"
Power Up Reset: 0000 0001
Command Reset: SSS0 SS01
By Local Bus definition, and independent of SCB architecture, the Source Identification Register is used to issue both general interrupts and end-of-transfer interrupts from the Micro Channel to the resident processor, saving status for these interrupts.
Bits in the SIR can only be set from the Micro Channel. Each bit is set through the Attention Port. Interrupts are generated by the logical OR of the bits in the SIR. A General Interrupt is generated by the logical OR of the lowest 8 bits in the register; an End-of-Data-Transfer Interrupt for the upper 8 bits in the register.
Bits in the SIR can only be reset from the Local Bus. Each bit is reset by writing a logical '0' to the corresponding bit location. Writes of '1' from the Local Bus to the SIR are ignored.
This manner of resetting bits allows the Micro Channel to generate interrupts to the resident processor through the SIR without losing interrupt status. More information on Local Bus interrupts is available in Section 3.1.5 , "Local Bus Interrupts" More information on the Subsystem Control Block (SCB) architecture is available in Section 3.3.2 , "Subsystem Control Block (SCB) Support"
(Local Bus Address = 1FFA2014 h) 32-bit rd/wr
16-bit field defined
by SCB architecture
(Micro Channel Address = Indirect Access through ATTN)
15 0
+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+
|E7|E6|E5|E4|E3|E2|E1|E0|I7|I6|I5|I4|I3|I2|I1|I0|
+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+
Power Up Reset: 0000 0000 0000 0000
Command Reset: 0000 0000 0000 0000
Each channel has a six-word channel descriptor block (CDB). This CDB is loadable from the Local Bus. The CDB register map is described in Table 8
Table 8. BMCDB Local Bus Register Map
+======================+============+============+ | CDB Register | Channel 1 | Channel 2 | +======================+============+============+ | Card Addr Register | 1FFA3000 | 1FFA4000 | | 31-0 | | | +----------------------+------------+------------+ | System Addr Register | 1FFA3004 | 1FFA4004 | | 31-0 | | | +----------------------+------------+------------+ | Byte Count Register | 1FFA3008 | 1FFA4008 | +----------------------+------------+------------+ | Channel Control | 1FFA300C | 1FFA400C | | Register | | | +----------------------+------------+------------+ | Bus Master Addr | 1FFA3010 | 1FFA4010 | | Register 31-0 | | | +----------------------+------------+------------+ | List Addr Pointer | 1FFA3014 | 1FFA4014 | | 31-0 | | | +----------------------+------------+------------+Register descriptions within the CDB are given in the following sections. All channel addresses are Local Bus addresses.
(Channel 1 Address = 1FFA3000 h) 32-bit rd/wr
(Channel 2 Address = 1FFA4000 h) 32-bit rd/wr
31 0
+------------------------------------------------+
| CARD ADDRESS |
+------------------------------------------------+
Power Up Reset: uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu
Command Reset: SSSS SSSS SSSS SSSS SSSS SSSS SSSS SSSS
(Channel 1 Address = 1FFA3004 h) 32-bit rd/wr
(Channel 2 Address = 1FFA4004 h) 32-bit rd/wr
31 0
+------------------------------------------------+
| SYSTEM ADDRESS |
+------------------------------------------------+
Power Up Reset: uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu
Command Reset: SSSS SSSS SSSS SSSS SSSS SSSS SSSS SSSS
(Channel 1 Address = 1FFA3008 h) 32-bit rd/wr
(Channel 2 Address = 1FFA4008 h) 32-bit rd/wr
31 20 19 0
+-----------+-----------------------------------+
| RSVD | BYTE COUNT |
+-----------+-----------------------------------+
Power Up Reset: 0000 0000 uuuu uuuu uuuu uuuu uuuu uuuu
Command Reset: 0000 0000 SSSS SSSS SSSS SSSS SSSS SSSS
(Channel 1 Address = 1FFA300C h) 32-bit rd/wr
(Channel 2 Address = 1FFA400C h) 32-bit rd/wr
31 11 10 8 7 0
+-----------------------+--+--+--+--+--+--+--+--+--+--+--+
| RSVD |CA|A2|PS|AP|MI|SA|SC|LE|TC|DR|SS|
+-----------------------+--+--+--+--+--+--+--+--+--+--+--+
This register stores the control/status information for Bus Master Channel 1.
In addition: Reading this bit will not read zero unless the cycle has completed and the channel is stopped. The bit, therefore, provides status for the channel as well as controlling its function.
When this bit is set, no other bit in the CCR can be updated by a direct I/O write from the resident processor. This feature allows the start/stop bit to be reset without corrupting the transfer currently executing.
This bit is not updated during list chaining. All other bits in the CCR are updated during list chaining. This feature allows the register to be loaded with new values during list chaining without resetting the start/stop bit. Stopping the channel during list chaining is under control of Bit 4 in the CCR, 'Stop Channel after List Chaining.'
Power Up Reset: uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuu0
Command Reset: SSSS SSSS SSSS SSSS SSSS SSSS SSSS SSS0
For Posting Status, the value in the BMAR represents a location in Local Bus address space. The contents of the BMSTAT register for the given channel is written to this location as a 32-bit transfer. Therefore, the address should be four-byte aligned. Note that the posting of status does not reset the value of the BMSTAT register. This register must still be read upon termination to clear its contents. When list chaining, the contents of this register are cleared at the beginning of the next list chain operation to reset status for the next data transfer.
For Appended I/O transfers, the lower address word in the BMAR represents a location in Micro Channel I/O address space of a Micro Channel slave. The contents of the register are used by the Bus Master channel to locate the I/O address area of a slave device to access its SIR on appended I/O transfers. The lower eight bits of the upper word, that is, Bits 23-16, store the eight-bit data value for the Appended I/O transfer. Note that only eight-bit I/O transfers are supported. More information on Appended I/O transfers can be found in Section 3.2.3 , "Appended I/O Operations"
(Channel 1 Address = 1FFA3010 h) 16-bit rd/wr
(Channel 2 Address = 1FFA4010 h) 16-bit rd/wr
31 16 15 0
+-----------------------+-----------------------+
| UPPER ADDR WORD * | LOWER ADDR WORD |
+-----------------------+-----------------------+
* Bits 23-16 of Upper Address used for data in Appended
I/O operations.
Power Up Reset: uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu
Command Reset: SSSS SSSS SSSS SSSS SSSS SSSS SSSS SSSS
(Channel 1 Address = 1FFA3014 h) 32-bit rd/wr
(Channel 2 Address = 1FFA4014 h) 32-bit rd/wr
31 1 0
+-----------------------------------------+--+--+
| LIST ADDRESS POINTER |L1|L0|
+-----------------------------------------+--+--+
Power Up Reset: uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu
Command Reset: SSSS SSSS SSSS SSSS SSSS SSSS SSSS SSSS
(Channel 1 Address = 1FFA3018 h) 32-bit rd only
(Channel 2 Address = 1FFA4018 h) 32-bit rd only
31 10 9 7 0
+-----------------+--+--+--+--+--+--+--+--+--+--+
| RESERVED |PX|LX|EX|LP|LC|IC|SI|CK|PE|NT|
+-----------------+--+--+--+--+--+--+--+--+--+--+
Power Up Reset: 0000 0000 0000 0000 0000 0000 0000 0000
Command Reset: 0000 0000 0000 0000 0000 0000 0000 0000
(Channel 1 Address = 1FFA301C H) 32-bit rd/wr
(Channel 2 Address = 1FFA401C H) 32-bit rd/wr
31 2 1 0
+-----------------------------------------+--+--+
| RESERVED |RS|SS|
+-----------------------------------------+--+--+
Power Up Reset: 0000 0000 0000 0000 0000 0000 0000 0000
Command Reset: 0000 0000 0000 0000 0000 0000 0000 0000
The I/O map of the Micro Channel addressable registers is shown in Table 9
Table 9. Micro Channel Addressable Registers
+=========+=========+=========+=======+=====+==========+=======+=====+ | Name | Section | Micro | Width | R/W | Local | Data | R/W | | | | Channel | h | | Bus | Field | | | | | Address l | | Address | | | +=========+=========+=========+=======+=====+==========+=======+=====+ | COMMAND | 2.4.11 | 00-03 | 32 | R/W | 1FFA2000 | 32 | R | +---------+---------+---------+-------+-----+----------+-------+-----+ | ATTN | 2.4.12 | 04 | 8 | R/W | 1FFA2004 | 8 | R | +---------+---------+---------+-------+-----+----------+-------+-----+ | SCP | 2.4.13 | 05 | 8 | R/W | 1FFA2008 | 8 | R | +---------+---------+---------+-------+-----+----------+-------+-----+ | ISP | 2.4.14 | 06 | 8 | R | 1FFA200C | 8 | R/W | +---------+---------+---------+-------+-----+----------+-------+-----+ | CBSP | 2.4.15 | 07 | 8 | R | 1FFA2010 | 8 | R/W | +---------+---------+---------+-------+-----+----------+-------+-----+ | SIR | 2.4.16 | - | - | - | 1FFA2014 | 16 | R/W | +---------+---------+---------+-------+-----+----------+-------+-----+ | GAID | 2.4.3 | 0A | 8 | R | 1FFA0008 | 8 | R | +---------+---------+---------+-------+-----+----------+-------+-----+ | NMI | 2.4.8 | 0B | 8 | R/W | 1FFA001C | 1 | R | +---------+---------+---------+-------+-----+----------+-------+-----+ | HSBR | 2.5.1 | 0C-0F | 32 | R/W | - | - | - | +---------+---------+---------+-------+-----+----------+-------+-----+ | MDATA | 2.5.2 | 10-13 | 32 | R/W | - | - | - | +---------+---------+---------+-------+-----+----------+-------+-----+ | CONF1 | 2.5.3 | 14-17 | 32 | R | - | - | - | +---------+---------+---------+-------+-----+----------+-------+-----+ | CONF2 | 2.5.4 | 18-1B | 32 | R | - | - | - | +---------+---------+---------+-------+-----+----------+-------+-----+ | CONF3 | 2.5.5 | 1C-1F | 32 | R | - | - | - | +---------+---------+---------+-------+-----+----------+-------+-----+
Note that it is possible to read and write Miami's internal registers using this mechanism. These accesses must be 32-bit accesses.
(Micro Channel Address = Base + 0C-0F h) 32-bit rd/wr
31 0
+------------------------------------------------+
| HOST-SLAVE BASE ADDRESS |
+------------------------------------------------+
Power Up Reset: uuuu uuuu uuuu uuuu
Command Reset: SSSS SSSS SSSS SSSS
The MDATA register can be accessed on the Micro Channel as a single 32-bit register, two 16-bit registers, or four 8-bit registers. Therefore, to access individual bytes on various address boundaries, the address used to access the MDATA register must match the alignment of the value stored in the HSBR. That is, the two least significant bits of the MDATA I/O address must match the least significant bits of the HSBR. For example, to access an odd word in Local Bus address space, i.e. an address located on an odd word boundary, the HSBR is first loaded with this odd word address. To access the odd word, the MDATA register is subsequently accessed as a word register at Micro Channel location 0012 hex. To access a byte at this Local Bus location, the MDATA register is accessed as a byte register at location 0012 hex.
As a result of this limited data steering, the following limitations are placed on MDATA access:
Note that read accesses through MDATA to the nonbursting area in Local Bus address space limits the prefetch buffer to single transfers. That is, only single transfers will occur on the Local Bus, and -CDCHRDY will be asserted on the Micro Channel for each slave access. More information on the nonbursting address space can be found in Section 3.1.1 , "Shared Memory"
(Micro Channel Address = Base + 10 h) 32-bit rd/wr
(Micro Channel Address = Base + 10,12 h) 16-bit rd/wr
(Micro Channel Address = Base + 10,11,12,13 h) 8-bit rd/wr
31 0
+------------------------------------------------+
| MEMORY DATA |
+------------------------------------------------+
Power Up Reset: uuuu uuuu uuuu uuuu
Command Reset: SSSS SSSS SSSS SSSS
(Micro Channel Address = Base + 14h) 32-bit rd only
(POS 3A,3B Addresses = Subaddress 100,101) 8-bit rd/wr
31 0
+--------------+--------------+--------------+--------------+
| PROC_CFG H | PROC_CFG L | POS3B | POS3A |
+--------------+--------------+--------------+--------------+
Power Up Reset: 0000 0000 000u uu00 000u uuu0 1110 0000
Command Reset: 0000 0000 000S SS00 00SS SSSS SSSS SSSS
(Micro Channel Address = Base + 18h) 32-bit rd only
(POS Addresses = 0-3) 8-bit rd/wr
31 0
+--------------+--------------+--------------+--------------+
| POS3 | POS2 | POS1 | POS0 |
+--------------+--------------+--------------+--------------+
Power Up Reset: 0001 1100 0001 0010 0000 0000 0000 0000
Command Reset: SSSS SSSS SSSS SSSS SSSS SSSS SSSS SSSS
(Micro Channel Address = Base + 1Ch) 32-bit rd only
(POS Addresses = 4-7) 8-bit rd/wr
31 0
+--------------+--------------+--------------+--------------+
| POS7 | POS6 | POS5 | POS4 |
+--------------+--------------+--------------+--------------+
Power Up Reset: uuuu uuuu uuuu uuuu 11uu uuuu uuuu uuu0
Command Reset: SSSS SSSS SSSS SSSS SSSS SSSS SSSS SSSS
POS0 POS1 POS2 POS3 POS4 POS5 POS6 POS7 POS3A POS3B
CE B0 CKE MW0 SA8 (IBE) SA0 A24 EN
C C W1 B1 A20 MW1 SA9 (CTO) SA1 A25 AL0
A A R0 B2 A21 MW2 SA10(XST) SA2 A26 AL1
R R R1 B3 A22 I13 SA11(SDP) SA3 A27 AL2
D D R2 AS A23 I14 SA12(BDP) SA4 A28 AL3
R3 PE A29 I15 SA13 SA5 I10 ADP
I I L0 SF A30 CS SA14 SA6 I11 RSV
D D L1 SE A31 CK SA15 SA7 I12 RSV
The Local Bus is based on the Intel 80960 Processor Bus. The Local Bus contains a 32-bit multiplexed address/data bus, operating at 25 MHz. A description of the Local Bus signals is available in Table 3. Local Bus Timings are available in Appendix C. "Miami Timing".
The following sections describe operation on the Local Bus of the Miami chip.
Access to Local Bus address space (and to memory resident on the Local Bus) is available from the Micro Channel memory space. There are two independent windows into resident memory from the Micro Channel memory map. These windows are configured in POS and separately enabled by the resident processor in the PROC_CFG register.
Note. 16 KByte windows must be on 16 KByte boundaries.
Note. The memory window must be placed on a boundary equal to the size of the available memory as set in the PROC_CFG. For example, for 8 MBytes of memory (MW2-0 = 100), A22-A20 must equal zero.
A28-A24 are configurable in the POS subaddress register 3A, allowing additional options for window placement. These bits are set to zero on a Power Up Reset, allowing systems that do not support subaddressing to configure Miami through POS 4 only.
A memory map showing the relationship between the Micro Channel memory windows and Local Bus address space is given in Figure 4.
Figure 4. Shared Memory Windows
MICRO CHANNEL LOCAL BUS
ADDRESS SPACE ADDRESS SPACE
FFFFFFFF FFFFFFFF
| | | |
_________ |____________| | |
A | |\ | |
| | | \ | |
SECOND | | \ | |
WINDOW | | \ | |
| | | \ | |
_V_______ |____________| \ | |
| |\ \ | |
| | \ \ | |
| | \ \ | |
| | \ \ | |
| | \ \ | |
| | \ \ | |
| | \ \ | |
| | \ \ | |
| | \ \ | |
| | \ \ | |
| | \ \ | | TOP OF
_ _00100000|_ _ _ _ _ _ | \ \|____________| /___ RESIDENT
| | \ | | \ MEMORY
_ _000DFFFF|_ _ _ _ _ _ | \ | |
| | \ | |
ROM/RAM |____________|_ _ _ _ _ _ _ _\__|____________|
AREA | | 8K OR 16K \ | |
|____________|_ WINDOW_ _ _ _ _\|____________| BASE ADDR
| | | | (LBBAR)
_ _000C0000|_ _ _ _ _ _ | | |
| | | |
| | | |
00000000| | | |00000000
Table 10. Burst/Non-Burst Address Map
+==========================+======================+ | Local Bus Address | Access | +==========================+======================+ | 0000 0000 - 1FFF FFFF | Non-Burst | +--------------------------+----------------------+ | 2000 0000 - FFFF FFFF | Burst | +--------------------------+----------------------+This nonbursting area can be accessed through the two shared memory windows, by the DMA channels, through the MDATA register and through POS subaddress space. In addition, for Micro Channel slave read access to this area through the MDATA register, the prefetch buffer associated with Micro Channel slave read accesses is filled by single transfers, i.e. the prefetch mechanism is disabled. This nonbursting, nonprefetching mechanism provides the ability to access Local Bus address areas that are affected by the prefetch mechanism. One example of this type of address area is self-clearing registers that may be corrupted by a prefetch read during an access to a contiguous address. Another example is a protected memory containing boundaries that may be crossed during a prefetch associated with a read from a contiguous location.
Note that all POS subaddress access are both nonbursting and nonprefetching.
Miami arbitrates for the Local Bus by asserting one of two bus request signals: -SLVEREQ or -MSTRREQ. These signals are asserted dependent on the source of the bus request. That is, requests from the Micro Channel slave interface are asserted by -SLVEREQ and requests from the Bus Master Channels, 1 and 2, are asserted by -MSTRREQ. Each request has an individual acknowledge signal: -SLVEACK and -MSTRACK, respectively. Providing separate requests for master and slave activity allows separate arbitration by a Local Bus arbiter based on the activity requested. Arbtration between the two Bus Master channels, and their priority is discussed in Section 3.2 , "Bus Master Channel Functional Description".
In handling the arbitration of -SLVEREQ and -MSTRREQ external to Miami, consideration must be given to the 3.4 microsecond timeout of -CDCHRDY, based on pending slave requests. This is the only restriction placed on the priority of Local Bus access.
Miami ownership of the Local Bus can be preempted by removing the active acknowledge from the Local Bus. Miami will detect the removal of acknowledge, and remove the associated request with the assertion of -L_BLAST, signalling the termination of its ownership. Ownership is then relinquished when the slave asserts -L_READY. The general timing for initiating and relinquishing Local Bus ownership is available in Section C.0.1 , "Miami CFE Local Bus Timings".
The time from recognizing the removal of acknowledge to the removal of request with -L_BLAST is variable, dependent upon 1) which request is active, 2) the type of transfer, and 3) how many transfers have already occurred on the Local Bus. The number of transfers is a factor in termination because Miami guarantees a minimum number of transfers for each bus ownership. This number is 16 for -SLVEREQ accesses and four for -MSTRREQ. The time to relinquish ownership of the bus, in number of transfers is given in Table 11.
Table 11. Local Bus Ownership Termination (number of transfers)
+==================+==================+==================+==================+ | Request Active | Type of Access | Xfers Performed | Xfers Before | | | | (XP) prior to | Termination | | | | Ack | | +==================+==================+==================+==================+ | -MSTRREQ | Read or Write | 1 to 3 | 4-XP | +------------------+------------------+------------------+------------------+ | -MSTRREQ | Read or Write | >= 4 | 1 | +------------------+------------------+------------------+------------------+ | -SLVEREQ | Read | 1-15 | 16-XP | +------------------+------------------+------------------+------------------+ | -SLVEREQ | Read | >16 | 1 | +------------------+------------------+------------------+------------------+ | -SLVEREQ | Write | 1-15 | 16-XP | +------------------+------------------+------------------+------------------+
Miami supports the generation and checking of data and address parity on the Local Bus. Address and Data Parity are always generated for the Local Bus. The checking of address and data parity is enabled by setting Bit 9 in PROC_CFG. The detection of a Local Bus address parity error by Miami as a slave blocks the current transfer with no interrupt or status provided. Note that the -L_EXCPT signal is not asserted, therefore, a Local Bus timeout mechanism must be implemented to detect this error. If a Local Bus data parity error is detected by Miami as a Local Bus slave, the -L_EXCPT signal is asserted synchronous to the transfer.
If Local Bus Parity is detected on a Bus Master channel access of the Local Bus, the Bus Master access is terminated and the Local Bus Parity Bit is set in the Bus Master Status Register. The Bus Master termination interrupt for that channel is also asserted.
The detection of Local Bus data parity on a Micro Channel read forces a Local Bus Parity/Exception interrupt to the Local Bus and the setting of Bit 0 in the Local Bus Parity/Exception Register. This bit, as well as the interrupt, is cleared by reading the Local Bus Parity/Exception Register. Data for the failing transfer is not passed to the Micro Channel. If currently streaming, streaming data is terminated on the transfer prior to the failing transfer in the prefetch buffer. If the Micro Channel master subsequently reaccesses Miami at the failing address, -CDCHRDY will be asserted. After a timeout of 3.4 microseconds, -CHCK will be asserted by Miami on the Micro Channel to signal the failing transfer. The assertion of -CHCK on erroneous data transfers is handled in this way to prevent the assertion of -CHCK for prefetched transfers not requested by the Micro Channel master.
If the CD CHRDY Timeout Disable (Bit 21, PROC_CFG) is set to disable, the -CHCK will not occur. This can result in timeout errors on the Micro Channel during exception conditions.
More information about the CD CHRDY Timeout Disable is provided in Section 2.4.5 , "Processor Configuration Register (PROC_CFG)".
Miami receives notification from two sources of Local Bus exceptions occurring remotely. These sources interrupt the Miami chip by two separate exception lines:
These two exceptions are summarized in Table 12.
+======================+======================+ | Source | Signal | +======================+======================+ | Watchdog | -WATCHDOG | +----------------------+----------------------+ | Local Bus Transfer | -L_EXCPT | +----------------------+----------------------+These exceptions create different responses by Miami:
The detection of the -L_EXCPT on a Micro Channel read forces a Local Bus Parity/Exception interrupt to the Local Bus and the setting of Bit 1 in the Local Bus Parity/Exception Register. This bit, as well as the interrupt, is cleared by reading the Local Bus Parity/Exception Register. Data for the failing transfer is not passed to the Micro Channel. If currently streaming, streaming data is terminated on the transfer prior to the failing transfer in the prefetch buffer. If the Micro Channel master subsequently reaccesses Miami at the failing address, -CDCHRDY will be asserted. After a timeout of 3.4 microseconds, -CHCK will be asserted by Miami on the Micro Channel to signal the failing transfer. The assertion of -CHCK on erroneous data transfers is handled in this way to prevent the assertion of -CHCK for prefetched transfers not requested by the Micro Channel master.
Note that this signal is also driven by Miami if a data parity error is detected on the Local Bus during a write to Miami as a Local Bus slave.
Note If the CD CHRDY Timeout Disable (Bit 21, PROC_CFG) is set to disable, -CHCKs will not occur for Local Bus Exceptions. This can result in timeout errors on the Micro Channel during exception conditions.
More information about the CD CHRDY Timeout Disable is provided in Section 2.4.5 , "Processor Configuration Register (PROC_CFG)".
The Miami chip interrupts the Local Bus under seven conditions. Miami presents each of these seven interrupt sources as encoded interrupts on the Local Bus interrupt lines, INT(3-0). These encoded interrupt lines can be used by external hardware to generate interrupts and vectors to the resident processor. The lines do not represent a valid vector for any particular resident processor.
Each source of interrupt and its corresponding interrupt code is present in Table 13. Note that although the Inactive State for the encoded interrupt signals is 1111, implying that the signals are active low, the signals have been given active high signal designations (INT(0-3)). The values in this table represent the actual state of the interrupt signals (0 = Low, 1 = High).
Table 13. Local Bus Interrupt Sources
+======================+======================+ | Interrupt Source | Encoded | | | Interrupt--INT(3-0) | +======================+======================+ | Non-Maskable | 0000 | | Interrupt (NMI) | | +----------------------+----------------------+ | Local Bus | 0001 | | Parity/Exception | | +----------------------+----------------------+ | SCB Attention Port | 0010 | +----------------------+----------------------+ | End-Of-Data-Transfer | 0011 | +----------------------+----------------------+ | General Interrupt | 0100 | +----------------------+----------------------+ | Bus Master Channel 2 | 0101 | +----------------------+----------------------+ | Bus Master Channel 1 | 0110 | +----------------------+----------------------+ | Reserved | 0111-1110 | +----------------------+----------------------+ | Inactive State | 1111 | +----------------------+----------------------+Each encoded interrupt is held active on the interrupt lines until the clearing procedure for that interrupt is performed. Until the current interrupt is cleared, all other interrupts asserted internally are held pending. After an interrupt is cleared, all pending interrupts are latched, and the highest priority pending interrupt is asserted on the encoded interrupt lines. After this interrupt is cleared, the next priority interrupt is serviced. This operation continues until all interrupts previously pending are serviced in order of priority. When the last interrupt is cleared, all new interrupts that were asserted internally while the current interrupts were serviced are latched, and the highest priority interrupt is asserted first. Interrupts for conditions occurring simultaneously are presented in the order of their encoded value. For example, if a General Interrupt occurs simultaneous to a Bus Master Channel interrupt, the General Interrupt would be presented first. he only exception to this procedure is the NMI command. This interrupt is always presented as the next available interrupt, regardless of the order of occurrence.
The clearing procedure varies with the source of the interrupt:
The handling of Local Bus exception conditions discussed in the previous sections, Local Bus Parity and the -L_EXCPT signal are summarized in Table 14.
Table 14. Local Bus Exception Handling Summary
+=========================+=========================+=========================+ | Miami Function | Local Bus Parity | -L_EXCPT | +=========================+=========================+=========================+ | Micro Channel Slave | Not Applicable | o Sets Status in LBPE | | Write | | o Asserts Local Bus | | | | o Parity/Exception | | | | Interrupt | +-------------------------+-------------------------+-------------------------+ | Micro Channel Slave | o Sets Status in LBPE | o Sets Status in LBPE | | Read | o Asserts Local Bus | o Asserts Local Bus | | | Parity/Exception | Parity/Exception | | | Interrupt | Interrupt | | | o Asserts -CHCK on | o Asserts -CHCK on | | | Micro Channel | Micro Channel | +-------------------------+-------------------------+-------------------------+ | Bus Master Channel Read | o Stops Channel | o Stops Channel | | | o Sets Status in BMSTAT | o Sets Status in BMSTAT | | | o Asserts Bus Master | o Asserts Bus Master | | | Termination Interrupt | Termination Interrupt | +-------------------------+-------------------------+-------------------------+ | Bus Master Channel | Not Applicable | o Stops Channel | | Write | | o Sets Status in BMSTAT | | | | o Asserts Bus Master | | | | Termination Interrupt | +-------------------------+-------------------------+-------------------------+ | Local Bus Slave Access | Assert -L_EXCPT | Not Applicable | +-------------------------+-------------------------+-------------------------+More information on the handling of the Watchdog interrupt can be found in Section 2.4.15 , "Command Busy Status Port (CBSP)".
The following sections describe the operation of the Bus Master Channels, 1 and 2.
As stated in Section 2.1 , "Miami Block Description", all data transactions, including Bus Master transfers, are subject to intermediate buffering. A diagram of this intermediate buffering is repeated from Section 2.1 , "Miami Block Description" in Figure 5.
Figure 5. Intermediate Buffering
+-------------------------------+
| +---------+ |
| | | |
| | | |
+-------------+ | | CH1 | |
| +---------+ | | +----->| BUFFER |<------+ |
| | | | | | | | | |
| | MICRO | | | | | | | |
<--->| CHANNEL |<---------+ +---------+ | |
| | BUS | | | | | |
| | MASTER | | | | +---------+ | |
| | | | | | | | | |
M | +---------+ | | | | | | |
I | | | | | CH2 | | |
C | | | +----->| BUFFER |<------+ |
R | | | | | | |
O | | | | | | |
| MICRO | | +---------+ | |
C | CHANNEL | | | |
H | INTERFACE | | +---------+ | | +--------------+
A | (MCI) | | | |-+ | | | +--------+ |
N | | | | SLAVE | |-+ | | | | | |
N | | | | WRITE | | | +-------->| LOCAL | |
E | | | +----->| BUFFER +---------------->| BUS |<---->
L | | | | | 0, 1, 2 | | | +---------+ MASTER | | L
| +---------+ | | | | | | | | | | | | | O
| | | | | | +---------+ | | | | | +--------+ | C
| | MICRO | | | | +---------+ | | | | | A
<--->| CHANNEL +----------+ +---------+ | | | LOCAL | L
| | SLAVE | | | | | | BUS |
| | INTFC |<---------+ +---------+ | | | INTERFACE | B
| | | | | | | |-+ | | | (LIB) | U
| +---------+ | | | | SLAVE | |-+ | | | | S
+-------------+ | | | READ | | |-+ | | +--------------+
| +------+ BUFFER | | | | | |
| | 0-3 |<------+ |
| | | | | | |
| +---------+ | | | |
| +---------+ | | |
| +---------+ | |
| +---------+ |
| INTERNAL BUFFERS |
| |
+-------------------------------+
Each Bus Master channel manages data movement through
128 bytes of intermediate buffering. This intermediate buffering
is organized as
two independent 64-byte ping-pong buffers. The Bus Master channel
alternately
uses these two buffers for accesses on
the Local Bus and Micro Channel interfaces, optimizing the
total throughput of its data transfers.
The following discussion pertains to the operation of a single Bus Master channel. Throughout this discussion, the term "buffer" refers to one of the 64-byte ping-pong buffers for that channel, and the term "intermediate buffering" refers to the entire 128 bytes of buffering available for that channel. The term "bus" refers generically to either the Micro Channel or the Local Bus.
As stated above, the general operation of a Bus Master channel for large transfers is to fill and flush data to and from its two buffers in a ping-pong fashion. That is, depending on the direction of transfer, if the data in a buffer is flushed to one bus, the buffer is immediately available to be filled on the other bus. At any given time, data can be flushed from one buffer on one bus, and filled into the other buffer from the other bus, approximating a constant throughput between the two buses. When the channel is active, if a buffer is available for data transfers on one bus and there is no data transfers currently taking place on that bus, the channel will immediately arbitrate for control of the bus. If a buffer becomes available for a bus and data transfers are taking place on that bus, transfers to the free buffer will take place in zero wait states after completion of transfers to the buffer currently being accessed. Therefore, in general, arbitration to a bus from an inactive state can occur when 64 bytes are available in the buffer, and can be sustained as long as buffers become available.
To provide better utilization of the Micro Channel, the Bus Master channel makes all 128 bytes of its intermediate buffering available for its initial access of the Micro Channel. An initial access is the first arbitration of the Micro Channel after the start/stop bit is set or after a list chain operation has initiated a new data transfer. This 128-byte initial access is easily accomplished for reads from the Micro Channel, since the full intermediate buffering is empty at the start of a cycle. For writes to the Micro Channel, both buffers must be completely full, or the byte count must equal zero, for this initial access to take place. As described above, the channel will continue to access the Micro Channel as long as buffers are available. After the Bus Master channel relinquishes control of the Micro Channel, it will rearbitrate for subsequent accesses after 64-bytes, or one buffer, is available.
Initial accesses on the Local Bus occur when 64-bytes, or one buffer is available.
Additional bandwidth is gained on the Micro Channel by sharing the Micro Channel grant period for Miami between the two Bus Master channels. That is, if Bus Master Channel 1 has run out of buffer space, and there is additional time on the Micro Channel, Bus Master Channel 2, will perform accesses to its 128-byte buffer. This sharing of the Micro Channel between channels is only possible when the arbitration levels for the channels are the same, i.e. the A2 option in the CCR of each channel is set to the same state.
Each Bus Master channel is configured from the Local Bus by programming a Channel Descriptor Block (CDB) resident in the Miami chip. A description of the CDBs for each Channel is given in Section 2.4.17 , "Bus Master Channel Descriptor Block (BMCDB)".
Each Bus Master channel is controlled through a Channel Control Register (CCR) located in each CDB. A channel is enabled by setting the Start/Stop Bit (Bit 0) in the CCR. The direction of the data transfer is set by the Direction Bit (Bit 1) in the CCR. Description of the CCR for each channel is given in Section "Channel Control Register (CCR)".
When the Start/Stop Bit is set in the Bus Master channel, operation begins in one of two ways, depending on the state of the Direction Bit. If the direction is set to read from the Micro Channel (writing to the Local Bus), the Bus Master channel will immediately arbitrate for the Micro Channel. When granted the Micro Channel, the Bus Master channel will fill its buffer by reading from the address specified in the System Address Register (SAR), located in the CDB. The channel will continue to fill its buffer until 128-bytes are read, or until the Byte Count in the Byte Count Register (BCR) equals zero. Concurrently, once the first 64-byte buffer is full, data is transferred from the buffer into memory resident on the Local Bus at the location specified in the Card Address Register (CAR). In the general case, the channel will read 128-bytes from the Micro Channel before data is completely flushed to resident memory. At this point, the channel will release its control of the Micro Channel. After the buffered data is flushed to resident memory, the channel rearbitrates for the Micro Channel. The channel continues this arbitrate/release/flush sequence until the Byte Count equals zero.
If the direction is set to write to the Micro Channel (reading from the Local Bus), the channel fills the buffer from memory resident on the Local Bus from the location loaded in the CAR. The channel continues to fill the buffer until 128-bytes are transferred or the Byte Count equals zero. After 128 bytes are loaded, the channel arbitrates for the Micro Channel. When granted, the channel flushes the buffered data to the Micro Channel at the location loaded in the SAR. Concurrently, after the first 64-byte buffer is completely flushed on the Micro Channel, additional data is loaded in the buffer from the Local Bus. In the general case, the Micro Channel will continue to flush the additional data until the buffer is empty. When there is no more data to be transferred the channel releases its control of the Micro Channel. The channel continues to fill from the Local Bus until the buffer is full or the Byte Count equals zero. The channel will then rearbitrate for the Micro Channel. The channel continues this fill/arbitrate/flush sequence until the Byte Count equals zero.
The two Bus Master channels have equal priority under normal operation, that is, they alternate ownership of the Local Bus equally. If one channel owns the Local Bus and the other channel has a Local Bus access pending, Miami will reissue its request for the Local Bus after the current owner relinquishes ownership. When Miami receives its -MSTRACK a second time, ownership of the Local Bus will pass to the pending channel.
If channel requests are asserted at the same time, Channel 1 is granted priority.
Miami is capable of performing transfers with any address alignment combination, as a Micro Channel Bus Master, and as a Micro Channel slave through the shared memory window. The number of bytes transferred on either the Micro Channel or the Local Bus is controlled by the respective byte enable signals for that bus.
On the Micro Channel, the number of bytes transferred during a cycle is determined by the total number of bytes to be transferred, the Micro Channel address, and the width of both the master and the slave. As a Micro Channel Bus Master, in all cases, the maximum number of bytes are transferred. Therefore, for a transfer between a 32-bit master and a 32-bit slave at an address on an odd byte boundary, i.e. an address with the least significant nibble equal to '1'h, Miami transfers three bytes.
Streaming data transfers, by Micro Channel definition, must be aligned to the width of the transfer. Miami, as a Micro Channel Bus Master, does this alignment, if starting on an odd boundary, in a minimum number of cycles. Therefore, in the above example, if the slave has multiplexed streaming data capability, Miami transfers three bytes, then performs a four-byte transfer before initiating a streaming cycle.
As a Local Bus Master, Miami also transfers the maximum number of bytes per transfer. When writing a slave on an odd byte boundary, Miami transfers three bytes . In this case, the upper three byte enables (BE3-1), are asserted. When reading a slave on any boundary, the entire 32-bit word associated with that address is read, i.e. all four byte enables are asserted and the two least significant bits of the Local Bus address are zero.
Each channel has the ability to append an I/O write to the Micro Channel upon reaching a terminal count. The intent of this I/O is to create an efficient method for interrupting the Source Identification Register (SIR) through the Attention Port of a slave adapter after a data transfer is complete. The function of the SIR is discussed in Section 2.4.16 , "Source Identification Register (SIR)".
The address and data for an Appended I/O operation are both stored in the Bus Master Address Register (BMAR). When an appended I/O operation is enabled, the channel writes to the Micro Channel I/O address stored in the lowest 16-bits of the BMAR, in the CDB. In general, this function is used to write an eight-bit value to the Attention Port of the Micro Channel slave's Subsystem Control Block (SCB) register map. When a terminal count is reached, the channel appends the I/O write to this address, using the data stored in Bits 16-23 of the BMAR. That is, if the direction of transfer is from the Local Bus to the Micro Channel, the I/O is appended after the last transfer to the Micro Channel. If the direction of transfer is from the Micro Channel to the Local Bus, the I/O is appended after the last transfer to the Local Bus. The BMAR register for each channel is discussed in Section "Bus Master Address Register (BMAR)".
The channel controls appended I/O operations through its CCR. The Appended I/O (AP) Bit, Bit 7, sets the channel for an Appended I/O operation. The setting and resetting of bits in the slave SIR is discussed in Section 2.4.16 , "Source Identification Register (SIR)".
Setting both the AP and the PS bits in the CCR is an invalid combination. Using this invalid combination will not interfere with the data transfer. A normal termination will occur, but no I/O write will be appended.
Each channel has the ability to perform a posted status operation to a location in Local Bus address space. The intent of this operation is to provide an alternate method of signalling the normal termination of a data transfer, in addition to the terminal count interrupt. Posting status has two applications in conjunction with list chained data transfer elements:
The 32-bit address for this operation is stored in the Bus Master Address Register (BMAR). The appended operation is a 32-bit write to this location of the contents of the Bus Master Status Register (BMSTAT). When a terminal count is reached, the channel posts status to the Local Bus, i.e. if the direction of transfer is from the Local Bus to the Micro Channel, status is posted after the last transfer to the Micro Channel. If the direction of transfer is from the Micro Channel to the Local Bus, status is posted after the last transfer to the Local Bus.
The channel controls Posted Status operations through its CCR. The Posted Status Bit, Bit 8, sets the channel for Posted Status operation.
Note that only normal termination status is posted. Status is not posted for exception conditions, but rather the channel is stopped and an interrupt is posted.
Both Bus Master channels support Linked List Chaining (LLC), or scatter/gather DMA. Linked List Chaining provides the ability for each channel to auto-initialize its Channel Descriptor Block (CDB) from a predefined list in memory. Each element in this list consists of a set of new register values. An element is loaded into the CDB when the channel reaches a terminal count for the current data transfer. Since each element represents a separate data transfer, Linked List Chaining allows the channel to interleave the scattering and the gathering of data from different buffer locations in memory, with minimum intervention from the resident processor. In addition, control information in the CCR can also be updated, allowing dynamic changing of DMA parameters.
Within the CDB a 32-bit address pointer to the list in memory is maintained. At the time of terminal count, if list chaining is enabled, the hardware will fetch six 32-bit words starting at this memory address and reload the CDB at hardware speeds. List chaining provides a mechanism to off-load the resident processor from register initialization after every terminal count. Based on the value programmed in the CCR, the channel can optionally interrupt the resident processor, in addition to List Chaining, on a terminal count. This list of buffers can occupy any area in free memory. The list chaining function is shown in Figure 6.
Figure 6. Linked List Chaining
CDB MEMORY ADDRESS
31 0
+------------------------+
| CARD ADDRESS 31-0 | LAP
LIST --------> +------------------------+
ADDRESS | SYSTEM ADDRESS 31-0 | LAP + 4
POINTER +------------------------+
| BYTE COUNT | LAP + B
+------------------------+
| CHANNEL CONTROL | LAP + C
+------------------------+
| BUS MASTER ADDRESS | LAP + 10
+------------------------+
| LIST ADDRESS | LAP + 14
+------------------------+
At the end of this operation, the CDB contains a new pointer to
a new list located anywhere else in memory.
There are several special modes of operation for termination of the Bus Master channels and interrupting the Local Bus. These different modes involve several bits in the CCR.
It is easiest to think of transfers as broken into three steps: a data transfer, an optional appended I/O and a list chain operation to bring in a new list chain element. A list chain element is a six-word entry in Local Bus address space containing the values for initializing the Channel Descriptor Block (CDB) for a data transfer. It is important to note that the termination interrupt enabled by the Terminal Count Interrupt Enable (Bit 2) in the CCR, represents the normal termination of a data transfer, or of a data transfer plus appended I/O when an appended I/O is enabled, and does not necessarily represent termination or disabling of Bus Master operation.
The beginning of a list chain operation is considered the start of a new data transfer.
Although it is possible to take interrupts on the fly, normal operation is to take a single termination interrupt at the end of the entire list chain. A single termination interrupt is desirable for the following two reasons:
This mode of operation is especially useful in conjunction with the List Chaining Zero Byte Elements option. In the case where there are currently no transfers to take place, an element of zero byte count can be appended with the Stop Channel after List Chaining Bit (CCR, Bit 4) set in the CCR. As long as the List Chain Enable Bit is also set in this element, operation will continue upon re-enabling the channel, with a list chain operation taking place to the address pointed to by the current list address pointer. Thus, the Stop Channel after List Chaining can be used as a true NOP or Pause function for a given list chain or pipe.
Note.Since this option terminates after a list chain, and not after a data transfer or appended I/O operation, there is no normal termination interrupt associated with stopping the channel in this mode. The start/stop bit must be polled to determine when the channel is stopped.
Note: Like the 'Stopping the Channel after List Chaining' option, this operation is not associated with normal termination of data transfers or Appended I/O, and thus, after the start/stop bit is reset, there is no termination interrupt associated with this mode of operation. Note also that this function is not supported with List Chaining enabled.
The following is a summary of conditions which stop the Bus Master channel with termination interrupt and status:
The following conditions stop the Bus Master channel without termination interrupt and status:
Note that all terminations are noncatastrophic, i.e. termination of the channel is nondisruptive to either the Micro Channel or the Local Bus.
In all cases, with the exception of resetting the Start/Stop bit, the channel is completely reset on termination. When resetting the Start/Stop bit, the channel terminates with the internal state machines intact, providing the option to restart the channel and complete the current transfer.
The following sections describe additional operations of the Miami chip on the Micro Channel.
The Miami chip is initialized on the Micro Channel through POS registers. The POS registers are read/write accessible through POS addresses defined for the Micro Channel. In addition, the POS registers are mapped to both the Local Bus address space and the Micro Channel I/O space. These mappings allow access to POS information for the resident processor and the Micro Channel device driver. A listing of the POS registers and their bit maps is available in Section 2.6 , "POS Registers". Discussion of the function of each bit in the POS registers is available in Section 2.4.1 , "POS Setup Register 1 (POS_SETUP1)" and Section 2.4.2 , "POS Setup Register 2 (POS_SETUP2)".
The subaddress locations 0100 h and 0101 h, in POS 6 and 7, address two registers internally: POS 3A and 3B. POS 6 contains the least signficant byte, and POS 7, the most significant byte of the subaddress. These two registers are used for extended functions on the Micro Channel. Accesses to subaddress locations from 0001-00FF h in POS 6 and 7 generate Local Bus cycles with the Extended POS address. This subaddress area is available for Vital Product Data (VPD) or configuration data, depending on implementation. Subaddress locations above 0101 h are out of normal VPD range, but are available as additional subaddress space. Accesses to these subaddresses will generate cycles to the Local Bus. This subaddress mapping is summarized in Table 15.
+============+============+======================+ | POS 7 | POS 6 | Function | +============+============+======================+ | 00 | 01-FF | Vital Product Data | | | | (VPD) | +------------+------------+----------------------+ | 01 | 00 | POS 3A | +------------+------------+----------------------+ | 01 | 01 | POS 3B | +------------+------------+----------------------+ | 01-FF | 02-FF | Add. Subaddress | | | | Space (0102-FFFF) | +------------+------------+----------------------+Note that subaddressing presents a nonbursting interface to the Local Bus, and that prefetching on reads is limited to single transfers. That is, reading subaddress space through POS 3 forces only single transfers.
Local Bus accesses resulting from subaddress cycles assume, by CFE definition, a 32-bit bus width. Therefore, subaddress interfaces to the CFE bus must provide data on all four bytes of the Local Bus although POS accesses, by Micro Channel definition, are eight-bit accesses. Miami provides an eight-bit interface to the Micro Channel, i.e. all odd-subaddress accesses are steered to the least significant byte of the Micro Channel.
Subaddress reads are performed as a 32-bit read on a four-byte boundary. Odd subaddress reads, therefore, are 32-bit accesses, and the correct byte is selected from the four-byte access and presented to the Micro Channel.
Subaddressing on the Local Bus is implemented as a 32-bit access because all devices on the CFE Local Bus are, by definition, 32-bit devices. Since all subaddress accesses are, by Micro Channel definition, eight-bit accesses, an eight-bit device can be interfaced for purposes of subaddressing, if the read address can be properly incremented, and the data properly steered for odd addressing. The easiest implementation, however, is to provide a 32-bit interface. For example, a 32-bit DRAM or SRAM can be used. POS Setup can be delayed until subaddress data is provided to this memory area by delaying the setting of the CRDID register until the data transfer to memory is complete. Micro Channel hosts will not perform POS Setup prior to reading a valid POS ID in POS registers 0 and 1.
Miami supports both Locate Mode and Move Mode of the Subsystem Control Block (SCB) architecture. The SCB registers and their access for each mode is shown in Table 16.
Table 16. SCB Register Access Summary
+--------------------+-----------------------------------------------------+ | | Normal Access within Operating Modes | +--------------------+--------------------------+--------------------------+ | SCB Register | Locate Mode | Move Mode | +--------------------+--------+---------+-------+--------+---------+-------+ | | System | Peer | Local | System | Peer | Local | | | Master | Adapter | Bus | Master | Adapter | Bus | +--------------------+--------+---------+-------+--------+---------+-------+ | COMMAND | W | None | R | W * | None | R * | +--------------------+--------+---------+-------+--------+---------+-------+ | ATTN | W | None | R | W | W | R | +--------------------+--------+---------+-------+--------+---------+-------+ | SCP | W | None | R | W | None | R | +--------------------+--------+---------+-------+--------+---------+-------+ | ISP | R | None | W | R ** | None | W ** | +--------------------+--------+---------+-------+--------+---------+-------+ | CBSP | R | None | W | R | None | W | +--------------------+--------+---------+-------+--------+---------+-------+ | * Under consideration for Move Mode - not approved | | ** Currently no function defined for Move Mode | +--------------------------------------------------------------------------+The overall objective of the SCB architecture is to provide a programming model for the Micro Channel, by defining the logical protocols for transferring commands, data and status between entities on the Micro Channel.
The Subsystem Control Port is accessed by the Micro Channel, and is used to enable various functions of the Miami chip. This register is used to enable Micro Channel interrupts, to enable DMA operation, to perform a Command Reset of Miami, and to reset the Reject state of the Command Busy Status Port.
In addition to these registers, the ISP and SIR support Micro Channel and additional Local Bus interrupts.
Micro Channel interrupts are cleared in two different ways dependent on the state of the Clear on Read Bit (COR, Bit 6) in the SCP. When this bit is reset, Micro Channel interrupts are cleared in hardware by writing the End of Interrupt command (E0 hex) to the Attention Port. This attention code/device number resets the interrupt in hardware, as well as the IV bit in the CBSP. When the COR is set, Micro Channel interrupts are cleared by reading the Command Busy Status Port from the Micro Channel. When read, the Interrupt Valid bit is reset, as well as the pending interrupt.
With the -CHCK enable bit set in POS, -CHCK is asserted under the following conditions:
Miami detects -CHCK only when operating as a Bus Master. Additionally, the Bus Master can only detect those channel checks which occur while it has control of the Micro Channel. Detection of an -CHCK stops the Bus Master channel and forces a termination interrupt to the resident processor.
Micro Channel data parity detection is also supported when operating as a Bus Master. The detection of parity forces a termination interrupt to the resident processor and stops the Bus Master channel, but does not assert -CHCK.
Micro Channel parity is controlled in POS by the Parity Enable bit. For Micro Channel parity to be supported during peer-to-peer transfers, parity must be enabled on both the master and the slave.
A special parity condition exists for non-streaming accesses to the Miami chip. By Micro Channel definition, data written to Miami as a slave is setup and held relative to the -CMD signal (Pin 171). If a Bus Master changes data while -CMD is active, resulting in a parity error, this error is normally reported as an asynchronous -CHCK. Since some systems cannot handle aynchronous -CHCKs, a bit is provided in POS 3B, Bit 5 to disable this -CHCK reporting, and alternately report this error through LBPE, and its associated interrupt. The default operation is for asynchronous -CHCK reporting for this special error. More information on the disable bit and alternate reporting mechanism is provided in Sections 2.4.2 , "POS Setup Register 2 (POS_SETUP2)" and 2.4.9 , "Local Bus Parity/Exception Register (LBPE)".
The following sections provide the pinout of the Miami chip.
In the following table, 'MC' denotes Micro Channel, and 'LB' denotes Local (CFE) Bus. Circuit type descriptions are given in Table 19
Note that the IRQx, -SLVEREQ, and -MSTRREQ require CIOs in support of ICT, although they have no functional input.
Note to Miami chip designers - Although all external bus signal names are given in vendor notation (Bit 0 = LSB), the Local Bus is given in IBM notation (Bit 0 = MSB) for all internal logics.
Table 17. Miami I/O by Pin Number
+=========+================+=========+================+=======================+ | PIN # | PIN NAME | I/O | CIRCUIT TYPE | SIGNAL NAME | +=========+================+=========+================+=======================+ | 001 | VSS | PWR | VSS | +0 VOLTS | +---------+----------------+---------+----------------+-----------------------+ | 002 | -TESTMODE | INP | IND | -TEST MODE | +---------+----------------+---------+----------------+-----------------------+ | 003 | A5 | CIO | ENR | MC ADDRESS BIT 5 | +---------+----------------+---------+----------------+-----------------------+ | 004 | A18 | CIO | ENR | MC ADDRESS BIT 18 | +---------+----------------+---------+----------------+-----------------------+ | 005 | CD CHRDY | DRV | DNG | CD CHRDY | +---------+----------------+---------+----------------+-----------------------+ | 006 | A19 | CIO | ENR | MC ADDRESS BIT 19 | +---------+----------------+---------+----------------+-----------------------+ | 007 | VSS | PWR | VSS | +0 VOLTS | +---------+----------------+---------+----------------+-----------------------+ | 008 | A6 | CIO | ENR | MC ADDRESS BIT 6 | +---------+----------------+---------+----------------+-----------------------+ | 009 | -CD SFDBK | DRV | DNG | CARD SEL FEEDBACK | +---------+----------------+---------+----------------+-----------------------+ | 010 | VDD | PWR | VDD | +5 VOLTS | +---------+----------------+---------+----------------+-----------------------+ | 011 | A20 | CIO | ENR | MC ADDRESS BIT 20 | +---------+----------------+---------+----------------+-----------------------+ | 012 | A7 | CIO | ENR | MC ADDRESS BIT 7 | +---------+----------------+---------+----------------+-----------------------+ | 013 | ARB/-GNT | INP | INU | ARB/-GNT | +---------+----------------+---------+----------------+-----------------------+ | 014 | VSS | PWR | VSS | +0 VOLTS | +---------+----------------+---------+----------------+-----------------------+ | 015 | APAR0 | CIO | ENR | MC ADDRESS PARITY 0 | +---------+----------------+---------+----------------+-----------------------+ | 016 | A8 | CIO | ENR | MC ADDRESS BIT 8 | +---------+----------------+---------+----------------+-----------------------+ | 017 | -DS 32 RTN | INP | INU | -DATA SIZE 32 RETURN | +---------+----------------+---------+----------------+-----------------------+ | 018 | GND | PWR | GND | +0 VOLTS | +---------+----------------+---------+----------------+-----------------------+ | 019 | A21 | CIO | ENR | MC ADDRESS BIT 21 | +---------+----------------+---------+----------------+-----------------------+ | 020 | VSS | PWR | VSS | +0 VOLTS | +---------+----------------+---------+----------------+-----------------------+ | 021 | -CD DS 32 | DRV | DNG | -CARD DATA SIZE 32 | +---------+----------------+---------+----------------+-----------------------+ | 022 | A22 | CIO | ENR | MC ADDRESS BIT 22 | +---------+----------------+---------+----------------+-----------------------+ | 023 | A9 | CIO | ENR | MC ADDRESS BIT 9 | +---------+----------------+---------+----------------+-----------------------+ | 024 | A23 | CIO | ENR | MC ADDRESS BIT 23 | +---------+----------------+---------+----------------+-----------------------+ | 025 | -16/32 DETECT | INP | INU | -16/32 BIT DETECT | +---------+----------------+---------+----------------+-----------------------+ | 026 | VSS | PWR | VSS | +0 VOLTS | +---------+----------------+---------+----------------+-----------------------+ | 027 | APAR2 | CIO | ENR | MC ADDRESS PARITY 2 | +---------+----------------+---------+----------------+-----------------------+ | 028 | A10 | CIO | ENR | MC ADDRESS BIT 10 | +---------+----------------+---------+----------------+-----------------------+ | 029 | -MSTRACK | INP | IND | -MASTER ACKNWLDGE | +---------+----------------+---------+----------------+-----------------------+ | 030 | VDD | PWR | VDD | +5 VOLTS | +---------+----------------+---------+----------------+-----------------------+ | 031 | VSS | PWR | VSS | +0 VOLTS | +---------+----------------+---------+----------------+-----------------------+ | 032 | A11 | CIO | ENR | MC ADDRESS BIT 11 | +---------+----------------+---------+----------------+-----------------------+ | 033 | MADE 24 | CIO | ENR | MEMORY ADDR DEC 24 | +---------+----------------+---------+----------------+-----------------------+ | 034 | INT3 | DRV | DNB | INTERRUPT BIT 3 | +---------+----------------+---------+----------------+-----------------------+ | 035 | -CD SETUP | INP | INU | -CARD SETUP | +---------+----------------+---------+----------------+-----------------------+ | 036 | INT2 | DRV | DNB | INTERRUPT BIT 2 | +---------+----------------+---------+----------------+-----------------------+ | 037 | VSS | PWR | VSS | +0 VOLTS | +---------+----------------+---------+----------------+-----------------------+ | 038 | INT1 | DRV | DNB | INTERRUPT BIT 1 | +---------+----------------+---------+----------------+-----------------------+ | 039 | -SLVEACK | INP | IND | -SLAVE ACKNOWLEDGE | +---------+----------------+---------+----------------+-----------------------+ | 040 | -L_ADS | CIO | ENB | -ADDR DATA STROBE | +---------+----------------+---------+----------------+-----------------------+ | 041 | GNR | PWR | GNR | +0 VOLTS | +---------+----------------+---------+----------------+-----------------------+ | 042 | 25MHZ OSC | INP | INU | +25 MHZ OSCILLATOR | +---------+----------------+---------+----------------+-----------------------+ | 043 | GND | PWR | GND | +0 VOLTS | +---------+----------------+---------+----------------+-----------------------+ | 044 | INT0 | DRV | DNB | INTERRUPT BIT 0 | +---------+----------------+---------+----------------+-----------------------+ | 045 | -WDOG | INP | INU | -WATCHDOG | +---------+----------------+---------+----------------+-----------------------+ | 046 | -CMDRSTOUT | DRV | DNB | -COMMAND RESET OUT | +---------+----------------+---------+----------------+-----------------------+ | 047 | -L_EXCPT | CIO | ENB | -L_EXCPT | +---------+----------------+---------+----------------+-----------------------+ | 048 | -SLVEREQ | CIO | ENG | -SLAVE REQUEST | +---------+----------------+---------+----------------+-----------------------+ | 049 | -L_BLAST | CIO | ENB | -BURST LAST | +---------+----------------+---------+----------------+-----------------------+ | 050 | -MSTRREQ | CIO | ENG | -MASTER REQUEST | +---------+----------------+---------+----------------+-----------------------+ | 051 | L_W/-R | CIO | ENB | WRITE/-READ | +---------+----------------+---------+----------------+-----------------------+ | 052 | -L_READY | CIO | ENB | -L_READY | +---------+----------------+---------+----------------+-----------------------+ | 053 | VSS | PWR | VSS | +0 VOLTS | +---------+----------------+---------+----------------+-----------------------+ | 054 | L_AD31 | CIO | ENB | LB ADDR/DATA BIT 31 | +---------+----------------+---------+----------------+-----------------------+ | 055 | L_AD30 | CIO | ENB | LB ADDR/DATA BIT 30 | +---------+----------------+---------+----------------+-----------------------+ | 056 | L_AD29 | CIO | ENB | LB ADDR/DATA BIT 29 | +---------+----------------+---------+----------------+-----------------------+ | 057 | L_AD28 | CIO | ENB | LB ADDR/DATA BIT 28 | +---------+----------------+---------+----------------+-----------------------+ | 058 | L_AD27 | CIO | ENB | LB ADDR/DATA BIT 27 | +---------+----------------+---------+----------------+-----------------------+ | 059 | L_AD26 | CIO | ENB | LB ADDR/DATA BIT 26 | +---------+----------------+---------+----------------+-----------------------+ | 060 | VDD | PWR | VDD | +5 VOLTS | +---------+----------------+---------+----------------+-----------------------+ | 061 | VSS | PWR | VSS | +0 VOLTS | +---------+----------------+---------+----------------+-----------------------+ | 062 | COMP2 | INP | ---- | COMP.RESISTOR 2 | +---------+----------------+---------+----------------+-----------------------+ | 063 | L_AD25 | CIO | ENB | LB ADDR/DATA BIT 25 | +---------+----------------+---------+----------------+-----------------------+ | 064 | L_AD24 | CIO | ENB | LB ADDR/DATA BIT 24 | +---------+----------------+---------+----------------+-----------------------+ | 065 | L_AD23 | CIO | ENB | LB ADDR/DATA BIT 23 | +---------+----------------+---------+----------------+-----------------------+ | 066 | L_AD22 | CIO | ENB | LB ADDR/DATA BIT 22 | +---------+----------------+---------+----------------+-----------------------+ | 067 | L_AD21 | CIO | ENB | LB ADDR/DATA BIT 21 | +---------+----------------+---------+----------------+-----------------------+ | 068 | VSS | PWR | VSS | +0 VOLTS | +---------+----------------+---------+----------------+-----------------------+ | 069 | L_AD20 | CIO | ENB | LB ADDR/DATA BIT 20 | +---------+----------------+---------+----------------+-----------------------+ | 070 | L_AD19 | CIO | ENB | LB ADDR/DATA BIT 19 | +---------+----------------+---------+----------------+-----------------------+ | 071 | VDD | PWR | VDD | +5 VOLTS | +---------+----------------+---------+----------------+-----------------------+ | 072 | GND | PWR | GND | +0 VOLTS | +---------+----------------+---------+----------------+-----------------------+ | 073 | L_AD18 | CIO | ENB | LB ADDR/DATA BIT 18 | +---------+----------------+---------+----------------+-----------------------+ | 074 | L_AD17 | CIO | ENB | LB ADDR/DATA BIT 17 | +---------+----------------+---------+----------------+-----------------------+ | 075 | L_AD16 | CIO | ENB | LB ADDR/DATA BIT 16 | +---------+----------------+---------+----------------+-----------------------+ | 076 | L_AD15 | CIO | ENB | LB ADDR/DATA BIT 15 | +---------+----------------+---------+----------------+-----------------------+ | 077 | VSS | PWR | VSS | +0 VOLTS | +---------+----------------+---------+----------------+-----------------------+ | 078 | L_AD14 | CIO | ENB | LB ADDR/DATA BIT 14 | +---------+----------------+---------+----------------+-----------------------+ | 079 | L_AD13 | CIO | ENB | LB ADDR/DATA BIT 13 | +---------+----------------+---------+----------------+-----------------------+ | 080 | VDD | PWR | VDD | +5 VOLTS | +---------+----------------+---------+----------------+-----------------------+ | 081 | L_AD12 | CIO | ENB | LB ADDR/DATA BIT 12 | +---------+----------------+---------+----------------+-----------------------+ | 082 | L_AD11 | CIO | ENB | LB ADDR/DATA BIT 11 | +---------+----------------+---------+----------------+-----------------------+ | 083 | L_AD10 | CIO | ENB | LB ADDR/DATA BIT 10 | +---------+----------------+---------+----------------+-----------------------+ | 084 | L_AD9 | CIO | ENB | LB ADDR/DATA BIT 9 | +---------+----------------+---------+----------------+-----------------------+ | 085 | VSS | PWR | VSS | +0 VOLTS | +---------+----------------+---------+----------------+-----------------------+ | 086 | L_AD8 | CIO | ENB | LB ADDR/DATA BIT 8 | +---------+----------------+---------+----------------+-----------------------+ | 087 | L_AD7 | CIO | ENB | LB ADDR/DATA BIT 7 | +---------+----------------+---------+----------------+-----------------------+ | 088 | L_AD6 | CIO | ENB | LB ADDR/DATA BIT 6 | +---------+----------------+---------+----------------+-----------------------+ | 089 | L_AD5 | CIO | ENB | LB ADDR/DATA BIT 5 | +---------+----------------+---------+----------------+-----------------------+ | 090 | VDD | PWR | VDD | +5 VOLTS | +---------+----------------+---------+----------------+-----------------------+ | 091 | GNR | PWR | GNR | +0 VOLTS | +---------+----------------+---------+----------------+-----------------------+ | 092 | L_AD4 | CIO | ENB | LB ADDR/DATA BIT 4 | +---------+----------------+---------+----------------+-----------------------+ | 093 | L_AD3 | CIO | ENB | LB ADDR/DATA BIT 3 | +---------+----------------+---------+----------------+-----------------------+ | 094 | L_AD2 | CIO | ENB | LB ADDR/DATA BIT 2 | +---------+----------------+---------+----------------+-----------------------+ | 095 | L_AD1 | CIO | ENB | LB ADDR/DATA BIT 1 | +---------+----------------+---------+----------------+-----------------------+ | 096 | L_AD0 | CIO | ENB | LB ADDR/DATA BIT 0 | +---------+----------------+---------+----------------+-----------------------+ | 097 | VSS | PWR | VSS | +0 VOLTS | +---------+----------------+---------+----------------+-----------------------+ | 098 | L_ADP0 | CIO | ENB | LB PARITY BIT 0 | +---------+----------------+---------+----------------+-----------------------+ | 099 | L_ADP1 | CIO | ENB | LB PARITY BIT 1 | +---------+----------------+---------+----------------+-----------------------+ | 100 | L_ADP2 | CIO | ENB | LB PARITY BIT 2 | +---------+----------------+---------+----------------+-----------------------+ | 101 | GND | PWR | GND | +0 VOLTS | +---------+----------------+---------+----------------+-----------------------+ | 102 | L_ADP3 | CIO | ENB | LB PARITY BIT 3 | +---------+----------------+---------+----------------+-----------------------+ | 103 | -L_BE0 | CIO | ENB | LB BYTE ENABLE 0 | +---------+----------------+---------+----------------+-----------------------+ | 104 | -L_BE1 | CIO | ENB | LB BYTE ENABLE 1 | +---------+----------------+---------+----------------+-----------------------+ | 105 | -L_BE2 | CIO | ENB | LB BYTE ENABLE 2 | +---------+----------------+---------+----------------+-----------------------+ | 106 | TEST_C | INP | INU | TEST C CLOCK | +---------+----------------+---------+----------------+-----------------------+ | 107 | VSS | PWR | VSS | +0 VOLTS | +---------+----------------+---------+----------------+-----------------------+ | 108 | TEST_B | INP | INU | TEST B CLOCK | +---------+----------------+---------+----------------+-----------------------+ | 109 | -L_BE3 | CIO | ENB | LB BYTE ENABLE 3 | +---------+----------------+---------+----------------+-----------------------+ | 110 | VDD | PWR | VDD | +5 VOLTS | +---------+----------------+---------+----------------+-----------------------+ | 111 | APAR3 | CIO | ENR | MC ADDR PARITY 3 | +---------+----------------+---------+----------------+-----------------------+ | 112 | -APAREN | CIO | ENR | -ADDR PARITY ENABLE | +---------+----------------+---------+----------------+-----------------------+ | 113 | A31 | CIO | ENR | MC ADDRESS BIT 31 | +---------+----------------+---------+----------------+-----------------------+ | 114 | A30 | CIO | ENR | MC ADDRESS BIT 30 | +---------+----------------+---------+----------------+-----------------------+ | 115 | VSS | PWR | VSS | +0 VOLTS | +---------+----------------+---------+----------------+-----------------------+ | 116 | A29 | CIO | ENR | MC ADDRESS BIT 29 | +---------+----------------+---------+----------------+-----------------------+ | 117 | A28 | CIO | ENR | MC ADDRESS BIT 28 | +---------+----------------+---------+----------------+-----------------------+ | 118 | A27 | CIO | ENR | MC ADDRESS BIT 27 | +---------+----------------+---------+----------------+-----------------------+ | 119 | TEST_A | INP | INU | TEST A CLOCK | +---------+----------------+---------+----------------+-----------------------+ | 120 | VDD | PWR | VDD | +5 VOLTS | +---------+----------------+---------+----------------+-----------------------+ | 121 | VSS | PWR | VSS | +0 VOLTS | +---------+----------------+---------+----------------+-----------------------+ | 122 | +RAMTSTCLK | INP | INU | +RAM TEST CLOCK | +---------+----------------+---------+----------------+-----------------------+ | 123 | A26 | CIO | ENR | MC ADDRESS BIT 26 | +---------+----------------+---------+----------------+-----------------------+ | 124 | A25 | CIO | ENR | MC ADDRESS BIT 25 | +---------+----------------+---------+----------------+-----------------------+ | 125 | A24 | CIO | ENR | MC ADDRESS BIT 24 | +---------+----------------+---------+----------------+-----------------------+ | 126 | TR 32 | CIO | ENR | TRANSLATE 32 | +---------+----------------+---------+----------------+-----------------------+ | 127 | DPAR3 | CIO | ENR | MC DATA PARITY 3 | +---------+----------------+---------+----------------+-----------------------+ | 128 | VSS | PWR | VSS | +0 VOLTS | +---------+----------------+---------+----------------+-----------------------+ | 129 | D31 | CIO | ENR | MC DATA BIT 31 | +---------+----------------+---------+----------------+-----------------------+ | 130 | D30 | CIO | ENR | MC DATA BIT 30 | +---------+----------------+---------+----------------+-----------------------+ | 131 | D29 | CIO | ENR | MC DATA BIT 29 | +---------+----------------+---------+----------------+-----------------------+ | 132 | D28 | CIO | ENR | MC DATA BIT 28 | +---------+----------------+---------+----------------+-----------------------+ | 133 | VSS | PWR | VSS | +0 VOLTS | +---------+----------------+---------+----------------+-----------------------+ | 134 | 40MHZ OSC | INP | INU | 40 MHZ OSCILLATOR | +---------+----------------+---------+----------------+-----------------------+ | 135 | GNR | PWR | GNR | +0 VOLTS | +---------+----------------+---------+----------------+-----------------------+ | 136 | D27 | CIO | ENR | MC DATA BIT 27 | +---------+----------------+---------+----------------+-----------------------+ | 137 | D26 | CIO | ENR | MC DATA BIT 26 | +---------+----------------+---------+----------------+-----------------------+ | 138 | D25 | CIO | ENR | MC DATA BIT 25 | +---------+----------------+---------+----------------+-----------------------+ | 139 | VSS | PWR | VSS | +0 VOLTS | +---------+----------------+---------+----------------+-----------------------+ | 140 | VDD | PWR | VDD | +5 VOLTS | +---------+----------------+---------+----------------+-----------------------+ | 141 | D24 | CIO | ENR | MC DATA BIT 24 | +---------+----------------+---------+----------------+-----------------------+ | 142 | DPAR2 | CIO | ENR | MC DATA PARITY 2 | +---------+----------------+---------+----------------+-----------------------+ | 143 | D23 | CIO | ENR | MC DATA BIT 23 | +---------+----------------+---------+----------------+-----------------------+ | 144 | D22 | CIO | ENR | MC DATA BIT 22 | +---------+----------------+---------+----------------+-----------------------+ | 145 | VSS | PWR | VSS | +0 VOLTS | +---------+----------------+---------+----------------+-----------------------+ | 146 | D21 | CIO | ENR | MC DATA BIT 21 | +---------+----------------+---------+----------------+-----------------------+ | 147 | D20 | CIO | ENR | MC DATA BIT 20 | +---------+----------------+---------+----------------+-----------------------+ | 148 | D19 | CIO | ENR | MC DATA BIT 19 | +---------+----------------+---------+----------------+-----------------------+ | 149 | D18 | CIO | ENR | MC DATA BIT 18 | +---------+----------------+---------+----------------+-----------------------+ | 150 | VDD | PWR | VDD | +5 VOLTS | +---------+----------------+---------+----------------+-----------------------+ | 151 | VSS | PWR | VSS | +0 VOLTS | +---------+----------------+---------+----------------+-----------------------+ | 152 | D17 | CIO | ENR | MC DATA BIT 17 | +---------+----------------+---------+----------------+-----------------------+ | 153 | D16 | CIO | ENR | MC DATA BIT 16 | +---------+----------------+---------+----------------+-----------------------+ | 154 | -SFDBKRTN | INP | INU | SEL.FEEDBACK RTN | +---------+----------------+---------+----------------+-----------------------+ | 155 | -MSDR | CIO | ENT | MUX'D STR DATA REQ | +---------+----------------+---------+----------------+-----------------------+ | 156 | -SDR1 | CIO | ENT | STREAM.DATA REQ 1 | +---------+----------------+---------+----------------+-----------------------+ | 157 | VSS | PWR | VSS | +0 VOLTS | +---------+----------------+---------+----------------+-----------------------+ | 158 | -SDR0 | CIO | ENT | STREAM.DATA REQ 0 | +---------+----------------+---------+----------------+-----------------------+ | 159 | -REFRESH | INP | INU | -REFRESH | +---------+----------------+---------+----------------+-----------------------+ | 160 | -IRQ A | CIO | ENR | -INTERRUPT REQ A | +---------+----------------+---------+----------------+-----------------------+ | 161 | -S1 | CIO | ENG | -STATUS 1 | +---------+----------------+---------+----------------+-----------------------+ | 162 | -IRQ B | CIO | ENR | -INTERRUPT REQ B | +---------+----------------+---------+----------------+-----------------------+ | 163 | -CMD CLK | INP | INU | -COMMAND CLOCK | +---------+----------------+---------+----------------+-----------------------+ | 164 | GND | PWR | GND | +0 VOLTS | +---------+----------------+---------+----------------+-----------------------+ | 165 | -SD STROBE | CIO | ENG | -STR DATA STROBE | +---------+----------------+---------+----------------+-----------------------+ | 166 | -S0 | CIO | ENG | -STATUS 0 | +---------+----------------+---------+----------------+-----------------------+ | 167 | DPAR1 | CIO | ENR | MC DATA PARITY 1 | +---------+----------------+---------+----------------+-----------------------+ | 168 | -ADL | CIO | ENG | -ADDR DATA LATCH | +---------+----------------+---------+----------------+-----------------------+ | 169 | -SDSTRCLK | INP | INU | -STR DATA STR CLK | +---------+----------------+---------+----------------+-----------------------+ | 170 | VSS | PWR | VSS | +0 VOLTS | +---------+----------------+---------+----------------+-----------------------+ | 171 | -CMD | CIO | ENG | -COMMAND | +---------+----------------+---------+----------------+-----------------------+ | 172 | -BE3 | CIO | ENR | -BYTE ENABLE 3 | +---------+----------------+---------+----------------+-----------------------+ | 173 | -BE2 | CIO | ENR | -BYTE ENABLE 2 | +---------+----------------+---------+----------------+-----------------------+ | 174 | -BE1 | CIO | ENR | -BYTE ENABLE 1 | +---------+----------------+---------+----------------+-----------------------+ | 175 | VSS | PWR | VSS | +0 VOLTS | +---------+----------------+---------+----------------+-----------------------+ | 176 | -BE0 | CIO | ENR | -BYTE ENABLE 0 | +---------+----------------+---------+----------------+-----------------------+ | 177 | -SBHE | CIO | ENR | -SYS BYTE HIGH EN | +---------+----------------+---------+----------------+-----------------------+ | 178 | D15 | CIO | ENR | MC DATA BIT 15 | +---------+----------------+---------+----------------+-----------------------+ | 179 | -ICT | INP | INU | -IN-CIRCUIT TEST PIN | +---------+----------------+---------+----------------+-----------------------+ | 180 | VDD | PWR | VDD | +5 VOLTS | +---------+----------------+---------+----------------+-----------------------+ | 181 | VSS | PWR | VSS | +0 VOLTS | +---------+----------------+---------+----------------+-----------------------+ | 182 | +BMSTREN | DRV | DNB | +BUSMASTER ENABLE | +---------+----------------+---------+----------------+-----------------------+ | 183 | D14 | CIO | ENR | MC DATA BIT 14 | +---------+----------------+---------+----------------+-----------------------+ | 184 | D13 | CIO | ENR | MC DATA BIT 13 | +---------+----------------+---------+----------------+-----------------------+ | 185 | D12 | CIO | ENR | MC DATA BIT 12 | +---------+----------------+---------+----------------+-----------------------+ | 186 | D11 | CIO | ENR | MC DATA BIT 11 | +---------+----------------+---------+----------------+-----------------------+ | 187 | VSS | PWR | VSS | +0 VOLTS | +---------+----------------+---------+----------------+-----------------------+ | 188 | D10 | CIO | ENR | MC DATA BIT 10 | +---------+----------------+---------+----------------+-----------------------+ | 189 | D9 | CIO | ENR | MC DATA BIT 9 | +---------+----------------+---------+----------------+-----------------------+ | 190 | VDD | PWR | VDD | +5 VOLTS | +---------+----------------+---------+----------------+-----------------------+ | 191 | D8 | CIO | ENR | MC DATA BIT 8 | +---------+----------------+---------+----------------+-----------------------+ | 192 | -DS 16 RTN | INP | INU | -DATA SIZE 16 RTN | +---------+----------------+---------+----------------+-----------------------+ | 193 | CHRESET | INP | INU | CHANNEL RESET | +---------+----------------+---------+----------------+-----------------------+ | 194 | D7 | CIO | ENR | MC DATA BIT 7 | +---------+----------------+---------+----------------+-----------------------+ | 195 | VSS | PWR | VSS | +0 VOLTS | +---------+----------------+---------+----------------+-----------------------+ | 196 | D6 | CIO | ENR | MC DATA BIT 6 | +---------+----------------+---------+----------------+-----------------------+ | 197 | D5 | CIO | ENR | MC DATA BIT 5 | +---------+----------------+---------+----------------+-----------------------+ | 198 | D4 | CIO | ENR | MC DATA BIT 4 | +---------+----------------+---------+----------------+-----------------------+ | 199 | D3 | CIO | ENR | MC DATA BIT 3 | +---------+----------------+---------+----------------+-----------------------+ | 200 | VSS | PWR | VSS | +0 VOLTS | +---------+----------------+---------+----------------+-----------------------+ | 201 | D2 | CIO | ENR | MC DATA BIT 2 | +---------+----------------+---------+----------------+-----------------------+ | 202 | D1 | CIO | ENR | MC DATA BIT 1 | +---------+----------------+---------+----------------+-----------------------+ | 203 | D0 | CIO | ENR | MC DATA BIT 0 | +---------+----------------+---------+----------------+-----------------------+ | 204 | CHRDYRTN | INP | INU | CHANNEL READY RTN | +---------+----------------+---------+----------------+-----------------------+ | 205 | M/-IO | CIO | ENR | MEMORY/-IO | +---------+----------------+---------+----------------+-----------------------+ | 206 | GNR | PWR | GNR | +0 VOLTS | +---------+----------------+---------+----------------+-----------------------+ | 207 | -CHCK | CIO | ENR | -CHANNEL CHECK | +---------+----------------+---------+----------------+-----------------------+ | 208 | DPAR0 | CIO | ENR | MC DATA PARITY 0 | +---------+----------------+---------+----------------+-----------------------+ | 209 | -DPAREN | CIO | ENR | -DATA PARITY EN | +---------+----------------+---------+----------------+-----------------------+ | 210 | VDD | PWR | VDD | +5 VOLTS | +---------+----------------+---------+----------------+-----------------------+ | 211 | GND | PWR | GND | +0 VOLTS | +---------+----------------+---------+----------------+-----------------------+ | 212 | ARB3 | CIO | ENR | ARBITRATION BIT 3 | +---------+----------------+---------+----------------+-----------------------+ | 213 | -IRQ D | CIO | ENR | -INTERRUPT REQ D | +---------+----------------+---------+----------------+-----------------------+ | 214 | VSS | PWR | VSS | +0 VOLTS | +---------+----------------+---------+----------------+-----------------------+ | 215 | ARB2 | CIO | ENR | ARBITRATION BIT 2 | +---------+----------------+---------+----------------+-----------------------+ | 216 | ARB1 | CIO | ENR | ARBITRATION BIT 1 | +---------+----------------+---------+----------------+-----------------------+ | 217 | ARB0 | CIO | ENR | ARBITRATION BIT 0 | +---------+----------------+---------+----------------+-----------------------+ | 218 | -IRQ C | CIO | ENR | -INTERRUPT REQ C | +---------+----------------+---------+----------------+-----------------------+ | 219 | -BURST | CIO | ENR | -BURST | +---------+----------------+---------+----------------+-----------------------+ | 220 | VDD | PWR | VDD | +5 VOLTS | +---------+----------------+---------+----------------+-----------------------+ | 221 | VSS | PWR | VSS | +0 VOLTS | +---------+----------------+---------+----------------+-----------------------+ | 222 | -PREEMPT | CIO | ENR | -PREEMPT | +---------+----------------+---------+----------------+-----------------------+ | 223 | A12 | CIO | ENR | MC ADDRESS BIT 12 | +---------+----------------+---------+----------------+-----------------------+ | 224 | A13 | CIO | ENR | MC ADDRESS BIT 13 | +---------+----------------+---------+----------------+-----------------------+ | 225 | A14 | CIO | ENR | MC ADDRESS BIT 14 | +---------+----------------+---------+----------------+-----------------------+ | 226 | A0 | CIO | ENR | MC ADDRESS BIT 0 | +---------+----------------+---------+----------------+-----------------------+ | 227 | VSS | PWR | VSS | +0 VOLTS | +---------+----------------+---------+----------------+-----------------------+ | 228 | A1 | CIO | ENR | MC ADDRESS BIT 1 | +---------+----------------+---------+----------------+-----------------------+ | 229 | A2 | CIO | ENR | MC ADDRESS BIT 2 | +---------+----------------+---------+----------------+-----------------------+ | 230 | A15 | CIO | ENR | MC ADDRESS BIT 15 | +---------+----------------+---------+----------------+-----------------------+ | 231 | VSS | PWR | VSS | +0 VOLTS | +---------+----------------+---------+----------------+-----------------------+ | 232 | APAR1 | CIO | ENR | MC ADDRESS PARITY 1 | +---------+----------------+---------+----------------+-----------------------+ | 233 | A16 | CIO | ENR | MC ADDRESS BIT 16 | +---------+----------------+---------+----------------+-----------------------+ | 234 | A17 | CIO | ENR | MC ADDRESS BIT 17 | +---------+----------------+---------+----------------+-----------------------+ | 235 | VSS | PWR | VSS | +0 VOLTS | +---------+----------------+---------+----------------+-----------------------+ | 236 | -CD DS 16 | DRV | DNG | -CARD DATA SIZE 16 | +---------+----------------+---------+----------------+-----------------------+ | 237 | A3 | CIO | ENR | MC ADDRESS BIT 3 | +---------+----------------+---------+----------------+-----------------------+ | 238 | A4 | CIO | ENR | MC ADDRESS BIT 4 | +---------+----------------+---------+----------------+-----------------------+ | 239 | COMP1 | INP | ---- | COMP.RESISTOR 1 | +---------+----------------+---------+----------------+-----------------------+ | 240 | VDD | PWR | VDD | +5 VOLTS | +---------+----------------+---------+----------------+-----------------------+
In the following table, 'MC' denotes Micro Channel, and 'LB' denotes Local (CFE) Bus. Circuit type descriptions are given in Table 19
Note that the IRQx, -SLVEREQ, and -MSTRREQ require CIOs in support of ICT, although they have no functional input.
Note to Miami chip designers - Although all external bus signal names are given in vendor notation (Bit 0 = LSB), the Local Bus is given in IBM notation (Bit 0 = MSB) for all internal logics.
Table 18. Miami I/O by Pin Name
+================+=========+=========+================+=======================+ | PIN NAME | PIN # | I/O | CIRCUIT TYPE | SIGNAL NAME | +================+=========+=========+================+=======================+ | -16/32 DETECT | 025 | INP | INU | -16/32 BIT DETECT | +----------------+---------+---------+----------------+-----------------------+ | 25MHZ OSC | 042 | INP | INU | +25 MHZ OSCILLATOR | +----------------+---------+---------+----------------+-----------------------+ | 40MHZ OSC | 134 | INP | INU | 40 MHZ OSCILLATOR | +----------------+---------+---------+----------------+-----------------------+ | A0 | 226 | CIO | ENR | MC ADDRESS BIT 0 | +----------------+---------+---------+----------------+-----------------------+ | A1 | 228 | CIO | ENR | MC ADDRESS BIT 1 | +----------------+---------+---------+----------------+-----------------------+ | A2 | 229 | CIO | ENR | MC ADDRESS BIT 2 | +----------------+---------+---------+----------------+-----------------------+ | A3 | 237 | CIO | ENR | MC ADDRESS BIT 3 | +----------------+---------+---------+----------------+-----------------------+ | A4 | 238 | CIO | ENR | MC ADDRESS BIT 4 | +----------------+---------+---------+----------------+-----------------------+ | A5 | 003 | CIO | ENR | MC ADDRESS BIT 5 | +----------------+---------+---------+----------------+-----------------------+ | A6 | 008 | CIO | ENR | MC ADDRESS BIT 6 | +----------------+---------+---------+----------------+-----------------------+ | A7 | 012 | CIO | ENR | MC ADDRESS BIT 7 | +----------------+---------+---------+----------------+-----------------------+ | A8 | 016 | CIO | ENR | MC ADDRESS BIT 8 | +----------------+---------+---------+----------------+-----------------------+ | A9 | 023 | CIO | ENR | MC ADDRESS BIT 9 | +----------------+---------+---------+----------------+-----------------------+ | A10 | 028 | CIO | ENR | MC ADDRESS BIT 10 | +----------------+---------+---------+----------------+-----------------------+ | A11 | 032 | CIO | ENR | MC ADDRESS BIT 11 | +----------------+---------+---------+----------------+-----------------------+ | A12 | 223 | CIO | ENR | MC ADDRESS BIT 12 | +----------------+---------+---------+----------------+-----------------------+ | A13 | 224 | CIO | ENR | MC ADDRESS BIT 13 | +----------------+---------+---------+----------------+-----------------------+ | A14 | 225 | CIO | ENR | MC ADDRESS BIT 14 | +----------------+---------+---------+----------------+-----------------------+ | A15 | 230 | CIO | ENR | MC ADDRESS BIT 15 | +----------------+---------+---------+----------------+-----------------------+ | A16 | 233 | CIO | ENR | MC ADDRESS BIT 16 | +----------------+---------+---------+----------------+-----------------------+ | A17 | 234 | CIO | ENR | MC ADDRESS BIT 17 | +----------------+---------+---------+----------------+-----------------------+ | A18 | 004 | CIO | ENR | MC ADDRESS BIT 18 | +----------------+---------+---------+----------------+-----------------------+ | A19 | 006 | CIO | ENR | MC ADDRESS BIT 19 | +----------------+---------+---------+----------------+-----------------------+ | A20 | 011 | CIO | ENR | MC ADDRESS BIT 20 | +----------------+---------+---------+----------------+-----------------------+ | A21 | 019 | CIO | ENR | MC ADDRESS BIT 21 | +----------------+---------+---------+----------------+-----------------------+ | A22 | 022 | CIO | ENR | MC ADDRESS BIT 22 | +----------------+---------+---------+----------------+-----------------------+ | A23 | 024 | CIO | ENR | MC ADDRESS BIT 23 | +----------------+---------+---------+----------------+-----------------------+ | A24 | 125 | CIO | ENR | MC ADDRESS BIT 24 | +----------------+---------+---------+----------------+-----------------------+ | A25 | 124 | CIO | ENR | MC ADDRESS BIT 25 | +----------------+---------+---------+----------------+-----------------------+ | A26 | 123 | CIO | ENR | MC ADDRESS BIT 26 | +----------------+---------+---------+----------------+-----------------------+ | A27 | 118 | CIO | ENR | MC ADDRESS BIT 27 | +----------------+---------+---------+----------------+-----------------------+ | A28 | 117 | CIO | ENR | MC ADDRESS BIT 28 | +----------------+---------+---------+----------------+-----------------------+ | A29 | 116 | CIO | ENR | MC ADDRESS BIT 29 | +----------------+---------+---------+----------------+-----------------------+ | A30 | 114 | CIO | ENR | MC ADDRESS BIT 30 | +----------------+---------+---------+----------------+-----------------------+ | A31 | 113 | CIO | ENR | MC ADDRESS BIT 31 | +----------------+---------+---------+----------------+-----------------------+ | -ADL | 168 | CIO | ENG | -ADDR DATA LATCH | +----------------+---------+---------+----------------+-----------------------+ | APAR0 | 015 | CIO | ENR | MC ADDRESS PARITY 0 | +----------------+---------+---------+----------------+-----------------------+ | APAR1 | 232 | CIO | ENR | MC ADDRESS PARITY 1 | +----------------+---------+---------+----------------+-----------------------+ | APAR2 | 027 | CIO | ENR | MC ADDRESS PARITY 2 | +----------------+---------+---------+----------------+-----------------------+ | APAR3 | 111 | CIO | ENR | MC ADDRESS PARITY 3 | +----------------+---------+---------+----------------+-----------------------+ | -APAREN | 112 | CIO | ENR | -ADDR PARITY ENABLE | +----------------+---------+---------+----------------+-----------------------+ | ARB0 | 217 | CIO | ENR | ARBITRATION BIT 0 | +----------------+---------+---------+----------------+-----------------------+ | ARB1 | 216 | CIO | ENR | ARBITRATION BIT 1 | +----------------+---------+---------+----------------+-----------------------+ | ARB2 | 215 | CIO | ENR | ARBITRATION BIT 2 | +----------------+---------+---------+----------------+-----------------------+ | ARB3 | 212 | CIO | ENR | ARBITRATION BIT 3 | +----------------+---------+---------+----------------+-----------------------+ | ARB/-GNT | 013 | INP | INU | ARB/-GNT | +----------------+---------+---------+----------------+-----------------------+ | -BE0 | 176 | CIO | ENR | -BYTE ENABLE 0 | +----------------+---------+---------+----------------+-----------------------+ | -BE1 | 174 | CIO | ENR | -BYTE ENABLE 1 | +----------------+---------+---------+----------------+-----------------------+ | -BE2 | 173 | CIO | ENR | -BYTE ENABLE 2 | +----------------+---------+---------+----------------+-----------------------+ | -BE3 | 172 | CIO | ENR | -BYTE ENABLE 3 | +----------------+---------+---------+----------------+-----------------------+ | +BMSTREN | 182 | DRV | DNB | +BUSMASTER ENABLE | +----------------+---------+---------+----------------+-----------------------+ | -BURST | 219 | CIO | ENR | -BURST | +----------------+---------+---------+----------------+-----------------------+ | CD CHRDY | 005 | DRV | DNG | CD CHRDY | +----------------+---------+---------+----------------+-----------------------+ | -CD DS 16 | 236 | DRV | DNG | -CARD DATA SIZE 16 | +----------------+---------+---------+----------------+-----------------------+ | -CD DS 32 | 021 | DRV | DNG | -CARD DATA SIZE 32 | +----------------+---------+---------+----------------+-----------------------+ | -CD SETUP | 035 | INP | INU | -CARD SETUP | +----------------+---------+---------+----------------+-----------------------+ | -CD SFDBK | 009 | DRV | DNG | CARD SEL FEEDBACK | +----------------+---------+---------+----------------+-----------------------+ | -CHCK | 207 | CIO | ENR | -CHANNEL CHECK | +----------------+---------+---------+----------------+-----------------------+ | CHRDYRTN | 204 | INP | INU | CHANNEL READY RTN | +----------------+---------+---------+----------------+-----------------------+ | CHRESET | 193 | INP | INU | CHANNEL RESET | +----------------+---------+---------+----------------+-----------------------+ | -CMD | 171 | CIO | ENG | -COMMAND | +----------------+---------+---------+----------------+-----------------------+ | -CMD CLK | 163 | INP | INU | -COMMAND CLOCK | +----------------+---------+---------+----------------+-----------------------+ | -CMDRSTOUT | 046 | DRV | DNB | -COMMAND RESET OUT | +----------------+---------+---------+----------------+-----------------------+ | COMP1 | 239 | INP | ---- | COMP.RESISTOR 1 | +----------------+---------+---------+----------------+-----------------------+ | COMP2 | 062 | INP | ---- | COMP.RESISTOR 2 | +----------------+---------+---------+----------------+-----------------------+ | D0 | 203 | CIO | ENR | MC DATA BIT 0 | +----------------+---------+---------+----------------+-----------------------+ | D1 | 202 | CIO | ENR | MC DATA BIT 1 | +----------------+---------+---------+----------------+-----------------------+ | D2 | 201 | CIO | ENR | MC DATA BIT 2 | +----------------+---------+---------+----------------+-----------------------+ | D3 | 199 | CIO | ENR | MC DATA BIT 3 | +----------------+---------+---------+----------------+-----------------------+ | D4 | 198 | CIO | ENR | MC DATA BIT 4 | +----------------+---------+---------+----------------+-----------------------+ | D5 | 197 | CIO | ENR | MC DATA BIT 5 | +----------------+---------+---------+----------------+-----------------------+ | D6 | 196 | CIO | ENR | MC DATA BIT 6 | +----------------+---------+---------+----------------+-----------------------+ | D7 | 194 | CIO | ENR | MC DATA BIT 7 | +----------------+---------+---------+----------------+-----------------------+ | D8 | 191 | CIO | ENR | MC DATA BIT 8 | +----------------+---------+---------+----------------+-----------------------+ | D9 | 189 | CIO | ENR | MC DATA BIT 9 | +----------------+---------+---------+----------------+-----------------------+ | D10 | 188 | CIO | ENR | MC DATA BIT 10 | +----------------+---------+---------+----------------+-----------------------+ | D11 | 186 | CIO | ENR | MC DATA BIT 11 | +----------------+---------+---------+----------------+-----------------------+ | D12 | 185 | CIO | ENR | MC DATA BIT 12 | +----------------+---------+---------+----------------+-----------------------+ | D13 | 184 | CIO | ENR | MC DATA BIT 13 | +----------------+---------+---------+----------------+-----------------------+ | D14 | 183 | CIO | ENR | MC DATA BIT 14 | +----------------+---------+---------+----------------+-----------------------+ | D15 | 178 | CIO | ENR | MC DATA BIT 15 | +----------------+---------+---------+----------------+-----------------------+ | D16 | 153 | CIO | ENR | MC DATA BIT 16 | +----------------+---------+---------+----------------+-----------------------+ | D17 | 152 | CIO | ENR | MC DATA BIT 17 | +----------------+---------+---------+----------------+-----------------------+ | D18 | 149 | CIO | ENR | MC DATA BIT 18 | +----------------+---------+---------+----------------+-----------------------+ | D19 | 148 | CIO | ENR | MC DATA BIT 19 | +----------------+---------+---------+----------------+-----------------------+ | D20 | 147 | CIO | ENR | MC DATA BIT 20 | +----------------+---------+---------+----------------+-----------------------+ | D21 | 146 | CIO | ENR | MC DATA BIT 21 | +----------------+---------+---------+----------------+-----------------------+ | D22 | 144 | CIO | ENR | MC DATA BIT 22 | +----------------+---------+---------+----------------+-----------------------+ | D23 | 143 | CIO | ENR | MC DATA BIT 23 | +----------------+---------+---------+----------------+-----------------------+ | D24 | 141 | CIO | ENR | MC DATA BIT 24 | +----------------+---------+---------+----------------+-----------------------+ | D25 | 138 | CIO | ENR | MC DATA BIT 25 | +----------------+---------+---------+----------------+-----------------------+ | D26 | 137 | CIO | ENR | MC DATA BIT 26 | +----------------+---------+---------+----------------+-----------------------+ | D27 | 136 | CIO | ENR | MC DATA BIT 27 | +----------------+---------+---------+----------------+-----------------------+ | D28 | 132 | CIO | ENR | MC DATA BIT 28 | +----------------+---------+---------+----------------+-----------------------+ | D29 | 131 | CIO | ENR | MC DATA BIT 29 | +----------------+---------+---------+----------------+-----------------------+ | D30 | 130 | CIO | ENR | MC DATA BIT 30 | +----------------+---------+---------+----------------+-----------------------+ | D31 | 129 | CIO | ENR | MC DATA BIT 31 | +----------------+---------+---------+----------------+-----------------------+ | DPAR0 | 208 | CIO | ENR | MC DATA PARITY 0 | +----------------+---------+---------+----------------+-----------------------+ | DPAR1 | 167 | CIO | ENR | MC DATA PARITY 1 | +----------------+---------+---------+----------------+-----------------------+ | DPAR2 | 142 | CIO | ENR | MC DATA PARITY 2 | +----------------+---------+---------+----------------+-----------------------+ | DPAR3 | 127 | CIO | ENR | MC DATA PARITY 3 | +----------------+---------+---------+----------------+-----------------------+ | -DPAREN | 209 | CIO | ENR | -DATA PARITY EN | +----------------+---------+---------+----------------+-----------------------+ | -DS 16 RTN | 192 | INP | INU | -DATA SIZE 16 RTN | +----------------+---------+---------+----------------+-----------------------+ | -DS 32 RTN | 017 | INP | INU | -DATA SIZE 32 RTN | +----------------+---------+---------+----------------+-----------------------+ | GND | 018 | PWR | GND | +0 VOLTS | +----------------+---------+---------+----------------+-----------------------+ | GND | 043 | PWR | GND | +0 VOLTS | +----------------+---------+---------+----------------+-----------------------+ | GND | 072 | PWR | GND | +0 VOLTS | +----------------+---------+---------+----------------+-----------------------+ | GND | 101 | PWR | GND | +0 VOLTS | +----------------+---------+---------+----------------+-----------------------+ | GND | 164 | PWR | GND | +0 VOLTS | +----------------+---------+---------+----------------+-----------------------+ | GND | 211 | PWR | GND | +0 VOLTS | +----------------+---------+---------+----------------+-----------------------+ | GNR | 041 | PWR | GNR | +0 VOLTS | +----------------+---------+---------+----------------+-----------------------+ | GNR | 091 | PWR | GNR | +0 VOLTS | +----------------+---------+---------+----------------+-----------------------+ | GNR | 135 | PWR | GNR | +0 VOLTS | +----------------+---------+---------+----------------+-----------------------+ | GNR | 206 | PWR | GNR | +0 VOLTS | +----------------+---------+---------+----------------+-----------------------+ | -ICT | 179 | INP | INU | -IN CIRCUIT TEST PIN | +----------------+---------+---------+----------------+-----------------------+ | INT0 | 044 | DRV | DNB | INTERRUPT BIT 0 | +----------------+---------+---------+----------------+-----------------------+ | INT1 | 038 | DRV | DNB | INTERRUPT BIT 1 | +----------------+---------+---------+----------------+-----------------------+ | INT2 | 036 | DRV | DNB | INTERRUPT BIT 2 | +----------------+---------+---------+----------------+-----------------------+ | INT3 | 034 | DRV | DNB | INTERRUPT BIT 3 | +----------------+---------+---------+----------------+-----------------------+ | -IRQ A | 160 | CIO | ENR | -INTERRUPT REQ 0 | +----------------+---------+---------+----------------+-----------------------+ | -IRQ B | 162 | CIO | ENR | -INTERRUPT REQ 1 | +----------------+---------+---------+----------------+-----------------------+ | -IRQ C | 218 | CIO | ENR | -INTERRUPT REQ 2 | +----------------+---------+---------+----------------+-----------------------+ | -IRQ D | 213 | CIO | ENR | -INTERRUPT REQ 3 | +----------------+---------+---------+----------------+-----------------------+ | L_AD0 | 096 | CIO | ENB | LB ADDR/DATA BIT 0 | +----------------+---------+---------+----------------+-----------------------+ | L_AD1 | 095 | CIO | ENB | LB ADDR/DATA BIT 1 | +----------------+---------+---------+----------------+-----------------------+ | L_AD2 | 094 | CIO | ENB | LB ADDR/DATA BIT 2 | +----------------+---------+---------+----------------+-----------------------+ | L_AD3 | 093 | CIO | ENB | LB ADDR/DATA BIT 3 | +----------------+---------+---------+----------------+-----------------------+ | L_AD4 | 092 | CIO | ENB | LB ADDR/DATA BIT 4 | +----------------+---------+---------+----------------+-----------------------+ | L_AD5 | 089 | CIO | ENB | LB ADDR/DATA BIT 5 | +----------------+---------+---------+----------------+-----------------------+ | L_AD6 | 088 | CIO | ENB | LB ADDR/DATA BIT 6 | +----------------+---------+---------+----------------+-----------------------+ | L_AD7 | 087 | CIO | ENB | LB ADDR/DATA BIT 7 | +----------------+---------+---------+----------------+-----------------------+ | L_AD8 | 086 | CIO | ENB | LB ADDR/DATA BIT 8 | +----------------+---------+---------+----------------+-----------------------+ | L_AD9 | 084 | CIO | ENB | LB ADDR/DATA BIT 9 | +----------------+---------+---------+----------------+-----------------------+ | L_AD10 | 083 | CIO | ENB | LB ADDR/DATA BIT 10 | +----------------+---------+---------+----------------+-----------------------+ | L_AD11 | 082 | CIO | ENB | LB ADDR/DATA BIT 11 | +----------------+---------+---------+----------------+-----------------------+ | L_AD12 | 081 | CIO | ENB | LB ADDR/DATA BIT 12 | +----------------+---------+---------+----------------+-----------------------+ | L_AD13 | 079 | CIO | ENB | LB ADDR/DATA BIT 13 | +----------------+---------+---------+----------------+-----------------------+ | L_AD14 | 078 | CIO | ENB | LB ADDR/DATA BIT 14 | +----------------+---------+---------+----------------+-----------------------+ | L_AD15 | 076 | CIO | ENB | LB ADDR/DATA BIT 15 | +----------------+---------+---------+----------------+-----------------------+ | L_AD16 | 075 | CIO | ENB | LB ADDR/DATA BIT 16 | +----------------+---------+---------+----------------+-----------------------+ | L_AD17 | 074 | CIO | ENB | LB ADDR/DATA BIT 17 | +----------------+---------+---------+----------------+-----------------------+ | L_AD18 | 073 | CIO | ENB | LB ADDR/DATA BIT 18 | +----------------+---------+---------+----------------+-----------------------+ | L_AD19 | 070 | CIO | ENB | LB ADDR/DATA BIT 19 | +----------------+---------+---------+----------------+-----------------------+ | L_AD20 | 069 | CIO | ENB | LB ADDR/DATA BIT 20 | +----------------+---------+---------+----------------+-----------------------+ | L_AD21 | 067 | CIO | ENB | LB ADDR/DATA BIT 21 | +----------------+---------+---------+----------------+-----------------------+ | L_AD22 | 066 | CIO | ENB | LB ADDR/DATA BIT 22 | +----------------+---------+---------+----------------+-----------------------+ | L_AD23 | 065 | CIO | ENB | LB ADDR/DATA BIT 23 | +----------------+---------+---------+----------------+-----------------------+ | L_AD24 | 064 | CIO | ENB | LB ADDR/DATA BIT 24 | +----------------+---------+---------+----------------+-----------------------+ | L_AD25 | 063 | CIO | ENB | LB ADDR/DATA BIT 25 | +----------------+---------+---------+----------------+-----------------------+ | L_AD26 | 059 | CIO | ENB | LB ADDR/DATA BIT 26 | +----------------+---------+---------+----------------+-----------------------+ | L_AD27 | 058 | CIO | ENB | LB ADDR/DATA BIT 27 | +----------------+---------+---------+----------------+-----------------------+ | L_AD28 | 057 | CIO | ENB | LB ADDR/DATA BIT 28 | +----------------+---------+---------+----------------+-----------------------+ | L_AD29 | 056 | CIO | ENB | LB ADDR/DATA BIT 29 | +----------------+---------+---------+----------------+-----------------------+ | L_AD30 | 055 | CIO | ENB | LB ADDR/DATA BIT 30 | +----------------+---------+---------+----------------+-----------------------+ | L_AD31 | 054 | CIO | ENB | LB ADDR/DATA BIT 31 | +----------------+---------+---------+----------------+-----------------------+ | L_ADP0 | 098 | CIO | ENB | LB PARITY BIT 0 | +----------------+---------+---------+----------------+-----------------------+ | L_ADP1 | 099 | CIO | ENB | LB PARITY BIT 1 | +----------------+---------+---------+----------------+-----------------------+ | L_ADP2 | 100 | CIO | ENB | LB PARITY BIT 2 | +----------------+---------+---------+----------------+-----------------------+ | L_ADP3 | 102 | CIO | ENB | LB PARITY BIT 3 | +----------------+---------+---------+----------------+-----------------------+ | -L_ADS | 040 | CIO | ENB | -ADDR DATA STROBE | +----------------+---------+---------+----------------+-----------------------+ | -L_BE0 | 103 | CIO | ENB | LB BYTE ENABLE 0 | +----------------+---------+---------+----------------+-----------------------+ | -L_BE1 | 104 | CIO | ENB | LB BYTE ENABLE 1 | +----------------+---------+---------+----------------+-----------------------+ | -L_BE2 | 105 | CIO | ENB | LB BYTE ENABLE 2 | +----------------+---------+---------+----------------+-----------------------+ | -L_BE3 | 109 | CIO | ENB | LB BYTE ENABLE 3 | +----------------+---------+---------+----------------+-----------------------+ | -L_BLAST | 049 | CIO | ENB | -BURST LAST | +----------------+---------+---------+----------------+-----------------------+ | -L_EXCPT | 047 | CIO | ENB | -L_EXCPT | +----------------+---------+---------+----------------+-----------------------+ | -L_READY | 052 | CIO | ENB | -L_READY | +----------------+---------+---------+----------------+-----------------------+ | L_W/-R | 051 | CIO | ENB | WRITE/-READ | +----------------+---------+---------+----------------+-----------------------+ | MADE 24 | 033 | CIO | ENR | MEMORY ADDR DEC 24 | +----------------+---------+---------+----------------+-----------------------+ | M/-IO | 205 | CIO | ENR | MEMORY/-IO | +----------------+---------+---------+----------------+-----------------------+ | -MSDR | 155 | CIO | ENT | MUX'D STR DATA REQ | +----------------+---------+---------+----------------+-----------------------+ | -MSTRACK | 029 | INP | IND | -MASTER ACKNWLDGE | +----------------+---------+---------+----------------+-----------------------+ | -MSTRREQ | 050 | CIO | ENG | -MASTER REQUEST | +----------------+---------+---------+----------------+-----------------------+ | -PREEMPT | 222 | CIO | ENR | -PREEMPT | +----------------+---------+---------+----------------+-----------------------+ | +RAMTSTCLK | 122 | INP | INU | +RAM TEST CLOCK | +----------------+---------+---------+----------------+-----------------------+ | -REFRESH | 159 | INP | INU | -REFRESH | +----------------+---------+---------+----------------+-----------------------+ | -S0 | 166 | CIO | ENG | -STATUS 0 | +----------------+---------+---------+----------------+-----------------------+ | -S1 | 161 | CIO | ENG | -STATUS 1 | +----------------+---------+---------+----------------+-----------------------+ | -SBHE | 177 | CIO | ENR | -SYS BYTE HIGH EN | +----------------+---------+---------+----------------+-----------------------+ | -SDR0 | 158 | CIO | ENT | STREAM.DATA REQ 0 | +----------------+---------+---------+----------------+-----------------------+ | -SDR1 | 156 | CIO | ENT | STREAM.DATA REQ 1 | +----------------+---------+---------+----------------+-----------------------+ | -SDSTRCLK | 169 | INP | INU | -STR DATA STR CLK | +----------------+---------+---------+----------------+-----------------------+ | -SD STROBE | 165 | CIO | ENG | -STR DATA STROBE | +----------------+---------+---------+----------------+-----------------------+ | -SFDBKRTN | 154 | INP | INU | SEL.FEEDBACK RTN | +----------------+---------+---------+----------------+-----------------------+ | -SLVEACK | 039 | INP | IND | -SLAVE ACKNOWLEDGE | +----------------+---------+---------+----------------+-----------------------+ | -SLVEREQ | 048 | CIO | ENG | -SLAVE REQUEST | +----------------+---------+---------+----------------+-----------------------+ | TEST_A | 119 | INP | INU | TEST A CLOCK | +----------------+---------+---------+----------------+-----------------------+ | TEST_B | 108 | INP | INU | TEST B CLOCK | +----------------+---------+---------+----------------+-----------------------+ | TEST_C | 106 | INP | INU | TEST C CLOCK | +----------------+---------+---------+----------------+-----------------------+ | -TESTMODE | 002 | INP | IND | -TEST MODE | +----------------+---------+---------+----------------+-----------------------+ | TR 32 | 126 | CIO | ENR | TRANSLATE 32 | +----------------+---------+---------+----------------+-----------------------+ | VDD | 010 | PWR | VDD | +5 VOLTS | +----------------+---------+---------+----------------+-----------------------+ | VDD | 030 | PWR | VDD | +5 VOLTS | +----------------+---------+---------+----------------+-----------------------+ | VDD | 060 | PWR | VDD | +5 VOLTS | +----------------+---------+---------+----------------+-----------------------+ | VDD | 071 | PWR | VDD | +5 VOLTS | +----------------+---------+---------+----------------+-----------------------+ | VDD | 080 | PWR | VDD | +5 VOLTS | +----------------+---------+---------+----------------+-----------------------+ | VDD | 090 | PWR | VDD | +5 VOLTS | +----------------+---------+---------+----------------+-----------------------+ | VDD | 110 | PWR | VDD | +5 VOLTS | +----------------+---------+---------+----------------+-----------------------+ | VDD | 120 | PWR | VDD | +5 VOLTS | +----------------+---------+---------+----------------+-----------------------+ | VDD | 140 | PWR | VDD | +5 VOLTS | +----------------+---------+---------+----------------+-----------------------+ | VDD | 150 | PWR | VDD | +5 VOLTS | +----------------+---------+---------+----------------+-----------------------+ | VDD | 180 | PWR | VDD | +5 VOLTS | +----------------+---------+---------+----------------+-----------------------+ | VDD | 190 | PWR | VDD | +5 VOLTS | +----------------+---------+---------+----------------+-----------------------+ | VDD | 210 | PWR | VDD | +5 VOLTS | +----------------+---------+---------+----------------+-----------------------+ | VDD | 220 | PWR | VDD | +5 VOLTS | +----------------+---------+---------+----------------+-----------------------+ | VDD | 240 | PWR | VDD | +5 VOLTS | +----------------+---------+---------+----------------+-----------------------+ | VSS | 001 | PWR | VSS | +0 VOLTS | +----------------+---------+---------+----------------+-----------------------+ | VSS | 007 | PWR | VSS | +0 VOLTS | +----------------+---------+---------+----------------+-----------------------+ | VSS | 014 | PWR | VSS | +0 VOLTS | +----------------+---------+---------+----------------+-----------------------+ | VSS | 020 | PWR | VSS | +0 VOLTS | +----------------+---------+---------+----------------+-----------------------+ | VSS | 026 | PWR | VSS | +0 VOLTS | +----------------+---------+---------+----------------+-----------------------+ | VSS | 031 | PWR | VSS | +0 VOLTS | +----------------+---------+---------+----------------+-----------------------+ | VSS | 037 | PWR | VSS | +0 VOLTS | +----------------+---------+---------+----------------+-----------------------+ | VSS | 053 | PWR | VSS | +0 VOLTS | +----------------+---------+---------+----------------+-----------------------+ | VSS | 061 | PWR | VSS | +0 VOLTS | +----------------+---------+---------+----------------+-----------------------+ | VSS | 068 | PWR | VSS | +0 VOLTS | +----------------+---------+---------+----------------+-----------------------+ | VSS | 077 | PWR | VSS | +0 VOLTS | +----------------+---------+---------+----------------+-----------------------+ | VSS | 085 | PWR | VSS | +0 VOLTS | +----------------+---------+---------+----------------+-----------------------+ | VSS | 097 | PWR | VSS | +0 VOLTS | +----------------+---------+---------+----------------+-----------------------+ | VSS | 107 | PWR | VSS | +0 VOLTS | +----------------+---------+---------+----------------+-----------------------+ | VSS | 115 | PWR | VSS | +0 VOLTS | +----------------+---------+---------+----------------+-----------------------+ | VSS | 121 | PWR | VSS | +0 VOLTS | +----------------+---------+---------+----------------+-----------------------+ | VSS | 128 | PWR | VSS | +0 VOLTS | +----------------+---------+---------+----------------+-----------------------+ | VSS | 133 | PWR | VSS | +0 VOLTS | +----------------+---------+---------+----------------+-----------------------+ | VSS | 139 | PWR | VSS | +0 VOLTS | +----------------+---------+---------+----------------+-----------------------+ | VSS | 145 | PWR | VSS | +0 VOLTS | +----------------+---------+---------+----------------+-----------------------+ | VSS | 151 | PWR | VSS | +0 VOLTS | +----------------+---------+---------+----------------+-----------------------+ | VSS | 157 | PWR | VSS | +0 VOLTS | +----------------+---------+---------+----------------+-----------------------+ | VSS | 170 | PWR | VSS | +0 VOLTS | +----------------+---------+---------+----------------+-----------------------+ | VSS | 175 | PWR | VSS | +0 VOLTS | +----------------+---------+---------+----------------+-----------------------+ | VSS | 181 | PWR | VSS | +0 VOLTS | +----------------+---------+---------+----------------+-----------------------+ | VSS | 187 | PWR | VSS | +0 VOLTS | +----------------+---------+---------+----------------+-----------------------+ | VSS | 195 | PWR | VSS | +0 VOLTS | +----------------+---------+---------+----------------+-----------------------+ | VSS | 200 | PWR | VSS | +0 VOLTS | +----------------+---------+---------+----------------+-----------------------+ | VSS | 214 | PWR | VSS | +0 VOLTS | +----------------+---------+---------+----------------+-----------------------+ | VSS | 221 | PWR | VSS | +0 VOLTS | +----------------+---------+---------+----------------+-----------------------+ | VSS | 227 | PWR | VSS | +0 VOLTS | +----------------+---------+---------+----------------+-----------------------+ | VSS | 231 | PWR | VSS | +0 VOLTS | +----------------+---------+---------+----------------+-----------------------+ | VSS | 235 | PWR | VSS | +0 VOLTS | +----------------+---------+---------+----------------+-----------------------+ | -WDOG | 045 | INP | INU | -WATCHDOG | +----------------+---------+---------+----------------+-----------------------+
The following table gives the circuit definitions for all circuit types listed in the pinout tables.
+================+==========================================================+ | CIRCUIT TYPE | DESCRIPTIONS | +================+==========================================================+ | IND | Noninverting receiver w/pull down (17.5k - 55k) | +----------------+----------------------------------------------------------+ | INU | Noninverting receiver w/pull up (65k - 204k) | +----------------+----------------------------------------------------------+ | DNB | Noninverting, 5 mA, 3V tri-state driver | +----------------+----------------------------------------------------------+ | DNG | Noninverting, 8 mA, 3V tri-state driver | +----------------+----------------------------------------------------------+ | ENB | Noninverting, 5 mA, 3V tri-state driver and inverting | | | receiver w/pulldown (15.7k - 55k) | +----------------+----------------------------------------------------------+ | ENG | Noninverting, 8 mA, 3V tri-state driver and inverting | | | receiver w/pulldown (15.7k - 55k) | +----------------+----------------------------------------------------------+ | ENR | Noninverting, 24 mA, 3V tri-state driver and inverting | | | receiver w/pullup (65k - 204k) | +----------------+----------------------------------------------------------+ | ENT | Noninverting, 24 mA, 5V tri-state driver and inverting | | | receiver w/pullup (65k - 204k) | +----------------+----------------------------------------------------------+ | VDD | +5 Volts | +----------------+----------------------------------------------------------+ | VSS | +0 Volts (Driver Ground) | +----------------+----------------------------------------------------------+ | GND | +0 Volts (Internal Ground) | +----------------+----------------------------------------------------------+ | GNR | +0 Volts (Receiver Ground) | +----------------+----------------------------------------------------------+ | COMP | Compensation Resistor input (Pulled to +5V through 909 | | | ohms, 1% tol.) | +----------------+----------------------------------------------------------+
The total power dissipation for Miami varies with the Local Bus speed. Operating at 25 MHz and clocking the Local Bus continually at one wait state, the power dissipation is is estimated to be 800 mW. For zero wait state operation at 25 MHz, the power dissipation is estimated to be 1 W.
Electrical characteristics with a 909 Ohm compensation resistor are shown in Tables Table 20 and Table 21
The CFE driver/receiver pins are TTL compatible and have the following pin capacitances:
+==========+============+===========+===========+===========+============+=====+ |PARAMETER |TEST |DNB |DNG |INU |IND |UNITS| | |CONDITION +--+---+----+--+---+----+--+---+----+--+---+-----+ | | | |WC|NOM| BC |WC|NOM| BC |WC|NOM| BC |WC|NOM| BC | | +==========+============+===========+===========+===========+============+=====+ | VIH High | | | | 2 | 2 | V | | Level | | | | | | | | Input | | | | | | | | Voltage | | | | | | | +----------+------------+-----------+-----------+-----------+------------+-----+ | VIL Low | | | | 0.8 | 0.8 | V | | Level | | | | | | | | Input | | | | | | | | Voltage | | | | | | | +----------+------------+-----------+-----------+-----------+------------+-----+ | IOH High | VDD = 4.5V | 1.85| 4.00| | | mA | | Level | VOH = 2.4V | | | | | | | Output | | | | | | | | Current | | | | | | | +----------+------------+-----------+-----------+-----------+------------+-----+ | IOL Low | VDD = 4.5V | 4.50| 8.50| | | mA | | Level | VOL = 0.4V | | | | | | | Output | | | | | | | | Current | | | | | | | +----------+------------+-----------+-----------+-----------+------------+-----+ | IIL Low | VDD = 4.5V | | | 64.0| 45.00| uA | | Level | VIL = 0.4V | | | | | | | Input | | | | | | | | Current | | | | | | | +----------+------------+-----------+-----------+-----------+------------+-----+ | IIH High | VDD = 4.5V | | | 68.0| 198.0| uA | | Level | VIL = 2.0V | | | | | | | Input | | | | | | | | Current | | | | | | | +----------+------------+-----------+-----------+-----------+------------+-----+ | # of | GND bounce | 5.0 | 3.0 | | | | | Drivers | = 0.8V | | | | | | | per GND | | | | | | | | pin | | | | | | | +----------+------------+-----------+-----------+-----------+------------+-----+Table 21. Electrical characteristics with Compensation Resistor = 909 Ohms
+==========+============+===========+===========+===========+============+=====+ |PARAMETER |TEST |ENB |ENG |ENR |ENT |UNITS| | |CONDITION +--+---+----+--+---+----+--+---+----+--+---+-----+ | | | |WC|NOM| BC |WC|NOM| BC |WC|NOM| BC |WC|NOM| BC | | +==========+============+===========+===========+===========+============+=====+ | VIH High | | 2 | 2 | 2 | 2 | V | | Level | | | | | | | | Input | | | | | | | | Voltage | | | | | | | +----------+------------+-----------+-----------+-----------+------------+-----+ | VIL Low | | 0.8 | 0.8 | 0.8 | 0.8 | V | | Level | | | | | | | | Input | | | | | | | | Voltage | | | | | | | +----------+------------+-----------+-----------+-----------+------------+-----+ | IOH High | VDD = 4.5V | 1.85| 4.00| 0.60| 30.0 | mA | | Level | VOH = 2.4V | | | | | | | Output | | | | | | | | Current | | | | | | | +----------+------------+-----------+-----------+-----------+------------+-----+ | IOL Low | VDD = 4.5V | 4.50| 8.50| 27.0| 28.0 | mA | | Level | VOL = 0.4V | | | | | | | Output | | | | | | | | Current | | | | | | | +----------+------------+-----------+-----------+-----------+------------+-----+ | IIL Low | VDD = 4.5V | 64.0| 64.0| 64.0| 45.00| uA | | Level | VIL = 0.4V | | | | | | | Input | | | | | | | | Current | | | | | | | +----------+------------+-----------+-----------+-----------+------------+-----+ | IIH High | VDD = 4.5V | 68.0| 68.0| 68.0| 198.0| uA | | Level | VIL = 2.0V | | | | | | | Input | | | | | | | | Current | | | | | | | +----------+------------+-----------+-----------+-----------+------------+-----+ | # of | GND bounce | 5.0 | 3.0 | 3.0 | 0.5| | | Drivers | = 0.8V | | | | | | | per GND | | | | | | | | pin | | | | | | | +----------+------------+-----------+-----------+-----------+------------+-----+
VDD VSS VSS VDD VDD GNR VSS
| VSS | GND | VSS | VSS | VSS | VSS | VSS
| | | | | | | | | | | | | |
+--+---+---+---+---+---+---+---+---+---+---+---+---+---+--+
| 180.175.170.164.157.151.150.145.140.139.135.133.128.121 |
| . . |
VSS --+ 181 120 +-- VDD
| . . |
VSS --+ 187 110 +-- VDD
| . . |
VDD --+ 190 107 +-- VSS
| . . |
VSS --+ 195 101 +-- GND
| . . |
VSS --+ 200 97 +-- VSS
| . . |
GNR --+ 206 91 +-- GNR
VDD --+ 210 . |
GND --+ 211 90 +-- VDD
| . . |
VSS --+ 214 85 +-- VSS
| . . |
VDD --+ 220 80 +-- VDD
| . . |
VSS --+ 221 77 +-- VSS
| . . |
VSS --+ 227 72 +-- GND
| . . |
VSS --+ 231 71 +-- VDD
| . . |
VSS --+ 235 68 +-- VSS
| . . |
RES(COMP1)+ 239 62 +-- RES (COMP 2)
VDD --+ 240 . 61 +-- VSS
| *1..7...10..14..18..20..26..30..31..37..41..43..53..60 |
+--+---+---+---+---+---+---+---+---+---+---+---+---+---+--+
| | | | | | | | | | | | | |
| VSS | VSS | VSS | VDD | VSS | GND | VDD
VSS VDD GND VSS VSS GNR VSS
VDD = Power (+ 5 Volts)
VSS = Driver Ground
GNR = Receiver Ground
GND = Internal Ground
RES = Resistor Pin
Miami registers are listed in alphabetical order in Table 22
Table 22. Miami Registers - Alphabetical Order
+============+==========+=========+=======+=====+=============+=======+=====+ | Name | Section | Micro | Width | R/W | Local | Data | R/W | | | | Channel | | | Bus | Field | | | | | Address | | | Address | Size | | +============+==========+=========+=======+=====+=============+=======+=====+ | ATTN | 2.4.12 | 04 | 8 | R/W | 1FFA2004 | 8 | R | +------------+----------+---------+-------+-----+-------------+-------+-----+ | BCR1 | 2.4.17.3 | - | - | - | 1FFA3008 | 20 | R/W | +------------+----------+---------+-------+-----+-------------+-------+-----+ | BCR2 | 2.4.17.3 | - | - | - | 1FFA4008 | 20 | R/W | +------------+----------+---------+-------+-----+-------------+-------+-----+ | BMAR1 | 2.4.17.5 | - | - | - | 1FFA3010 | 16 | R/W | +------------+----------+---------+-------+-----+-------------+-------+-----+ | BMAR2 | 2.4.17.5 | - | - | - | 1FFA4010 | 16 | R/W | +------------+----------+---------+-------+-----+-------------+-------+-----+ | BMCDB1 | 2.4.17 | - | - | - | 1FFA3000-14 | 32 | R/W | +------------+----------+---------+-------+-----+-------------+-------+-----+ | BMCDB2 | 2.4.17 | - | - | - | 1FFA4000-14 | 32 | R/W | +------------+----------+---------+-------+-----+-------------+-------+-----+ | BMCMD1 | 2.4.19 | - | - | - | 1FFA301C | 2 | R/W | +------------+----------+---------+-------+-----+-------------+-------+-----+ | BMCMD2 | 2.4.19 | - | - | - | 1FFA401C | 2 | R/W | +------------+----------+---------+-------+-----+-------------+-------+-----+ | BMSTAT1 | 2.4.18 | - | - | - | 1FFA3018 | 10 | R | +------------+----------+---------+-------+-----+-------------+-------+-----+ | BMSTAT2 | 2.4.18 | - | - | - | 1FFA4018 | 10 | R | +------------+----------+---------+-------+-----+-------------+-------+-----+ | CAR1 | 2.4.17.1 | - | - | - | 1FFA3000 | 32 | R/W | +------------+----------+---------+-------+-----+-------------+-------+-----+ | CAR2 | 2.4.17.1 | - | - | - | 1FFA4000 | 32 | R/W | +------------+----------+---------+-------+-----+-------------+-------+-----+ | CBSP | 2.4.15 | 07 | 8 | R | 1FFA2010 | 8 | R/W | +------------+----------+---------+-------+-----+-------------+-------+-----+ | CCR1 | 2.4.17.4 | - | - | - | 1FFA300C | 11 | R/W | +------------+----------+---------+-------+-----+-------------+-------+-----+ | CCR2 | 2.4.17.4 | - | - | - | 1FFA400C | 11 | R/W | +------------+----------+---------+-------+-----+-------------+-------+-----+ | COMMAND | 2.4.11 | 00-03 | 32 | R/W | 1FFA2000 | 32 | R | +------------+----------+---------+-------+-----+-------------+-------+-----+ | CONF1 | 2.5.3 | 14-17 | 32 | R | - | - | - | +------------+----------+---------+-------+-----+-------------+-------+-----+ | CONF2 | 2.5.4 | 18-1B | 32 | R | - | - | - | +------------+----------+---------+-------+-----+-------------+-------+-----+ | CONF3 | 2.5.5 | 1C-1F | 32 | R | - | - | - | +------------+----------+---------+-------+-----+-------------+-------+-----+ | GAID | 2.4.3 | 0A | 8 | R | 1FFA0008 | 8 | R | +------------+----------+---------+-------+-----+-------------+-------+-----+ | HSBR | 2.5.1 | 0C-0F | 8 | R/W | - | - | - | +------------+----------+---------+-------+-----+-------------+-------+-----+ | ISP | 2.4.14 | 06 | 8 | R | 1FFA200C | 8 | R/W | +------------+----------+---------+-------+-----+-------------+-------+-----+ | LAP1 | 2.4.17.6 | - | - | - | 1FFA3014 | 32 | R/W | +------------+----------+---------+-------+-----+-------------+-------+-----+ | LAP2 | 2.4.17.6 | - | - | - | 1FFA4014 | 32 | R/W | +------------+----------+---------+-------+-----+-------------+-------+-----+ | LBBAR | 2.4.10 | - | - | - | 1FFA0024 | 12 | R/W | +------------+----------+---------+-------+-----+-------------+-------+-----+ | LBPE | 2.4.9 | - | - | - | 1FFA0020 | 3 | R | +------------+----------+---------+-------+-----+-------------+-------+-----+ | MDATA | 2.5.2 | 10-13 | 8 | R/W | - | - | - | +------------+----------+---------+-------+-----+-------------+-------+-----+ | NMI | 2.4.8 | 0B | 8 | R/W | 1FFA001C | 1 | R | +------------+----------+---------+-------+-----+-------------+-------+-----+ | POS_SETUP1 | 2.4.1 | - | - | - | 1FFA0000 | 32 | R | +------------+----------+---------+-------+-----+-------------+-------+-----+ | POS_SETUP2 | 2.4.2 | - | - | - | 1FFA0004 | 32 | R | +------------+----------+---------+-------+-----+-------------+-------+-----+ | PROC_CFG | 2.4.5 | - | - | - | 1FFA0010 | 14 | R/W | +------------+----------+---------+-------+-----+-------------+-------+-----+ | RSR | 2.4.6 | - | - | - | 1FFA0014 | 1 | R | +------------+----------+---------+-------+-----+-------------+-------+-----+ | SAR1 | 2.4.17.2 | - | - | - | 1FFA3004 | 32 | R/W | +------------+----------+---------+-------+-----+-------------+-------+-----+ | SAR2 | 2.4.17.2 | - | - | - | 1FFA4004 | 32 | R/W | +------------+----------+---------+-------+-----+-------------+-------+-----+ | SCP | 2.4.13 | 05 | 8 | R/W | 1FFA2008 | 8 | R | +------------+----------+----------+------+-----+-------------+-------+-----+ | SIR | 2.4.16 | - | - | - | 1FFA2014 | 16 | R/W | +------------+----------+---------+-------+-----+-------------+-------+-----+ | XPOS | 2.4.7 | - | - | - | 1FFA0018 | 16 | R/W | +------------+----------+---------+-------+-----+-------------+-------+-----+
The following sections provide the timing specifications for the Miami chip.
This section documents the CFE local bus timings. All local bus signal timings (outputs) are based on a capacitance of 55pf except -MSTRREQ and -SLVEREQ (20 pf). The MAX timings can be approximated for lower capacitanaces (down to 30pf) by subtracting 0.25ns per pf. (e.g. at 35pf subtract (55pf-35pf)*.25ns/pf = 5ns from max timing.) All timings are referenced to the rising edge of the PCLK.
Table 23. Miami CFE local bus timings, outputs
+==========+==============================================+======+======+======+ | Symbol | Description | Max | Min | Notes| | | | Tov | Toh | | | | | (ns) | (ns) | | +==========+==============================================+======+======+======+ | Tov, Toh | -L_ADS | 29 | 4 | | +----------+----------------------------------------------+------+------+------+ | Tov, Toh | L_AD, L_ADP (address) | 26 | 4 | | +----------+----------------------------------------------+------+------+------+ | Tov, Toh | -L_BLAST | 29 | 4 | | +----------+----------------------------------------------+------+------+------+ | Tov, Toh | -L_BE, L_W/-R | 29 | 4 | 1 | +----------+----------------------------------------------+------+------+------+ | Tov, Toh | L_AD, L_ADP (data) | 32 | 4 | | +----------+----------------------------------------------+------+------+------+ | Tov, Toh | -L_EXCPT | 29 | 4 | | +----------+----------------------------------------------+------+------+------+ | Tov, Toh | -L_READY | 29 | 4 | | +----------+----------------------------------------------+------+------+------+ | Tov, Toh | -L_GNT | 29 | 4 | | +----------+----------------------------------------------+------+------+------+ | Tov, Toh | -MSTRREQ, -SLVEREQ | 31 | 4 | 2 | +----------+----------------------------------------------+------+------+------+ | NOTE: | | | | 1. The CFE specification shows these signals valid only during the address | | state, however, Miami, as a master, holds these signals until the | | assertion of -L_BLAST. Designing to the CFE definition is recommended. | | 2. This timing does not meet the CFE specification. Designing to the Miami | | timing is recommended. | +------------------------------------------------------------------------------+Table 24. Miami CFE local bus timings, inputs
+==========+==============================================+======+======+======+ | Symbol | Description | Min | Min | Notes| | | | Tis | Tih | | | | | (ns) | (ns) | | +==========+==============================================+======+======+======+ | Tis, Tih | -L_ADS, -L_BLAST, -L_BE, L_W/-R, -L_READY, | 7 | 6 | 1 | | | -L_EXCPT, -MSTRACK, -SLVEACK | | | | +----------+----------------------------------------------+------+------+------+ | Tis, Tih | L_AD, L_ADP (address) | 10 | 6 | 1 | +----------+----------------------------------------------+------+------+------+ | Tis, Tih | L_AD, L_ADP (data) | 4 | 6 | 1 | +----------+----------------------------------------------+------+------+------+ | NOTE: | | | | 1. This timing does not meet the CFE specification. Designing to the Miami | | timing is recommended. | +------------------------------------------------------------------------------+Figure 7. Miami Input and Output Timing Reference
+----+ +--- / +----+
25MHz | | | \ | |
CLOCK + +----+ / ---+ +----
| \ |
++++---------- / ------+++++++
OUTPUTS ++++ | \ | +++++++
++++---------- / ------+++++++
>| |<-Tov \ >| |<-Toh
| / |
| \ |
++++---------- / ------+++++++
INPUTS ++++ | \ | +++++++
++++---------- / ------+++++++
>| |<-Tis >| |<-Tih
A write operation to Miami as a CFE slave is shown in Figure 8 Miami paces the master for one additional wait state during slave accesses. The basic slave transfer is, therefore, a two wait-state cycle consisting of an address state, two wait states, a data state, and a recovery state. Since the CFE Master must provide data immediately after the first wait state, Miami uses the second wait state to verify data parity and to latch data. Using the additional wait state to check parity allows Miami to assert the -L_EXCPT signal during the data state in the case of a data parity error. This early assertion simplifies the Miami design but is not required. By CFE definition, the L_EXCPT signal can be asserted during the Recovery state. Note that the L_EXCPT signal must be asserted for two clocks.
Figure 8. Miami Slave Write Timing
A W W D R
+----+ +----+ +----+ +----+ +----+ +----+
25MHz | | | | | | | | | | | |
CLOCK + +----+ +----+ +----+ +----+ +----+ +--
| | | | | |
---+ | +--------------------------------------------
-LADS | | | | | | | |
| +---------+ | | | |
| | | | | |
++++---------+++++++++++-------------------+++++++++++++++
L_AD ++++ | +++++++++++ | | +++++++++++++++
L_ADP ++++---------+++++++++++-------------------+++++++++++++++
| | | | | |
++++---------+++++++++++++++++++++++++++++++++++++++++++++
L_W/-R ++++ | +++++++++++++++++++++++++++++++++++++++++++++
++++ | +++++++++++++++++++++++++++++++++++++++++++++
| | | | | |
++++ | +++++++++++++++++++++++++++++++++++++++++++++
-L_BE ++++ | +++++++++++++++++++++++++++++++++++++++++++++
++++---------+++++++++++++++++++++++++++++++++++++++++++++
| | | | | |
---------------------------------+ | +--------------
-L_READY | | | | | | | |
| | | | +---------+ |
| | | | | |
-----------------------+ | | +--------------
-L_BLAST | | | | | | | |
| | | +-------------------+ |
| | | | | |
---------------------------------+ | | +----
-L_EXCPT | | | | | | | |
| | | | +-------------------+
A read operation to Miami as a CFE slave is shown in Figure 9 As in the slave write timing example, Miami paces the CFE master by an additional wait state. Read data is setup to the data state. Note that there are no conditions for asserting -L_EXCPT on a Slave Read from Miami
Figure 9. Miami Slave Read Timing
A W W D R
+----+ +----+ +----+ +----+ +----+ +----+
25MHz | | | | | | | | | | | |
CLOCK + +----+ +----+ +----+ +----+ +----+ +--
| | | | | |
---+ | +--------------------------------------------
-L_ADS | | | | | | | |
| +---------+ | | | |
| | | | | |
++++---------+++++++++++++++++++++---------+++++++++++++++
L_AD ++++ | +++++++++++++++++++++ | +++++++++++++++
L_ADP ++++---------+++++++++++++++++++++---------+++++++++++++++
| | | | | |
++++ | +++++++++++++++++++++++++++++++++++++++++++++
L_W/-R ++++ | +++++++++++++++++++++++++++++++++++++++++++++
-L_BE ++++---------+++++++++++++++++++++++++++++++++++++++++++++
| | | | | |
----------------------------------+ | +-------------
-L_READY | | | | | | | |
| | | | +--------+ |
| | | | | |
-----------------------+ | | +-------------
-L_BLAST | | | | | | | |
| | | +-------------------+ |
A Miami CFE Master operation is shown in Figure 10 The primary purpose of this example is to demonstrate the Miami bus operation after receiving an acknowledge, and the release of the CFE at the completion of a transfer. Miami requires four cycles after the receipt of acknowledge, before the assertion of -L_ADS. These four cycles are required to 1) Bring acknowledge on chip, 2) complete internal arbitration, and 3) access the correct address source and issue the address state. This four cycle overhead is present for both -MSTRACK_ and -SLVEACK_. The four cycle overhead is specific to the Miami implementation of the CFE Local Bus. By CFE definition, the arbitrating master MUST take a minimum of one state to assert -L_ADS after receiving acknowledge.
Miami completes the transfer by asserting -BLAST. By CFE definition, -BLAST is asserted during the state immediately preceeding the last data state, to identify this state as the last of the burst transfer. For a single transfer, -BLAST must be asserted immediately following the first wait state.
When relinquishing ownership of the CFE, Miami releases -MSTRREQ (-SLVEREQ) with -BLAST. Releasing request with -BLAST is specific to the Miami implementation, and is not required by the CFE architecture. The CFE architecture allows an arbitrating master to remove request at any time after -L_ADS when relinquishing the bus. After -L_ADS, ownership of the Local Bus is relinquished by a bus master when both 1) the request is released and 2) -BLAST and -L_READY are asserted. (-L_EXCPT is used in place of -BLAST and -L_READY during an exception condition). It is the responsibility of the CFE arbitration to detect the loss of request and the assertion of -BLAST and -L_READY (L_EXCPT) regardless of the order of the two conditions.
Figure 10. Single Transfer to Zero-Wait-State Slave
1 2 3 4 A W D R
+----+ +----+ +----+ +----+ +----+ +----+ +----+ +----+ +----+ +--
25MHz | | | | | | | | | | | | | | | | | | |
CLOCK + +----+ +----+ +----+ +----+ +----+ +----+ +----+ +----+ +----+
| | | | | | | | |
---+ | | | | | | | +-------------------
-MSTRREQ| | | | | | | | | | |
| +---------------------------------------------------------------------+ |
| | | | | | | | |
-------------+ | | | | | | | +---------
-MSTRACK| | | | | | | | | | |
| | ---------------------------------------------------------------------+
| | | | | | | | |
-----------------------------------------------------+ | +-----------------------------
-L_ADS | | | | | | | | | | |
| | | | | | +---------+ | |
| | | | | | | | |
-------------------------------------------------------------------------+ | +---------
-L_BLAST| | | | | | | | | | |
| | | | | | | | +---------+
| | | | | | | | |
-------------------------------------------------------------------------+ | +---------
-L_READY| | | | | | | | | | |
| | | | | | | | +---------+
A Miami CFE Master operation is shown in Figure 11 Miami asserts L_BEs and L_W/-R during the address state, and holds these signals until -BLAST is asserted, or until the final data state. Holding these signals beyond the address state is specific to the Miami implementation and is not required by the CFE architecture. A CFE slave should latch the L_BEs and L_W/-R during the address state, and not rely on their value in subsequent states.
A W D D D D R
+----
+----+ +----+ +----+ +----+ +----+ +----+ +----+ +----+ +--
25MHz | | | | | | | | | | | | | | | | | | |
CLOCK + ----+ +----+ +----+ +----+ +----+ +----+ +----+ +----+ +----+
| | | | | | | | | |
---+ | +-------------------------------------------------------------------------------
-L_ADS | | | | | | | | | | | |
| +---------+ | | | | | | | |
| | | | | | | | | |
++++---------+++++++++++---------+---------+---------+---------++++++++++++++++++++++++++++++
L_AD ++++ ADDR +++++++++++ DATA | DATA | DATA | DATA ++++++++++++++++++++++++++++++
++++---------+++++++++++---------+---------+---------+---------++++++++++++++++++++++++++++++
| | | | | | | | | |
++++ | | | | | ++++++++++++++++++++++++++++++++++++++++
-L_BE ++++ | | | | | ++++++++++++++++++++++++++++++++++++++++
++++-------------------------------------------------++++++++++++++++++++++++++++++++++++++++
| | | | | | | | | |
++++-------------------------------------------------++++++++++++++++++++++++++++++++++++++++
L_W/-R ++++ | | | | | ++++++++++++++++++++++++++++++++++++++++
++++ | | | | | ++++++++++++++++++++++++++++++++++++++++
| | | | | | | | | |
-----------------------------------------------------+ | +-----------------------------
-L_BLAST| | | | | | | | | | | |
| | | | | | +---------+ | | |
| | | | | | | | | |
-----------------------+ | | | | +-----------------------------
-L_READY| | | | | | | | | | | |
| | | +---------------------------------------+ | | |
Four-byte burst to zero-wait-state slave
Miami asserts only L_BEs for valid bytes during the address state. When Miami must change the byte enables, another address state must be issued to change their values. Therefore, if a large transfer starts on an odd byte boundary, the transfer is broken into a single transfer of an odd number of bytes followed by a new address state to change the byte enables for a word transfer. Likewise, if a large transfer ends in an odd number of bytes, a final single transfer cycle will occur with the byte enables for the odd number of bytes.
An example of this would be a tranfer of 16 bytes to the CFE starting at an address of xxxx xxx1. Miami would first perform a single transfer of three bytes with -L_BE3,2, and 1, asserted. This transfer would be followed by a new address state with all four byte enables asserted, creating a burst transfer of three cycles, or twelve bytes. Finally, a single transfer cycle with L_BE0 asserted would transfer the final byte.
The following chart lists the Micro Channel timings verified during Engineering Verification of the Miami chip. These timings are nominal timings, provided primarily to demonstrate Miami's ability to meet the Micro Channel specification. These timings do not represent absolute worst/best case timings. The Tx numbers reference the Micro Channel Architecture Technical Reference, listed in Section 1.4 , "Reference Documents"
Table 25. Micro Channel Timings
+========+========================================+======+======+=========+ | TMG | Description | MIN | MAX | ACTUAL | +========+========================================+======+======+=========+ | T1 | Status active from valid address | 10 | - | 16 | +--------+----------------------------------------+------+------+---------+ | T2 | -CMD active from status active | 55 | - | 76 | +--------+----------------------------------------+------+------+---------+ | T3 | -ADL active from valid address | 45 | - | 45 | +--------+----------------------------------------+------+------+---------+ | T4 | -ADL active to -CMD active | 40 | - | 48 | +--------+----------------------------------------+------+------+---------+ | T5 | -ADL active from status active | 12 | - | 24 | +--------+----------------------------------------+------+------+---------+ | T6 | -ADL pulse width | 40 | - | 46 | +--------+----------------------------------------+------+------+---------+ | T7 | Status hold from -ADL inactive | 25 | - | 48 | +--------+----------------------------------------+------+------+---------+ | T8 | Address valid hold from -ADL inactive | 25 | - | 96 | +--------+----------------------------------------+------+------+---------+ | T9 | Address valid hold from -CMD active | 30 | - | 92 | +--------+----------------------------------------+------+------+---------+ | T10 | Status hold from -CMD active | 30 | - | 48 | +--------+----------------------------------------+------+------+---------+ | T11 | SBHE setup to -ADL inactive | 40 | - | 118 | +--------+----------------------------------------+------+------+---------+ | T12 | -SBHE setup to -CMD active | 40 | - | 122 | +--------+----------------------------------------+------+------+---------+ | T13 | -CD DS 16/32 active from valid address | - | 55 | 23 | +--------+----------------------------------------+------+------+---------+ | T14 | -CD SFDBK active from valid address | - | 60 | 21 | +--------+----------------------------------------+------+------+---------+ | T15 | CMD active from Address valid | 85 | - | 92 | +--------+----------------------------------------+------+------+---------+ | T16 | -CMD pulse width | 90 | - | 94 | +--------+----------------------------------------+------+------+---------+ | T16A | -CMD pulse width | 190 | - | 196 | +--------+----------------------------------------+------+------+---------+ | T17 | Write data setup to -CMD active | 0 | - | >0 | +--------+----------------------------------------+------+------+---------+ | T18 | Write data hold from -CMD inactive | 30 | - | >31 | +--------+----------------------------------------+------+------+---------+ | T20 | Read data valid from -CMD active | 0 | 60 | 26 | +--------+----------------------------------------+------+------+---------+ | T22 | Data bus tri-state from -CMD inactive | - | 40 | 35 | +--------+----------------------------------------+------+------+---------+ | T22B | Read data tri-state from -CMD inactive | 7 | 40 | 35 | +--------+----------------------------------------+------+------+---------+ | T23 | -CMD active to next -CMD active | 190 | - | 198 | +--------+----------------------------------------+------+------+---------+ | T23A | -CMD inactive to next -CMD active | 80 | - | 104 | +--------+----------------------------------------+------+------+---------+ | T23B | -CMD inactive to next -ADL active | 40 | - | 52 | +--------+----------------------------------------+------+------+---------+ | T24 | Next status active from status inactive| 30 | - | 52 | +--------+----------------------------------------+------+------+---------+ | T27 | CD CHRDY inactive from status valid | 0 | 30 | 20 | +--------+----------------------------------------+------+------+---------+ | T29A | -CMD inactive from CHRDYRTN active | 60 | - | 76 | +--------+----------------------------------------+------+------+---------+ | T29M | Read data valid to master from CHRDYRTN| - | 60 | <60 | +--------+----------------------------------------+------+------+---------+ | T31 | -BE(0-3) valid to CMD active and to ADL| 40 | - | 100 | | | inactive | | | | +--------+----------------------------------------+------+------+---------+ | T33A | -BE(0-3) hold from -CMD inactive | 10 | - | 168 | +--------+----------------------------------------+------+------+---------+ | T35 | CD CHRDY active from CD CHRDY inactive | 0 | 3500 | (1) | +--------+----------------------------------------+------+------+---------+ | T42 | -PREEMPT inactive from ARB/-GNT in -GNT| 0 | 120 | 50 | | | state +70 dly | | | | +--------+----------------------------------------+------+------+---------+ | T42A | -PREEMPT inactive to status inactive | 20 | - | 286 | +--------+----------------------------------------+------+------+---------+ | T43 | -BURST active from ARB/-GNT in -GNT | - | 50 | 33 | | | state | | | | +--------+----------------------------------------+------+------+---------+ | T43B | -CMD active from ARB/-GNT in the -GNT | 115 | - | 160 | | | state | | | | +--------+----------------------------------------+------+------+---------+ | T43D | Status inactive from ARB/-GNT in the | 145 | - | 330 | | | -GNT state | | | | +--------+----------------------------------------+------+------+---------+ | T70 | -SDR(0,1) & -MSDR valid from -ADL | 0 | 40 | 24 | | | active (slave only) | | | | +--------+----------------------------------------+------+------+---------+ | T70A | -SDR(0,1) & -MSDR valid from -ADL | 0 | 115 | 18 | | | active (master only) | | | | +--------+----------------------------------------+------+------+---------+ | T71 | -SDR(0,1) & -MSDR inactive from last | 0 | 40 | 20 | | | -SD STROBE fall | | | | +--------+----------------------------------------+------+------+---------+ | T71A | -S0,-S1 inactive from -SD STROBE fall | - | 10 | -10 | | | (master term) | | | | +--------+----------------------------------------+------+------+---------+ | T71B | -SDR(0,1) & -MSDR inactive from -S0,S1 | 0 | 40 | 15 | | | inactive | | | | +--------+----------------------------------------+------+------+---------+ | T73 | -SD STROBE active to -CMD active | - | 10 | <10 | +--------+----------------------------------------+------+------+---------+ | T73A | -SD STROBE active from CHRDYRTN active | 0 | - | >0 | +--------+----------------------------------------+------+------+---------+ | T74 | -SD STROBE period (100 ns streaming) | 100 | - | 100 | +--------+----------------------------------------+------+------+---------+ | T74A | -CMD inactive from last -SD STROBE | 100 | - | 98 | | | fall (100 ns stream) | | | (2) | +--------+----------------------------------------+------+------+---------+ | T75 | -SD STROBE active (100 ns streaming) | 35 | - | 46 | +--------+----------------------------------------+------+------+---------+ | T75A | -SD STROBE inactive (100 ns streaming) | 35 | - | 50 | +--------+----------------------------------------+------+------+---------+ | T75B | -SD STROBE inactive to -CMD inactive | 35 | - | 50 | | | (100 ns streaming) | | | | +--------+----------------------------------------+------+------+---------+ | T76 | Send data valid from -SD STROBE fall | - | 75 | 38 | | | (100 ns streaming) | | | | +--------+----------------------------------------+------+------+---------+ | T77 | Send data hold from -SD STROBE fall | 10 | - | 18 | +--------+----------------------------------------+------+------+---------+ | T77A | Write data hold from -CMD inactive | 11 | - | >30 | | | (100 ns streaming) | | | | +--------+----------------------------------------+------+------+---------+ | T77B | Read data hold from -CMD inactive | 7 | - | >30 | +--------+----------------------------------------+------+------+---------+ | T78 | Receive data valid before -SD STROBE | 25 | - | 62 | | | fall (100 ns) | | | | +--------+----------------------------------------+------+------+---------+ | T78A | Receive data valid before -CMD inactive| 25 | - | 60 | | | (100 ns) | | | | +--------+----------------------------------------+------+------+---------+ | T79 | Status inactive from -CMD active | - | 7800 | <7800 | | | inactive | | | | +--------+----------------------------------------+------+------+---------+ | T83 | -BE(0-3) inactive from A(0:31) | 0 | - | -10 | | | tristated | | | (3) | +--------+----------------------------------------+------+------+---------+ | T83A | -BE(0-3) inactive from -SD STROBE | 20 | - | 26 | | | active | | | | +--------+----------------------------------------+------+------+---------+ | T84 | A(0-31) valid from -BE(0-3) inact. and | 0 | 60 | 30 | | | -SD STROBE active | | | | +--------+----------------------------------------+------+------+---------+ | T88 | - SD STROBE inactive from -BE(0-3) | 40 | - | 40 | | | inactive | | | | +--------+----------------------------------------+------+------+---------+ | T89 | Valid address hold from -SDR(1,0) | 0 | - | >0 | | | inactive | | | | +--------+----------------------------------------+------+------+---------+ | T90 | -DPAREN active from -CMD active for | 0 | 60 | 20 | | | default cycle | | | | +--------+----------------------------------------+------+------+---------+ | T91 | -DPAREN inactive from -CMD inactive | 0 | 40 | 50/27(4)| +--------+----------------------------------------+------+------+---------+ | T94 | -DPAREN active from -CMD active | - | 20 | 8 | +--------+----------------------------------------+------+------+---------+ | T96 | -CMD active from write data setup | 15 | - | 18 | +--------+----------------------------------------+------+------+---------+ | T97 | -DPAREN hold from -CMD inactive | 40 | - | 56 | +--------+----------------------------------------+------+------+---------+ | T102 | -CHCK active from CD CHRDY active | - | 50 | 10 | +--------+----------------------------------------+------+------+---------+ | T106 | -DPAREN inactive from -CMD inactive | 20 | - | 26 | +--------+----------------------------------------+------+------+---------+ | NOTE: | | | | (1) For Microchannel reads, the timing of CHRDY is determined by the | | time it takes the local bus to respond with enough data to release | | CHRDY. It is possible, when the CHRDY timer is disabled, that the | | local bus response is such that CHRDY is held longer than 3.5 usec.| | | | (2) Both CMD inactive and STROBE active are clocked by Miami at | | exactly 100ns. Because of the 2ns skew in the ALS245 transceiver | | for signals rising (CMD) and signals falling (STROBE), this timing | | is only 98ns. | | | | (3) Address and BE are released on the same clock internal to Miami. | | Because of system dependent loading, a skew of 10ns has been | | observed. | | | | (4) 27ns for Streaming, and 50ns for basic transfer cycles. | +-------------------------------------------------------------------------+
The -CMDRSTOUT signal is synchronous to the CFE bus clock. This signal is driven when a Micro Channel reset occurs, or under program control via the Command Reset bit in the SCP. Both the 40Mhz OSC. and the CFE bus clock must be active for the -CMDRSTOUT signal to function properly.
The -CMDRSTOUT signal can be used to reset any devices residing on the CFE Local Bus.
+-+ +-+ +-+ +-+ +-+ +-+ +-+ +-+ +-+
40Mhz CLK ------------------+ +-+ +-+ +{..}-+ +-+ +-+ +-+ +-+ +-+ +-
+---------------------------+
MC Reset --------------+ +---------------
+-+ +-+ +-+ +-+ +-+ +-+ +-+ +-+ +-+
CFE CLK ----------------------+ +-+ +-+ +-+ +-+ +-+ +{..}-+ +-+ +-+ +-
----------------------------------+ +---------
-CMDRSTOUT +--------------------+
** NOTE: The number of clocks that occur before the -CMDRSTOUT signal is
driven for a MC RESET may be different than shown.
The Miami chip has a special In-Circuit-Test (ICT) mode. This mode is activated by driving the ICT pin to 0 volts (this pin should be pulled up through a resistor to VCC for normal chip operation). The ICT mode implements an i/o mapping scheme that maps the chip inputs to the chip outputs. Bi-directional signals (signal pins which have transceivers internal to the chip) are treated as inputs when Miami is in ICT mode. The intent of the ICT test feature is to create a quick, simple method for verifying that the Miami chip has been properly soldered to the card with no shorts or opens at the pins. Only 170 input vectors are required to test the Miami chip. The input vector has 169 bits (one bit for each chip input pin). The input vector IV is assigned to the chip pins in the following order (IV(0)=msb):
Note to Miami chip designers - Internal signal names are provided to aid any changes to the ICT logic. Although all external bus signal names are given in vendor notation (Bit 0 = LSB), the Local Bus is given in IBM notation (Bit 0 = MSB) for all internal logics.
Table 26. Input Vector Pin Ordering
+=============+========================+========================+=============+ | INPUT | PIN NAME | INTERNAL SIGNAL NAME | PIN # | | VECTOR | | | | +=============+========================+========================+=============+ | IV(0) | A25 | MC_ADDR(25) | 124 | +-------------+------------------------+------------------------+-------------+ | IV(1) | A24 | MC_ADDR(24) | 125 | +-------------+------------------------+------------------------+-------------+ | IV(2) | TR 32 | MC_TR32 | 126 | +-------------+------------------------+------------------------+-------------+ | IV(3) | DPAR3 | MC_DATAP(3) | 127 | +-------------+------------------------+------------------------+-------------+ | IV(4) | D31 | MC_DATA(31) | 129 | +-------------+------------------------+------------------------+-------------+ | IV(5) | D30 | MC_DATA(30) | 130 | +-------------+------------------------+------------------------+-------------+ | IV(6) | D29 | MC_DATA(29) | 131 | +-------------+------------------------+------------------------+-------------+ | IV(7) | D28 | MC_DATA(28) | 132 | +-------------+------------------------+------------------------+-------------+ | IV(8) | 40MHZ OSC | OSC_40MHZ | 134 | +-------------+------------------------+------------------------+-------------+ | IV(9) | D27 | MC_DATA(27) | 136 | +-------------+------------------------+------------------------+-------------+ | IV(10) | D26 | MC_DATA(26) | 137 | +-------------+------------------------+------------------------+-------------+ | IV(11) | D25 | MC_DATA(25) | 138 | +-------------+------------------------+------------------------+-------------+ | IV(12) | D24 | MC_DATA(24) | 141 | +-------------+------------------------+------------------------+-------------+ | IV(13) | DPAR2 | MC_DATAP(2) | 142 | +-------------+------------------------+------------------------+-------------+ | IV(14) | D23 | MC_DATA(23) | 143 | +-------------+------------------------+------------------------+-------------+ | IV(15) | D22 | MC_DATA(22) | 144 | +-------------+------------------------+------------------------+-------------+ | IV(16) | D21 | MC_DATA(21) | 146 | +-------------+------------------------+------------------------+-------------+ | IV(17) | D20 | MC_DATA(20) | 147 | +-------------+------------------------+------------------------+-------------+ | IV(18) | D19 | MC_DATA(19) | 148 | +-------------+------------------------+------------------------+-------------+ | IV(19) | D18 | MC_DATA(18) | 149 | +-------------+------------------------+------------------------+-------------+ | IV(20) | D17 | MC_DATA(17) | 152 | +-------------+------------------------+------------------------+-------------+ | IV(21) | D16 | MC_DATA(16) | 153 | +-------------+------------------------+------------------------+-------------+ | IV(22) | -SFDBKRTN | MC_SFDBK_RTN | 154 | +-------------+------------------------+------------------------+-------------+ | IV(23) | -MSDR | MC_MSDR | 155 | +-------------+------------------------+------------------------+-------------+ | IV(24) | -SDR(1) | MC_SDR01(1) | 156 | +-------------+------------------------+------------------------+-------------+ | IV(25) | -SDR(0) | MC_SDR01(0) | 158 | +-------------+------------------------+------------------------+-------------+ | IV(26) | -REFRESH | MC_REFRESH | 159 | +-------------+------------------------+------------------------+-------------+ | IV(27) | -IRQ A | MC_IRQ(0) | 160 | +-------------+------------------------+------------------------+-------------+ | IV(28) | -S1 | MC_S1 | 161 | +-------------+------------------------+------------------------+-------------+ | IV(29) | -IRQ B | MC_IRQ(1) | 162 | +-------------+------------------------+------------------------+-------------+ | IV(30) | -CMD CLK | MC_CMD_CLK_ | 163 | +-------------+------------------------+------------------------+-------------+ | IV(31) | -SD STROBE | MC_SDSTRB | 165 | +-------------+------------------------+------------------------+-------------+ | IV(32) | -S0 | MC_S0 | 166 | +-------------+------------------------+------------------------+-------------+ | IV(33) | DPAR1 | MC_DATAP(1) | 167 | +-------------+------------------------+------------------------+-------------+ | IV(34) | -ADL | MC_ADL | 168 | +-------------+------------------------+------------------------+-------------+ | IV(35) | -SDSTRCLK | MC_STRB_CLK_ | 169 | +-------------+------------------------+------------------------+-------------+ | IV(36) | -CMD | MC_CMD | 171 | +-------------+------------------------+------------------------+-------------+ | IV(37) | -BE3 | MC_BE(3) | 172 | +-------------+------------------------+------------------------+-------------+ | IV(38) | -BE2 | MC_BE(2) | 173 | +-------------+------------------------+------------------------+-------------+ | IV(39) | -BE1 | MC_BE(1) | 174 | +-------------+------------------------+------------------------+-------------+ | IV(40) | -BE0 | MC_BE(0) | 176 | +-------------+------------------------+------------------------+-------------+ | IV(41) | -SBHE | MC_SBHE | 177 | +-------------+------------------------+------------------------+-------------+ | IV(42) | D15 | MC_DATA(15) | 178 | +-------------+------------------------+------------------------+-------------+ | IV(43) | D14 | MC_DATA(14) | 183 | +-------------+------------------------+------------------------+-------------+ | IV(44) | D13 | MC_DATA(13) | 184 | +-------------+------------------------+------------------------+-------------+ | IV(45) | D12 | MC_DATA(12) | 185 | +-------------+------------------------+------------------------+-------------+ | IV(46) | D11 | MC_DATA(11) | 186 | +-------------+------------------------+------------------------+-------------+ | IV(47) | D10 | MC_DATA(10) | 188 | +-------------+------------------------+------------------------+-------------+ | IV(48) | D9 | MC_DATA(9) | 189 | +-------------+------------------------+------------------------+-------------+ | IV(49) | D8 | MC_DATA(8) | 191 | +-------------+------------------------+------------------------+-------------+ | IV(50) | -DS 16 RTN | MC_DS16_RTN | 192 | +-------------+------------------------+------------------------+-------------+ | IV(51) | CHRESET | MC_RESET | 193 | +-------------+------------------------+------------------------+-------------+ | IV(52) | D7 | MC_DATA(7) | 194 | +-------------+------------------------+------------------------+-------------+ | IV(53) | D6 | MC_DATA(6) | 196 | +-------------+------------------------+------------------------+-------------+ | IV(54) | D5 | MC_DATA(5) | 197 | +-------------+------------------------+------------------------+-------------+ | IV(55) | D4 | MC_DATA(4) | 198 | +-------------+------------------------+------------------------+-------------+ | IV(56) | D3 | MC_DATA(3) | 199 | +-------------+------------------------+------------------------+-------------+ | IV(57) | D2 | MC_DATA(2) | 201 | +-------------+------------------------+------------------------+-------------+ | IV(58) | D1 | MC_DATA(1) | 202 | +-------------+------------------------+------------------------+-------------+ | IV(59) | D0 | MC_DATA(0) | 203 | +-------------+------------------------+------------------------+-------------+ | IV(60) | CHRDYRTN | MC_CHRDY_RTN | 204 | +-------------+------------------------+------------------------+-------------+ | IV(61) | M/-IO | MC_MIO | 205 | +-------------+------------------------+------------------------+-------------+ | IV(62) | -CHCK | MC_CHCK | 207 | +-------------+------------------------+------------------------+-------------+ | IV(63) | DPAR0 | MC_DATAP(0) | 208 | +-------------+------------------------+------------------------+-------------+ | IV(64) | -DPAREN | MC_DPAREN | 209 | +-------------+------------------------+------------------------+-------------+ | IV(65) | ARB3 | MC_ARB(3) | 212 | +-------------+------------------------+------------------------+-------------+ | IV(66) | -IRQ D | MC_IRQ(3) | 213 | +-------------+------------------------+------------------------+-------------+ | IV(67) | ARB2 | MC_ARB(2) | 215 | +-------------+------------------------+------------------------+-------------+ | IV(68) | ARB1 | MC_ARB(1) | 216 | +-------------+------------------------+------------------------+-------------+ | IV(69) | ARB0 | MC_ARB(0) | 217 | +-------------+------------------------+------------------------+-------------+ | IV(70) | -IRQ C | MC_IRQ(2) | 218 | +-------------+------------------------+------------------------+-------------+ | IV(71) | -BURST | MC_BURST | 219 | +-------------+------------------------+------------------------+-------------+ | IV(72) | -PREEMPT | MC_PREEMPT | 222 | +-------------+------------------------+------------------------+-------------+ | IV(73) | A12 | MC_ADDR(12) | 223 | +-------------+------------------------+------------------------+-------------+ | IV(74) | A13 | MC_ADDR(13) | 224 | +-------------+------------------------+------------------------+-------------+ | IV(75) | A14 | MC_ADDR(14) | 225 | +-------------+------------------------+------------------------+-------------+ | IV(76) | A0 | MC_ADDR(0) | 226 | +-------------+------------------------+------------------------+-------------+ | IV(77) | A1 | MC_ADDR(1) | 228 | +-------------+------------------------+------------------------+-------------+ | IV(78) | A2 | MC_ADDR(2) | 229 | +-------------+------------------------+------------------------+-------------+ | IV(79) | A15 | MC_ADDR(15) | 230 | +-------------+------------------------+------------------------+-------------+ | IV(80) | APAR1 | MC_APAR(1) | 232 | +-------------+------------------------+------------------------+-------------+ | IV(81) | A16 | MC_ADDR(16) | 233 | +-------------+------------------------+------------------------+-------------+ | IV(82) | A17 | MC_ADDR(17) | 234 | +-------------+------------------------+------------------------+-------------+ | IV(83) | A3 | MC_ADDR(3) | 237 | +-------------+------------------------+------------------------+-------------+ | IV(84) | A4 | MC_ADDR(4) | 238 | +-------------+------------------------+------------------------+-------------+ | IV(85) | -TESTMODE | TEST_RAM_EN | 002 | +-------------+------------------------+------------------------+-------------+ | IV(86) | A5 | MC_ADDR(5) | 003 | +-------------+------------------------+------------------------+-------------+ | IV(87) | A18 | MC_ADDR(18) | 004 | +-------------+------------------------+------------------------+-------------+ | IV(88) | A19 | MC_ADDR(19) | 006 | +-------------+------------------------+------------------------+-------------+ | IV(89) | A6 | MC_ADDR(6) | 008 | +-------------+------------------------+------------------------+-------------+ | IV(90) | A20 | MC_ADDR(20) | 011 | +-------------+------------------------+------------------------+-------------+ | IV(91) | A7 | MC_ADDR(7) | 012 | +-------------+------------------------+------------------------+-------------+ | IV(92) | ARB/-GNT | MC_ARB_GNT | 013 | +-------------+------------------------+------------------------+-------------+ | IV(93) | APAR0 | MC_APAR(0) | 015 | +-------------+------------------------+------------------------+-------------+ | IV(94) | A8 | MC_ADDR(8) | 016 | +-------------+------------------------+------------------------+-------------+ | IV(95) | -DS 32 RTN | MC_DS32_RTN | 017 | +-------------+------------------------+------------------------+-------------+ | IV(96) | A21 | MC_ADDR(21) | 019 | +-------------+------------------------+------------------------+-------------+ | IV(97) | A22 | MC_ADDR(22) | 022 | +-------------+------------------------+------------------------+-------------+ | IV(98) | A9 | MC_ADDR(9) | 023 | +-------------+------------------------+------------------------+-------------+ | IV(99) | A23 | MC_ADDR(23) | 024 | +-------------+------------------------+------------------------+-------------+ | IV(100) | -16/32 DETECT | MC_CD_SIZE_16 | 025 | +-------------+------------------------+------------------------+-------------+ | IV(101) | APAR2 | MC_APAR(2) | 027 | +-------------+------------------------+------------------------+-------------+ | IV(102) | A10 | MC_ADDR(10) | 028 | +-------------+------------------------+------------------------+-------------+ | IV(103) | -MSTRACK | LMSTRACK_ | 029 | +-------------+------------------------+------------------------+-------------+ | IV(104) | A11 | MC_ADDR(11) | 032 | +-------------+------------------------+------------------------+-------------+ | IV(105) | MADE 24 | MC_MADE24 | 033 | +-------------+------------------------+------------------------+-------------+ | IV(106) | -CD SETUP | MC_CD_SETUP | 035 | +-------------+------------------------+------------------------+-------------+ | IV(107) | L_ADS | LADS_ | 040 | +-------------+------------------------+------------------------+-------------+ | IV(108) | 25MHZ OSC | LOSC | 042 | +-------------+------------------------+------------------------+-------------+ | IV(109) | -SLVEACK | LSLVEACK_ | 039 | +-------------+------------------------+------------------------+-------------+ | IV(110) | -WDOG | WDOG_ | 045 | +-------------+------------------------+------------------------+-------------+ | IV(111) | -L_EXCPT | LEXCPT_ | 047 | +-------------+------------------------+------------------------+-------------+ | IV(112) | -SLVEREQ | LSLVEREQ_ | 048 | +-------------+------------------------+------------------------+-------------+ | IV(113) | -L_BLAST | LBLAST_ | 049 | +-------------+------------------------+------------------------+-------------+ | IV(114) | -MSTRREQ | LMSTRREQ_ | 050 | +-------------+------------------------+------------------------+-------------+ | IV(115) | -L_W/-R | LW_R_ | 051 | +-------------+------------------------+------------------------+-------------+ | IV(116) | -W_READY | LREADY_ | 052 | +-------------+------------------------+------------------------+-------------+ | IV(117) | L_AD31 | L_AD0 | 054 | +-------------+------------------------+------------------------+-------------+ | IV(118) | L_AD30 | L_AD1 | 055 | +-------------+------------------------+------------------------+-------------+ | IV(119) | L_AD29 | L_AD2 | 056 | +-------------+------------------------+------------------------+-------------+ | IV(120) | L_AD28 | L_AD3 | 057 | +-------------+------------------------+------------------------+-------------+ | IV(121) | L_AD27 | L_AD4 | 058 | +-------------+------------------------+------------------------+-------------+ | IV(122) | L_AD26 | L_AD5 | 059 | +-------------+------------------------+------------------------+-------------+ | IV(123) | L_AD25 | L_AD6 | 063 | +-------------+------------------------+------------------------+-------------+ | IV(124) | L_AD24 | L_AD7 | 064 | +-------------+------------------------+------------------------+-------------+ | IV(125) | L_AD23 | L_AD8 | 065 | +-------------+------------------------+------------------------+-------------+ | IV(126) | L_AD22 | L_AD9 | 066 | +-------------+------------------------+------------------------+-------------+ | IV(127) | L_AD21 | L_AD10 | 067 | +-------------+------------------------+------------------------+-------------+ | IV(128) | L_AD20 | L_AD11 | 069 | +-------------+------------------------+------------------------+-------------+ | IV(129) | L_AD19 | L_AD12 | 070 | +-------------+------------------------+------------------------+-------------+ | IV(130) | L_AD18 | L_AD13 | 073 | +-------------+------------------------+------------------------+-------------+ | IV(131) | L_AD17 | L_AD14 | 074 | +-------------+------------------------+------------------------+-------------+ | IV(132) | L_AD16 | L_AD15 | 075 | +-------------+------------------------+------------------------+-------------+ | IV(133) | L_AD15 | L_AD16 | 076 | +-------------+------------------------+------------------------+-------------+ | IV(134) | L_AD14 | L_AD17 | 078 | +-------------+------------------------+------------------------+-------------+ | IV(135) | L_AD13 | L_AD18 | 079 | +-------------+------------------------+------------------------+-------------+ | IV(136) | L_AD12 | L_AD19 | 081 | +-------------+------------------------+------------------------+-------------+ | IV(137) | L_AD11 | L_AD20 | 082 | +-------------+------------------------+------------------------+-------------+ | IV(138) | L_AD10 | L_AD21 | 083 | +-------------+------------------------+------------------------+-------------+ | IV(139) | L_AD9 | L_AD22 | 084 | +-------------+------------------------+------------------------+-------------+ | IV(140) | L_AD8 | L_AD23 | 086 | +-------------+------------------------+------------------------+-------------+ | IV(141) | L_AD7 | L_AD24 | 087 | +-------------+------------------------+------------------------+-------------+ | IV(142) | L_AD6 | L_AD25 | 088 | +-------------+------------------------+------------------------+-------------+ | IV(143) | L_AD5 | L_AD26 | 089 | +-------------+------------------------+------------------------+-------------+ | IV(144) | L_AD4 | L_AD27 | 092 | +-------------+------------------------+------------------------+-------------+ | IV(145) | L_AD3 | L_AD28 | 093 | +-------------+------------------------+------------------------+-------------+ | IV(146) | L_AD2 | L_AD29 | 094 | +-------------+------------------------+------------------------+-------------+ | IV(147) | L_AD1 | L_AD30 | 095 | +-------------+------------------------+------------------------+-------------+ | IV(148) | L_AD0 | L_AD31 | 096 | +-------------+------------------------+------------------------+-------------+ | IV(149) | LBPAR0 | LADP0 | 098 | +-------------+------------------------+------------------------+-------------+ | IV(150) | LBPAR1 | LADP1 | 099 | +-------------+------------------------+------------------------+-------------+ | IV(151) | LBPAR2 | LADP2 | 100 | +-------------+------------------------+------------------------+-------------+ | IV(152) | LBPAR3 | LADP3 | 102 | +-------------+------------------------+------------------------+-------------+ | IV(153) | -L_BE0 | LBE0_ | 103 | +-------------+------------------------+------------------------+-------------+ | IV(154) | -L_BE1 | LBE1_ | 104 | +-------------+------------------------+------------------------+-------------+ | IV(155) | -L_BE2 | LBE2_ | 105 | +-------------+------------------------+------------------------+-------------+ | IV(156) | -L_BE3 | LBE3_ | 109 | +-------------+------------------------+------------------------+-------------+ | IV(157) | APAR3 | MC_APAR(3) | 111 | +-------------+------------------------+------------------------+-------------+ | IV(158) | -APAREN | MC_APAREN | 112 | +-------------+------------------------+------------------------+-------------+ | IV(159) | A31 | MC_ADDR(31) | 113 | +-------------+------------------------+------------------------+-------------+ | IV(160) | A30 | MC_ADDR(30) | 114 | +-------------+------------------------+------------------------+-------------+ | IV(161) | A29 | MC_ADDR(29) | 116 | +-------------+------------------------+------------------------+-------------+ | IV(162) | A28 | MC_ADDR(28) | 117 | +-------------+------------------------+------------------------+-------------+ | IV(163) | A27 | MC_ADDR(27) | 118 | +-------------+------------------------+------------------------+-------------+ | IV(164) | A26 | MC_ADDR(26) | 123 | +-------------+------------------------+------------------------+-------------+ | IV(165) | +RAMTSTCLK | TEST_RAM_CLOCK | 122 | +-------------+------------------------+------------------------+-------------+ | IV(166) | TEST_A | TEST_A | 119 | +-------------+------------------------+------------------------+-------------+ | IV(167) | TEST_B | TEST_B | 108 | +-------------+------------------------+------------------------+-------------+ | IV(168) | TEST_C | TEST_C | 106 | +-------------+------------------------+------------------------+-------------+The output vector is detected on the following output pins:
Table 27. Output Vector Pin Ordering
+=============+========================+========================+=============+ | OUTPUT | PIN NAME | INTERNAL SIGNAL NAME | Pin # | | VECTOR | | | | +=============+========================+========================+=============+ | OV(0) | +BMSTREN | BMSTREN | 182 | +-------------+------------------------+------------------------+-------------+ | OV(1) | -CDSFDBK | MC_CD_SFDBK | 009 | +-------------+------------------------+------------------------+-------------+ | OV(2) | -CD DS 32 | MC_CD_DS32 | 021 | +-------------+------------------------+------------------------+-------------+ | OV(3) | -CD DS 16 | MC_CD_DS16 | 236 | +-------------+------------------------+------------------------+-------------+ | OV(4) | INT(0) | LINT(0) | 044 | +-------------+------------------------+------------------------+-------------+ | OV(5) | INT(1) | LINT(1) | 038 | +-------------+------------------------+------------------------+-------------+ | OV(6) | INT(2) | LINT(2) | 036 | +-------------+------------------------+------------------------+-------------+ | OV(7) | INT(3) | LINT(3) | 034 | +-------------+------------------------+------------------------+-------------+ | OV(8) | CMDRSTOUT | LRESET_ | 046 | +-------------+------------------------+------------------------+-------------+When an input vector is applied to the chip's input pins, all pins associated with the output value switch to either a '0' or a '1'. The input vector is generated by shifting 1's to the right starting with the most significant bit IV(0). Changing the input vector one bit at a time allows isolation down to single pin resolution. All Miami pins are tested except for MC_CHRDY signal pin. The Input Vector versus Output Vector values are shown below.
Figure 13. Test Input Vectors and Associated Output Vectors
START:
IV(0.168) = 00000000 00000000 00000000 00000000 00000000 00h || 0b
OV(0.8) = 000000000b
IV(0.168) = 80000000 00000000 00000000 00000000 00000000 00h || 0b
OV(0.8) = 111111111b
IV(0.168) = C0000000 00000000 00000000 00000000 00000000 00h || 0b
OV(0.8) = 000000000b
IV(0.168) = E0000000 00000000 00000000 00000000 00000000 00h || 0b
OV(0.8) = 111111111b
IV(0.168) = F0000000 00000000 00000000 00000000 00000000 00h || 0b
OV(0.8) = 000000000b
IV(0.168) = F8000000 00000000 00000000 00000000 00000000 00h || 0b
OV(0.8) = 111111111b
.
.
.
IV(0.168) = FFFFFFFF FFFFFFFF FFFFFFFF FFFFFFFF FFFFFFFF F8h || 0b
OV(0.8) = 111111111b
IV(0.168) = FFFFFFFF FFFFFFFF FFFFFFFF FFFFFFFF FFFFFFFF FCh || 0b
OV(0.8) = 000000000b
IV(0.168) = FFFFFFFF FFFFFFFF FFFFFFFF FFFFFFFF FFFFFFFF FEh || 0b
OV(0.8) = 111111111b
IV(0.168) = FFFFFFFF FFFFFFFF FFFFFFFF FFFFFFFF FFFFFFFF FFh || 0b
OV(0.8) = 000000000b
IV(0.168) = FFFFFFFF FFFFFFFF FFFFFFFF FFFFFFFF FFFFFFFF FFh || 1b
OV(0.8) = 111111111b
END:
There are five scan chains defined for Miami, as listed in Table 28 On the chip tester, these five chains are used to scan the patterns through the chip.
Table 28. LSSD Scan Chains in Miami
+============+===============+======================+ | SCAN IN | SCAN OUT PIN# | # OF LATCHES IN | | PIN# | | CHAIN | +============+===============+======================+ | 045 | 005 | 762 | +------------+---------------+----------------------+ | 013 | 021 | 648 | +------------+---------------+----------------------+ | 025 | 236 | 635 | +------------+---------------+----------------------+ | 017 | 009 | 649 | +------------+---------------+----------------------+ | 159 | 046 | 448 | +------------+---------------+----------------------+
The A_CLOCK is on pin 119. A_CLOCK will be OFF when this pin is HIGH.
The B_CLOCK is on pin 108. B_CLOCK will be OFF when this pin is LOW.
For B_CLOCK to be ON:
The C_CLOCK is on pin 106. C_CLOCK will be OFF when this pin is LOW.
For C_CLOCK to be ON:
The Static IDD mode is used for chip manufacturing test only. This mode disables the power to all off-chip drivers and receivers, allowing current measurements for logic only. This mode is invoked by asserting the -TEST MODE pin low and applying an encoded value to the -MSTRACK and -SLVEACK inputs. This mode is not used for on-card testing.
To place the chip in Static IDD Test Mode:
The Tri-Stating Drivers mode is used on the chip tester to disable all the off-chip drivers, including the Common I/O. This mode is invoked by asserting the -TEST MODE pin low and applying an encoded value to the -MSTRACK and -SLVEACK inputs. This mode is not used for on-card testing.
To tri-state all drivers (including CIO):
The following appendix provides the major additions to Miami's function in Pass 2, as well as the errata for Miami Passes 1 and 2. The additions to Miami's function are program and pin compatible to Miami Pass 1.
The following is a brief description of the functional changes from Miami Pass 1 to Miami Pass 2.
Reference: No reference
These bits were Reserved for Miami Pass 1, reading back as zero. Their new functions are active high for Pass 1 compatibility.
Reference: DCR 42
NOTE: Masters must record the state of -SFDBKRTN when a channel check is detected regardless of the state of the Select Feedback Return Exception Enable field.
-(Micro Channel TRM, Sep 1991 pg.129)
Miami Pass 2 updates BMSTAT1(2) Bit 3 (-SFDBKRTN) in addition to Bit 2 (IOCHCK) when a channel check is detected as a bus master. This operation is independent of the state of POS 3 Bit 6, in conformance with the architecture.
Reference: DCR 43
A write of zero to this bit in Miami Pass 2 will have no effect, so programs written to Miami Pass 1 are code compatible with Miami Pass 2.
Reference: DCR 44
Reference: DCR 45
Problem Area - Systems or Bus Masters that do not support parity can force a parity error on Miami if they change data while -CMD is active on the Micro Channel.
Configuration - Non-Parity master accessing Miami as a Micro Channel slave with parity enabled in Miami POS registers.
Description - Miami can assert an asynchronous -CHCK when data parity errors occur while -CMD is active. The Micro Channel spec states that data parity is valid before -CMD is active, and is held valid until -CMD is inactive. Some systems, however, disable data transceivers on inactive bytes (e.g. upper bytes of low word transfer), while -CMD is ACTIVE. Both Miami Pass 1 AND 2 assert asynchronous -CHCK for this condition.
Work Around -
Reference - PTR 65
Problem Area - Non sequential addressing of Miami (when -BURST is active) for a Microchannel slave read causes invalid local bus prefetching and eventually a bad word of data during the next read access to Miami.
Configuration - A bursting Microchannel master reading Miami as a memory or I/O slave.
Description - When a bursting Microchannel master (-BURST active for 2 or more Microchannel cycles) reads Miami via the shared memory window or the MDATA port, and then on the subsequent cycle accesses (read or write) at an address that is non-sequential from the previous read (ie. a sequential access would be address1=xxx04, address2=xxx08), the subsequent cycle causes prefetching to occur on the local bus and continue until the current master on the Microchannel issues and end of transfer (EOT). If the current master were to come back to Miami, prior to issuing the EOT, for another read while the continuous prefetching is occurring, a bad word of data may be passed onto the Microchannel.
Work Around -
ALS241
-------
-BURST from ------+------------| < < |------- +5 volts
Miami | ---o---
| +-----+
| | ALS241
| | -------
+------------| > > |------------ -BURST on
| ------- Microchannel
| |
+BMSTREN from --------------+-----+
Miami
Reference - PTR 42
Problem Area - Stopping the DMA channels by writing the CCR or BMCMD register may cause subsequent list chaining operations to be corrupted. The corrupted list chain operation causes the DMA control registers (CDB registers) to be loaded with incorrect values.
This same problem can occur if an L_Exception occurs during a list chain operation.
Configuration - Local Bus masters writing directly to Miami's CCR start/stop bit or the start/stop bit through the BMCMD register can cause list chaining errors.
Description - If a local bust master writes the start/stop bit of a DMA channel when the Miami LMSTRREQ_ (local bus request signal) is pending but hasn't been acknowledged yet, and the request is for one of Miami's DMA channels to perform a list chaining operation (load the CDB regs), the list chain operation will be initiated on the local bus and terminate prior to loading all 6 CDB registers. This pre-mature termination of the list chaining operation causes the list chain state machine to get out of synchronization with the internal list chain CDB register pointer. When the DMA channel is restarted, the subsequent list chain operation will load the CDB registers in the wrong order. The CDB registers will be loaded starting with the register following the last one loaded during the list chain operation that prematurely terminated.
The problem is further worsened by the fact that both DMA channels share the same list chaining state machine. When one channels list chaining operation is prematurely terminated, both DMA channels will be out of sync. during all subsequent list chain operations.
Work Around -
Reference - PTR 71
Problem Area - A local bus read data parity error occurs when a local bus master reads from the Miami 1ffa xxxxh address region and no valid register exists at the specific address location.
Configuration - A local bus master reading the local bus region 1ffa0000h - 1ffaffffh where no specific Miami register is located.
Description - Miami returns local bus Ready (LREADY_) for all local bus accesses in the 1ffa address region. For locations where no Miami register exists, the entire data path internal to Miami (including the parity bits) are forced to zero. Forcing both data and parity to zero causes Miami to drive invalid data parity for these accesses.
Work Around -
Reference - PTR 74
Problem Area - When a bursting Microchannel master writes to Miami in the shared memory regions, 1-3 bytes of data in a word can be corrupted when the data is written out on to the local bus.
Configuration - A bursting (-BURST active) Microchannel master performing basic transfer writes to Miami as a slave on the Microchannel.
Description - While -BURST is active, if the Micro Channel master accesses Miami as a slave with non-sequential writes, 1-3 data bytes in a word transferred on the local bus get corrupted. This problem occurs when the master writes less than a full word (1-3 bytes) to Miami at one address followed by a write to Miami of a full word (or a different byte enable combination than the previous write) to a non-sequential address (from the previous write). The corruption of data occurs on the second write to Miami. This kind of action occurs when the Micro Channel master is a Miami with both DMA channels active (using the same ARB level) such that both channels can write to the Miami slave under the same Micro Channel bus ownership period. This kind of scenario may also occur in systems that drive -BURST as a master.
Work Around -
ALS241
-------
-BURST from ------+------------| < < |------- +5 volts
Miami | ---o---
| +-----+
| | ALS241
| | -------
+------------| > > |------------ -BURST on
| ------- Microchannel
| |
+BMSTREN from --------------+-----+
Miami
Reference - PTR 91
Problem Area - Microchannel masters reading Miami as an I/O slave through the HSBR/MDATA port mechanism will not see a Channel Check when an exception occurs on the local bus when the read is accessing the non-burst region on the local bus (0h to 1FFFFFFFh).
Configuration - Microchannel masters reading non-burst local bus address space through Miami's MDATA port.
Description - When reading local bus address space in the non-burst region (addresses from 0-1FFFFFFF) through the MDATA port, local bus exceptions and read data parity errors are not reported as a Channel Check on the Micro Channel. Miami holds CHRDY inactive for the 3.4usec timeout period, and then releases ready and passes invalid data onto the Microchannel Bus.
Work Around -
Reference - PTR 110
Problem Area - 64-bit streaming DMA write transfers to the Microchannel larger than 256 bytes that start with either an unaligned (not 4 byte aligned) card address or an unaligned (not 4 byte aligned) system address may encounter the writing of 2 incorrect words during the write transfer.
Configuration - When streaming and 64-bit streaming are enabled, and the Miami DMA is performing a Microchannel write with the starting card address and starting system address not 4-byte aligned.
Description - The problem is only limited to certain alignment and byte count combinations for writes to the Micro Channel of over 256 bytes AND using 64-bit streaming data.
For these conditions the final, internal data buffer (which is partially filled to complete the transfer) has its first to locations corrupted. This channel is rolling over from the completing the filling of the previous buffer BEFORE the internal buffer used for the final data is available from the Micro Channel.
Work Around -
Reference - PTR 83
Problem Area - When running both Miami DMA channels with one channel using the primary bus master arbitration level (ARB lev 1) and the other channel using the secondary ARB level (ARB lev 2), and having the secondary ARB level enabled in POS, severe Microchannel errors occur. These errors are reported as channel check, and/or no SFBKRTN detected in the bus master status register (BMSTAT).
When the performance timer (bit 13 of the PROC_CFG) is disabled (bit=1), the problem does not occur.
Configuration - When running both Miami DMA channels with one channel using the primary bus master arbitration level (ARB lev 1) and the other channel using the secondary ARB level (ARB lev 2), and having the secondary ARB level enabled in POS.
Description - Miami Pass 2 provides a performance timer that extends ownership of the Micro Channel for 500 ns after a Bus Master channel has completed transferring all its available data. This extension is useful in cases where the terminating channel barely misses the time window when another of its internal data buffers becomes available, i.e. a buffer completes flushing on the Local Bus for a Micro Channel read operation, or filling on the Local Bus for writing the Micro Channel.
The performance timer holds -BURST active and waits for another internal request from EITHER channel. If both channels are programmed to the same ARB level, either internal request is properly serviced. Neither channel will try to cause the assertion of preempt on the Micro Channel, but will resume data operation while continuing to assert -BURST. If the channels are programmed to opposite ARB levels, however, a request from the opposite channel from the terminating channel is intended to force the assertion of preempt on the Micro Channel. This preemption logic is not properly qualified with the performance timer, such that -PREEMPT is asserted with -BURST active, rather than just resuming data operation.
Work Around - This problem is fixed limiting the enabling of the second ARB level and the performance timer. These two functions cannot be enabled together.
Reference - PTR 96
Problem Area - Reading the CBSP from the Micro Channel (system unit) at the same time the IV bit is written from the CFE bus may result in the loss of status of the interrupt.
Configuration - Reading the CBSP from the Micro Channel at the same time the CBSP is written to from the CFE bus. When Micro Channel interrupts are shared, it is common for the device driver to read the CBSP register of all Miami chips to determine which of the Miami chips actually has a pending interrupt. For device drivers that operate in this manner, it is likely that the CBSP register will be read even when Miami does not have an interrupt pending to the system.
Description - A race condition exists between a read of the CBSP from the Micro Channel which clears the interrupt and the IV bit, and the setting of the IV bit during a CBSP write from the CFE bus. This race condition may result in the Micro Channel reading the IV bit as '0' and clearing the interrupt in Miami. When this occurs, the interrupt is lost.
Work Around -
Reference - PTR 262
Problem Area - Data corruption can occur when an XIO based RS6000 system is writing to the Miami chip, and data streaming is enabled.
Description - Miami may defer the start of a streaming write transfer as a Micro Channel slave by pulling the CD CHRDY signal 'low' (inactive) at the beginning of a write cycle. Miami pulls CD CHRDY low initially on slave writes when there are no free buffer locations within the chip for the write data. As soon as space is available for the write data, Miami drives CD CHRDY 'high' (active) indicating that Miami is now ready to accept the write data. Although Miami's use of the the CD CHRDY signal is valid, XIO based RS6000 systems have specific requirements regarding the release of CD CHRDY on the Micro Channel.
On XIO systems, the XIO samples this asynchronous event with two discrete flip-flops just prior to the falling edge of CMD. If Miami happens to drive CD CHRDY active near the falling edge of CMD, it is possible for these two flip-flops to latch different values for the state of CD CHRDYRTN causing part of the XIO to begin a streaming write transfer while part of the XIO continues to defer the streaming transfer start. If these two flip-flops latch different values, the incorrect number of streaming data strobes occurs and thereby corrupts the write data.
Work Around - The following fix holds Miami's CD CHRDY signal inactive beyond the falling edge of CMD, and thereby avoiding the improper sampling of the CD CHRDYRTN signal. This fix has been implemented in a 10ns PAL.
MC_CHRDY >> CD CHRDY signal that connects to the Micro Channel
MIA_CMD >> CMD signal between Miami and ALS245
MIA_S0 >> S0 signal between Miami and ALS245
MIA_S1 >> S1 signal between Miami and ALS245
MIA_CHRDY >> CD CHRDY signal that connect Miami to the PAL
MC_CHRDY =
_________
( ( Miami_CMD + CD_SFBK + (Miami_S0 * Miami_S1) ) * Miami_CHRDY )
Reference - PTR 128/140
Description - If the Async. Data Parity Error function is disabled (see POS3B register for description of ADP function) and an ADP occurs, bit '2' on all register reads of Miami from the CFE bus reads back as a '1' until the LBPE register is read to clear the ADP interrupt.
Work Around -
Reference - PTR
Problem Area - Miami DMA writes to the Micro Channel may result in the corruption of the last one, two, or three bytes written out to the Micro Channel.
Description - When the DMA channel is programmed to do unaligned DMA write transfers from the CFE bus to the Micro Channel, and the Miami DMA is preempted on the CFE bus at or near the last word read into the chip off the CFE bus, Miami may prematurely write data onto the Micro Channel prior clocking the read data from the CFE bus into the internal RAM. This results in the data that was previously clocked into the RAM being written out on to the Micro Channel bus.
Work Around -
Do not preempt the Miami DMA read transfer on the CFE bus. Ownership of the CFE bus by the DMA channels is indicated by the presence of the LMSTRREQ_ signal active during the ADS phase of the transfer. Holding the LMSTRACK_ active until Miami release its request will prevent this problem from occurring.
Reference - PTR
Problem Area - Micro Channel reads to CFE bus addresses through the shared memory window.
Description - At the end of a Micro Channel slave read to CFE address space, the Miami LSLVEREQ_ signal may go active for 1 to 2 clocks after it has relinquished ownership of the bus for a previous CFE read transfer. When the CFE bus arbiter sees the 1 to 2 clock 'low' pulse on the request signal, it returns LSLVEACK_ active for 1 to 2 clocks. Miami latches and holds this active state of the acknowledge signal internally. Having latched the acknowledge active, Miami will get on the CFE bus the next time the SLVEREQ_ signal goes active regardless of the state of the acknowledge signal on the bus. This action can cause CFE bus conflicts and CFE bus hangs.
cfe_clk | | | | | | | | | | |
Mia_blast ------+ +-------------------------------------------
+-----------+
rdy ------------+ +-------------------------------------------
+-----+
Mia_lslvereq_ +-----------------+g l i t c h+-----------+
------+ +-----------+ +-------------
Mia_lslveack +-----------------+ +------------------
------------+ +------------+
Mia_ads_ ------------------------------------------------------+ +-
+-----+
Work Around -
The following fix prevents Miami from receiving LSLVEACK_ when the 1 to 2
clock glitch occurs:
+-+
Arbiter_Ack | |
---------+-D |
| | Q----+ |---\
| | | +---------------| \ Mia_Slvacknowledge
cfe_clk-----+-> | +---------------|OR3 |-------------
| +-+ | +----------| /
| | | |---/
+--------+ |
|
Mia_Slvrequest |
----------------------+
Reference - PTR 263
Description - A Micro Channel slave can indicate the desire to perform 160 MB/s streaming transfers by driving both SDR0_ and SDR1_ active low in response to a valid decode of its memory space. Miami incorrectly interprets the SDR1:0 = '00' combination and performs default (10 MB/s) transfers rather than performing the transfer using 64-bit streaming (80 MB/s) which it is capable of doing.
Note that only a few RS6000 machines are actually capable of performing 160 MB/s transfers.
Work Around -
--------------+
|
MIAMI | SDR1 "cut"
+----------------+------/ /-------<< MC connector
| >
| > r=20K
-------------+ >
+5v |
----+
Reference - PTR 302
Description - The problem occurs during a streaming data read by Miami on the Micro Channel: the Micro Channel status lines -S0 (read) and -S1 (write) switch, causing the slave (Streamline bridge chip) to assert CD CHRDY without recovery, hanging the system. Problem Area - The problem occurs when the system asserts the ARB/GNT signal high on the Micro Channel (indicating an arbitration cycle) after an extended period of time from its detection of an end-of-transfer (EOT) condition on the Micro Channel. Bus masters are required to hold the EOT transfer state until an arbitration cycle occurs. Miami's Micro Channel state machine is held correctly in the EOT state, but in some instances, Miami completes the transfer on the Local Bus and begins a list chain operation while the Micro Channel state machine is still held in this state. This creates a condition whereby the local bus is actually writing data on to the CFE bus before the Micro Channel reads the data into the Miami chip, resulting in corrupt read data. Eventually this action also results Miami switching the status lines in the middle of a Micro Channel transfer causing the system to hang.
Work Around -
Guaranteeing that Miami DMA transfers do not end on a 64-byte boundary is a function of the system address and the byte count. For each transfer, the starting system address determines the alignment of read data from the Micro Channel input into the buffer. Specifically, address lines SA2-0 define whether the data starts on byte 0 through 7 respectively in the buffer. The starting alignment of the buffer determines the amount of data that can be written to the buffer. For example, starting with a system address of SA2-0 = 3, the data starts at location 3 in the buffer, and there are 61 byte locations available in the buffer. A byte count of 61 (3D h) would place the end of the transfer on an internal boundary of 64-bytes.
Given that the internal buffer locations are accessed as 32-bit words, a byte count that includes a partial word access of the last location in a buffer will force the DMA transfer to end on a buffer boundary. That is, the buffers are organized as 16 four-byte words, and the transfer must not end on the access of the sixteenth location. In the previous example, a byte count of 58 (3A h) will also force termination on a buffer boundary, with one byte in the final location.
Note:
When Miami is driving data on the CFE bus, it only drives (enables its drivers) for bytes that are considered to be valid for the given transfer as determined by the LBE signals during the address phase. It is important that a CFE device receiving data from Miami only check parity on valid bytes as described in the CFE specification.
Problem Area - Slow rise time on Streaming Data request may cause slave streaming termination error.
Configuration - Streaming master accessing Miami as Micro Channel streaming slave.
Description - No known problems result from this error. The streaming data request signals--MSDR and SDR0(SDR1 is not driven)--are not actively restored to an inactive high state before tristating. As a result, they rely on the pullup provided to restore the request to a high state. The rise time, therefore, may be too slow for slave termination of streaming data, and is also dependent on the loading of these signals.
Work Around -
Reference - PTR 20
Problem Area - Overrun of Micro Channel master internal buffer can cause corrupt data to be written to a Micro Channel slave.
Configuration - Miami writing the Micro Channel as a master.
Description - When Miami writes to the Micro Channel as a master starting on an odd 32-bit word boundary (i.e. SAR bit 2=1), the chip fails to increment its internal buffer counter correctly. As a result, the chip does not terminate its write on the Micro Channel correctly, but accesses over an internal buffer boundary. This problem can occur for transfers greater than 124 bytes.
Work Around -
Reference - PTR 24
Problem Area - Appended I/O transfers cause corrupt data on next data transfer.
Configuration - Miami performing Appended I/O operation to an address xxx7 h or xxxF h, where 'x' is any value.
Description - When Miami performs an Appended I/O operation to an I/O location ending in 7 or F, i.e. the highest byte of a 32-bit word, the internal buffer counters are corrupted. As a result, the next data transfer list chained or programmed into the channel CDB will execute with data errors.
Work Around -
Reference - PTR 29
Problem Area - Data Hold time on streaming writes causes bit errors on write data to Local Bus.
Configuration - Micro Channel master writing Miami as Micro Channel streaming slave.
Description - Bit errors can occur when performing streaming writes to Miami due to hold time problems on streaming data. The bit errors occur only on the next-to-last transfer before a master termination of streaming.
Work Around -
Reference - PTR 30
Problem Area - CD CHRDY timeout as a Micro Channel slave causes the system to hang with a system NMI.
Configuration - Micro Channel master accessing Miami as Micro Channel slave causes system NMI or system to hang.
Description - In some instances when reading or writing Miami as a slave, Miami pull CD CHRDY low, or "not ready", then attempts to release CD CHRDY prior to the 30 ns maximum from status. These instances occur when a write buffer becomes empty at the instant of access by the Micro Channel master, or when the read prefetch buffer is full for a contiguous address during a bursting read from the Micro Channel. Miami releases CD CHRDY internally, but not externally, resulting in a CD CHRDY hang condition on the Micro Channel.
Work Around -
Reference - PTR 31
Problem Area - When a Micro Channel slave read occurs while a Micro Channel posted slave write is active on the Local Bus, the Local Bus can hang. Likewise, when a Micro Channel slave write occurs while a Micro Channel posted slave read is active on the Local Bus, the Local Bus can hang.
Configuration - Micro Channel master accessing Miami as Micro Channel slave causes Local Bus to hang.
Description - If the Micro Channel reads Miami a slave while Miami is perform a write to the Local Bus with SLVEREQ active, i.e. flushing a posted write buffer to the Local Bus, the bus can hang.
Work Around -
Reference - PTR 32
Problem Area - When Micro Channel slave reads occur back-to-back with a minimum -CMD high time of 120ns, Miami can miss the CD CHRDY timing. The only system known to have this timing is the RS6000.
Configuration - Micro Channel master accessing Miami as Micro Channel slave with back-to-back reads.
Description - As a result, of this problem, the system will perform a default cycle. This can result in bad data, since Miami intended to deassert CD CHRDY. In addition, Miami may continue to request the Local Bus after the end-of-transfer (EOT) on the Micro Channel. Miami may block the next slave request to the Local Bus.
Work Around -
Reference - PTR 34
Problem Area - When resetting a bit in the Source Identification Register (SIR) from the Local Bus using the documented method, other bits can be reset.
Configuration - Bits in the SIR are reset by writing a zero to the correct bit location, with all other locations set to one to protect from being reset. Using this method some bits may still get reset.
Description - The timing of transferring write data from an internal holding register to the SIR allows bits rising from zero to one to miss the setup time to the SIR. Therefore, some bits may be reset with a zero that were intended to remain set with a one.
Work Around -
Reference - PTR 39
Problem Area - When Miami is performing 64-bit streaming DMA cycles on the Micro Channel, the DMA channel may halt with an Invalid Combination error in the BMSTAT register (bit 4 of BMSTAT @1FFAx018 h on CFE).
Configuration - Miami accessing the Micro Channel as a 64-bit streaming master
Description - Miami continuously checks the DS16/32RTN signals during a 64-bit streaming cycle. During 64-bit streaming, data is placed on the address bus causing the DS16/32RTN lines to toggle. The Miami chip inadvertently samples DS16RTN inactive and DS32RTN active, causing the DMA channel to halt with bit 4 of the BMSTAT set.
Work Around -
Reference - PTR 41
Problem Area - Systems or Bus Masters that do not support parity can force a parity error on Miami if they change data while -CMD is active on the Micro Channel.
Configuration - Non-Parity master accessing Miami as a Micro Channel slave with parity enabled in Miami POS registers.
Description - Miami can assert an asynchronous -CHCK when data parity errors occur while -CMD is active. The Micro Channel spec states that data parity is valid before -CMD is active, and is held valid until -CMD is inactive. Some systems, however, disable data transceivers on inactive bytes (e.g. upper bytes of low word transfer), while -CMD is ACTIVE. Both Miami Pass 1 AND 2 assert asynchronous -CHCK for this condition.
Work Around -
Reference - PTR 65
Problem Area - Non sequential addressing of Miami (when -BURST is active) for a Microchannel slave read causes invalid local bus prefetching and eventually a bad word of data during the next read access to Miami.
Configuration - A bursting Microchannel master reading Miami as a memory or I/O slave.
Description - When a bursting Microchannel master (-BURST active for 2 or more Microchannel cycles) reads Miami via the shared memory window or the MDATA port, and then on the subsequent cycle accesses (read or write) at an address that is non-sequential from the previous read (ie. a sequential access would be address1=xxx04, address2=xxx08), the subsequent cycle causes prefetching to occur on the local bus and continue until the current master on the Microchannel issues and end of transfer (EOT). If the current master were to come back to Miami, prior to issuing the EOT, for another read while the continuous prefetching is occurring, a bad word of data may be passed onto the Microchannel.
Work Around -
ALS241
-------
-BURST from ------+------------| < < |------- +5 volts
Miami | ---o---
| +-----+
| | ALS241
| | -------
+------------| > > |------------ -BURST on
| ------- Microchannel
| |
+BMSTREN from --------------+-----+
Miami
Reference - PTR 42
Problem Area - Stopping the DMA channels by writing the CCR or BMCMD register may cause subsequent list chaining operations to be corrupted. The corrupted list chain operation causes the DMA control registers (CDB registers) to be loaded with incorrect values.
Configuration - Local Bus masters writing directly to Miami's CCR start/stop bit or the start/stop bit through the BMCMD register can cause list chaining errors.
Description - If a local bust master writes the start/stop bit of a DMA channel when the Miami LMSTRREQ_ (local bus request signal) is pending but hasn't been acknowledged yet, and the request is for one of Miami's DMA channels to perform a list chaining operation (load the CDB regs), the list chain operation will be initiated on the local bus and terminate prior to loading all 6 CDB registers. This pre-mature termination of the list chaining operation causes the list chain state machine to get out of synchronization with the internal list chain CDB register pointer. When the DMA channel is restarted, the subsequent list chain operation will load the CDB registers in the wrong order. The CDB registers will be loaded starting with the register following the last one loaded during the list chain operation that prematurely terminated.
The problem is further worsened by the fact that both DMA channels share the same list chaining state machine. When one channels list chaining operation is prematurely terminated, both DMA channels will be out of sync. during all subsequent list chain operations.
Work Around -
Reference - PTR 71
Problem Area - A local bus read data parity error occurs when a local bus master reads from the Miami 1ffa xxxxh address region and no valid register exists at the specific address location.
Configuration - A local bus master reading the local bus region 1ffa0000h - 1ffaffffh where no specific Miami register is located.
Description - Miami returns local bus Ready (LREADY_) for all local bus accesses in the 1ffa address region. For locations where no Miami register exists, the entire data path internal to Miami (including the parity bits) are forced to zero. Forcing both data and parity to zero causes Miami to drive invalid data parity for these accesses.
Work Around -
Reference - PTR 74
Problem Area - When a bursting Microchannel master writes to Miami in the shared memory regions, 1-3 bytes of data in a word can be corrupted when the data is written out on to the local bus.
Configuration - A bursting (-BURST active) Microchannel master performing basic transfer writes to Miami as a slave on the Microchannel.
Description - While -BURST is active, if the Micro Channel master accesses Miami as a slave with non-sequential writes, 1-3 data bytes in a word transferred on the local bus get corrupted. This problem occurs when the master writes less than a full word (1-3 bytes) to Miami at one address followed by a write to Miami of a full word (or a different byte enable combination than the previous write) to a non-sequential address (from the previous write). The corruption of data occurs on the second write to Miami. This kind of action occurs when the Micro Channel master is a Miami with both DMA channels active (using the same ARB level) such that both channels can write to the Miami slave under the same Micro Channel bus ownership period. This kind of scenario may also occur in systems that drive -BURST as a master.
Work Around -
-------
-BURST from ------+------------| < < |------- +5 volts
Miami | ---o---
| +-----+
| |
| | -------
+------------| > > |------------ -BURST on
| ------- Microchannel
| |
+BMSTREN from --------------+-----+
Miami
Reference - PTR 91
Problem Area - Microchannel masters reading Miami as an I/O slave through the HSBR/MDATA port mechanism will not see a Channel Check when an exception occurs on the local bus when the read is accessing the non-burst region on the local bus (0h to 1FFFFFFFh).
Configuration - Microchannel masters reading non-burst local bus address space through Miami's MDATA port.
Description - When reading local bus address space in the non-burst region (addresses from 0-1FFFFFFF) through the MDATA port, local bus exceptions and read data parity errors are not reported as a Channel Check on the Micro Channel. Miami holds CHRDY inactive for the 3.4usec timeout period, and then releases ready and passes invalid data onto the Microchannel Bus.
Work Around -
Reference - PTR 110
Problem Area - RS6000 XIO Microchannel master writing Miami as a Memory slave with Streaming enabled may cause write data errors as a result of an extra data strobe.
Configuration - RS6000 XIO Machines performing Streaming writes to Miami.
Description - During Streaming Micro Channel slave writes to Miami, Miami may defer the start of the streaming transfer by negating the CD_CHRDY signal, indicating that Miami is NOT ready to accept data (all internal buffers are full). As soon as an internal Miami buffer is available, Miami asserts CD_CHRDY indicating that Miami is ready to accept the write data. Miami fully complies with the negation timings of CD_CHRDY, and by Micro Channel definition, no timings apply to the assertion of CD_CHRDY.
The negation/assertion of CD_CHRDY on the Micro Channel, however, does not operate correctly with the XIO design. The XIO system master to the Micro Channel, in this case, samples CD_CHRDYRTN with two separate latches, one for SD STROBE, and one for everything else. In cases where the freeing of Miami's buffers coincides with the start of a Micro Channel cycle, the assertion of CD_CHRDY can be sampled high by one latch and low by the other latch in the XIO design. This missampling of CD_CHRDY causes an additional SD STROBE and the subsequent data errors.
Work Around - As a result of this problem, Miami's CD CHRDY must be held inactive until after CMD becomes active on the Micro Channel. The following workaround will prevent this problem:
Channel Ready (MC_CHRDY) to the Micro Channel should no longer be driven directly by the Miami (Miami_CHRDY) and should now be driven by the following logic equation ( '+' is a logic 'OR' , '*' is a logic 'AND'):
MC_CHRDY =
_________
( ( Miami_CMD + CD_SFBK + (Miami_S0 * Miami_S1) ) * Miami_CHRDY )
Figure 14. Miami component detail
______________
||||||||||||||||||||||||||||||||||||||||||__________ A
/ \ A |
=| |= | |
=| |= | |
=| |= | |
=| |= | |
=| |= | |
=| |= | |
=| |= | |
=| |= | |
=| |= | |
=| |= +---|--32.00 / 1.362
=| |= | |
=| |= | +--34.60 / 1.260
=| |= | |
=| |= | |
=| |= | |
=| |= | |
=| |= | |
=| |= | |
=| |= | |
=| |= | |
=| |= | |
240 =| |= | |
\__________________________________________/_______V__ |
||||||||||||||||||||||||||||||||||||||||||____________V__
|| A
1 ->||<---0.50 /.0197 |---> 0.23 / .009
| | |
____________________________________________ ______|__V___V_
_/ \_ |
/ \ |||||||||||||||||||||||||||||||||||||||||| / \ ___V____
_/ |||||||||||||||||||||||||||||||||||||||||| \_ ____A_____
A A A | A
| | | | |
>| |<--- 0.50 / .020 0.30 / .012 MIN -------+ | |
3.40 / .134 REF ----------+ |
4.2 / .165 MAX ---------------+
Figure 15. Miami component footprint
________ +-+
A |O| O
| +-+_||||||||||||||||||||||||||||||||||||||||||_
| =| A |=--------
| =| | |= A
| =| +--- 0.2794 |= |
35.69 =| 0.11 |= |
1.405 =| (PAD) |= |
| =| (WIDTH) |= |
| =| |= |
| =| |= |
| =| |= |
| =| |= |
| =| |= 29.78
| ------ =|-------------------- X |= 1.1725
| A =| A |= |
| | =| | | | |= |
| | =| | | 14.880 | |= |
| | =| 14.880 | |<------------------>| |= |
| | =| -------+ | 0.5860 | |= |
| 17.59 =| 0.5860 | | | |= |
| 0.6928 =| | | | |= |
| | =| | | | |= |
| | =| | | | |= |
| | 239 =| | | | |= |
| | 240 =|____________V____ | | |= V
| | |____________________________________________|=---------
V V |||||||||||||||||||||||||||||||||||||||||| +-+
--------- O 1234 | |O|
| 17.59 | FIDUCIAL-------+ | +-+ |
|<-------------------->| CLEAR AREA \ +---+---+
| 0.6928 | \ | |
| \ V V
| +-----+ ------
__V___|___ |
| O |
| |
----- +-----+ ------
A A A
2.032 | | | 3.05
-------+ | 1.02 +----------
0.80 +----- 0.120
(PAD) 0.40
(HOLE)
SMT PAD SPACING (PITCH) FROM PAD CENTER LINE
* SPACING IS TO THE MEAREST 0.013 mm (.OOO5 in)
+=======+===============+=======+================+=======+====+============+
| PAD # | SPACING | PAD # | SPACING | PAD # | SPACING |
+=======+===============+=======+================+=======+=================+
| 1 | 0.000 (.0000) | 21 | 9.995 (.3935) | 41 | 20.003 (.7875) |
+-------+---------------+-------+----------------+-------+-----------------+
| 2 | 0.495 (.0195) | 22 | 10.503 (.4135) | 42 | 20.498 (.8070) |
+-------+---------------+-------+----------------+-------+-----------------+
| 3 | 1.003 (.0395) | 23 | 10.998 (.4330) | 43 | 21.006 (.8270) |
+-------+---------------+-------+----------------+-------+-----------------+
| 4 | 1.498 (.0590) | 24 | 11.505 (.4530) | 44 | 21.501 (.8465) |
+-------+---------------+-------+----------------+-------+-----------------+
| 5 | 1.994 (.1785) | 25 | 12.002 (.4725) | 45 | 21.996 (.8660) |
+-------+---------------+-------+----------------+-------+-----------------+
| 6 | 2.502 (.1985) | 26 | 12.497 (.4920) | 46 | 22.504 (.8860) |
+-------+---------------+-------+----------------+-------+-----------------+
| 7 | 2.997 (.1180) | 27 | 13.005 (.5120) | 47 | 23.000 (.9055) |
+-------+---------------+-------+----------------+-------+-----------------+
| 8 | 3.505 (.1380) | 28 | 13.500 (.5315) | 48 | 23.495 (.9250) |
+-------+---------------+-------+----------------+-------+-----------------+
| 9 | 4.001 (.1575) | 29 | 13.995 (.5510) | 49 | 24.003 (.9450) |
+-------+---------------+-------+----------------+-------+-----------------+
| 10 | 4.496 (.1770) | 30 | 14.503 (.5710) | 50 | 24.498 (.9645) |
+-------+---------------+-------+----------------+-------+-----------------+
| 11 | 5.004 (.1970) | 31 | 14.999 (.5905) | 51 | 25.006 (.9845) |
+-------+---------------+-------+----------------+-------+-----------------+
| 12 | 5.499 (.2165) | 32 | 15.494 (.6100) | 52 | 25.502 (1.0040) |
+-------+---------------+-------+----------------+-------+-----------------+
| 13 | 5.994 (.2360) | 33 | 16.002 (.6300) | 53 | 25.997 (1.0235) |
+-------+---------------+-------+----------------+-------+-----------------+
| 14 | 6.502 (.2650) | 34 | 16.497 (.6495) | 54 | 26.505 (1.0435) |
+-------+---------------+-------+----------------+-------+-----------------+
| 15 | 6.998 (.2755) | 35 | 17.005 (.6695) | 55 | 27.000 (1.0630) |
+-------+---------------+-------+----------------+-------+-----------------+
| 16 | 7.506 (.2955) | 36 | 17.501 (.6890) | 56 | 27.496 (1.0825) |
+-------+---------------+-------+----------------+-------+-----------------+
| 17 | 8.001 (.3150) | 37 | 17.996 (.7085) | 57 | 28.004 (1.1025) |
+-------+---------------+-------+----------------+-------+-----------------+
| 18 | 8.496 (.3345) | 38 | 18.504 (.7285) | 58 | 28.499 (1.1220) |
+-------+---------------+-------+----------------+-------+-----------------+
| 19 | 9.004 (.3545) | 39 | 18.999 (.7480) | 59 | 28.994 (1.1415) |
+-------+---------------+-------+----------------+-------+-----------------+
| 20 | 9.450 (.3740) | 40 | 19.495 (.7675) | 60 | 29.502 (1.1615) |
+-------+---------------+-------+----------------+-------+-----------------+
REMAINING PADS (3 SIDES) ARE A REPLICATION OF THIS SPACING
(1) The Performance Timer extends -BURST for up to 500ns after completion of a Micro Channel transfer, to allow time for more data to become available in the intermediate buffer. Independent of the state of this bit, the timer is not enabled when the byte count has reached zero, after detection of exception conditions, during reset, or when data is available for the other channel.
(2) The CD CHRDY timeout logic provides a mechanism to recover, with synchronous channel check, if a transfer to Miami as a Micro Channel slave exceeds 3.4 microseconds.
Last modified: October 4, 1996