IBM X.25 Interface Co-Processor/2
Technical Reference

Version 1.01

September, 1996


IBM may make improvements and/or changes in the product(s) and/or programs described in this publication at any time and without notice.

References in this publication to IBM products, programs, or services do not imply that IBM intends to make these available in all countries in which IBM operates. Any reference to an IBM licensed program in this publication is not intended to state or imply that only IBM's licensed program may be used. Any functionally equivalent program may be used instead.

No part of this book may be reproduced in any form or by any means, including storing in a data processing machine, without permission in writing from IBM.

Copyright International Business Machines Corporation 1988 All rights reserved.


Table of Contents

About This Book

  • Audience
  • Contents
  • Related publications
  • Other IBM X.25 Interface Co-Processor/2 Publications
  • Reference Publications
  • Conventions
  • Chapter 1. Introduction to X.25 Communications

  • Concepts of packet-switched data networks
  • DSEs, DTEs and DCEs
  • Levels of X.25
  • Physical level
  • Link level
  • Packet level
  • Logical channels
  • Virtual circuits
  • Types of logical channels
  • Chapter 2. Description of the IBM X.25 Interface Co-Processor/2

  • General description
  • Memory space
  • Programmable read-only memory
  • Dynamic random-access memory
  • Adapter microprocessor
  • Serial communications controller
  • Counter/timer and parallel I/O unit
  • Watchdog timer
  • Shared storage interface chip
  • PS/2 interface
  • Shared storage window
  • I/O block location
  • Adapter description file
  • Communications capabilities
  • Support functions
  • Other IBM communications co-processors
  • Chapter 3. Programming Considerations

  • Memory map
  • Programmable read-only memory
  • Dynamic random-access memory
  • Adapter 80186 microprocessor
  • Physical characteristics
  • Programming considerations
  • Interrupt lines
  • Interrupt register addresses
  • DMA channel allocation and registers
  • Peripheral control block
  • Memory
  • Zilog Z8030 serial communications controller
  • Functions
  • SCC registers
  • Programming the SCC
  • Zilog Z8036 counter/timer and parallel I/O unit
  • Functions
  • CIO registers
  • Programming the CIO
  • CIO port assignments and description
  • Hardware resource allocation
  • 80186 microprocessor interrupts
  • 80186 microprocessor timer/counters
  • 80186 microprocessor DMA channels
  • Z8036 CIO timers
  • Shared storage interface chip
  • DRAM access
  • Programming considerations
  • SSTIC register summary
  • Memory mapping
  • Relocation and paging
  • I/O block location
  • Adapter description file
  • SSTIC register descriptions
  • Chapter 4. X.25 Network Interface

  • X.21 interface
  • X.21 bis/V.24 interface(RS232)
  • X.21 bis/V.35 interface
  • Cables and connectors
  • Cable identification
  • D-37 connector
  • X.21 interface cable
  • X.21 bis/V.24 interface cable
  • X.21 bis/V.35 interface cable
  • Local loopback-test plugs
  • Chapter 5. Adapter Characteristics

  • Physical characteristics
  • Adapter technology
  • Adapter connectors
  • Electrical characteristics
  • Environmental characteristics
  • Product class assignment
  • Cooling
  • Heat output
  • Usability characteristics
  • Chapter 6. PROM Microcode Support

  • Support provided
  • Power-on self-test
  • Errors
  • Diagnostic subroutines
  • List of diagnostic subroutines
  • General invocation
  • General error handling
  • Test DRAM subroutine
  • Checksum subroutine
  • Get memory size subroutine
  • Test microprocessor subroutine
  • Test CIO subroutine
  • Test SCC subroutine
  • Test SSTIC subroutine
  • Get communications port identity subroutine
  • Configure CIO port subroutine
  • Configure SCC port subroutine
  • Configure DMA channel subroutine
  • Configure CIO timers subroutine
  • Configure watchdog timer subroutine
  • Switch interrupt priorities subroutine
  • Get X.25 electrical interface assembly identifier subroutine
  • PROM services
  • General invocation
  • List of PROM services
  • Interrupt PS/2 subroutine
  • Reset an SCC port subroutine
  • Access SCC registers subroutine
  • Access CIO registers subroutine
  • CIO timer support subroutine
  • Connect DMA channel(s) subroutine
  • Set up and start DMA channel subroutine
  • Access DMA channel registers subroutine
  • Stop DMA channel subroutine
  • Convert logical to physical address subroutine
  • Convert segment to page subroutine
  • Convert page to segment subroutine
  • Pointer to EBCDIC-ASCII tables
  • Convert EBCDIC string to ASCII subroutine
  • Convert ASCII string to EBCDIC subroutine
  • Add element to intrasegment ring subroutine
  • Remove element from intrasegment ring subroutine
  • Add element to intersegment ring subroutine
  • Remove element from intersegment ring subroutine
  • Bootstrap loader subroutine
  • Dump facility
  • Dump1 subroutine
  • Dump2 subroutine
  • Chapter 7. Glossary


    About This Book

    The IBM X.25 Interface Co-Processor/2 is an adapter that plugs into a single I/O slot in an IBM Personal System/2 (PS/2) computer Model 50 through Model 80. It allows a PS/2 to communicate over an X.25 packet-switched network. The adapter has its own microprocessor and memory, thus allowing it to carry out most of the communications work that would otherwise be done by the PS/2. For brevity and for the remainder of this manual, the IBM X.25 Interface Co-Processor/2 is called "the adapter" and "co-processor" is defined as the ARTIC family of co-processors which include the IBM Realtime Interface Co-Processor, the IBM Realtime Interface Co-Processor Multiport, the IBM Realtime Interface Co-Processor Multiport/2 and the IBM Realtime X.25 Co-Processor/2.


    Audience

    The information in this publication is both introductory and reference. It is intended for hardware and software designers, programmers, engineers, and those with a knowledge of electronics and/or programming who need to understand the operation of the IBM X.25 Interface Co-Processor/2.

    The reader is assumed to have some knowledge of telecommunication protocols, although an introduction to X.25 packet-switched data networks is contained in Chapter 1.


    Contents

    Chapter 1
    Introducing X.25 packet-switched networks: This chapter gives an overview of X.25 packet-switched networks.

    Chapter 2
    Description of the IBM X.25 Interface Co-Processor/2: This chapter describes the adapter hardware and how it operates; it also relates the adapter to other IBM communications co-processors.

    Chapter 3
    Programming considerations: This chapter gives programming considerations and a detailed description of the:

    1. Adapter microprocessor, including the purpose and contents of its registers.

    2. Serial communications controller (SCC), including the purpose and contents of its registers.

    3. Shared storage interface chip (SSTIC), including the purpose and contents of its registers.

    4. Counter/timer and parallel I/O unit (CIO), including the purpose and contents of its registers.

    5. I/O map.

    6. Watchdog timer.

    7. Hardware resource allocation.

    Chapter 4
    X.25 Interface: This chapter describes the network interface. It covers in detail the X.21 interface, the X.21 bis/V.24(RS232) interface, and the X.21 bis/V.35 interface.

    Chapter 5
    Adapter characteristics: This chapter describes the physical and electrical characteristics of the adapter.

    Chapter 6
    PROM microcode support: This chapter describes the power-on self-test and all the support subroutines resident in the adapter programmable read-only memory (PROM).

    Glossary
    The glossary contains definitions of special terms and abbreviations used in this manual but not in general use in other PS/2 publications.

    Related publications

    The library for the IBM Realtime Interface Co-Processor, the IBM Realtime Interface Co-Processor Multiport, and the IBM Realtime Interface Co-Processor Multiport/2 should be used for further information. The library consists of the following publications:


    Other IBM X.25 Interface Co-Processor/2 Publications

    The following publications provide information about installing and servicing the IBM X.25 Interface Co-Processor/2:

    The definitive X.25 reference is the CCITT (International Telegraph and Telephone Consultative Committee) Recommendation X.25.


    Reference Publications

    One or more of the following publications may be needed for reference when using this manual.


    Conventions

    Hexadecimal numbers are designated by a trailing "h", for example FFFFh, 18h, and so on. Assume decimal numbers if no trailing "h" is present.


    Chapter 1. Introduction to X.25 Communications


    Concepts of packet-switched data networks

    A packet-switched data network (PSDN) is an interconnecting set of intelligent switching nodes that enables subscribers to exchange data using a standard protocol and packet-switching technology. Such a network carries messages divided into parts (called packets) over circuits that are shared by many network users.

    Because several users simultaneously share the same circuits, a protocol is necessary to ensure that the network correctly routes data to its destination.

    In 1976, a protocol for attaching user equipment to a PSDN was defined by the International Telegraph and Telephone Consultative Committee (CCITT) in "CCITT Recommendation X.25".

    In 1980, a revision of the recommendation was published. This gave firm specifications for many aspects that were previously open to different interpretation. Today, most of the public packet-switched data networks throughout the world are based on CCITT Recommendation X.25 (1980).

    In 1984 a further revision of the recommendation was published and many X.25 networks are being upgraded to incorporate enhancements and changes defined at this level.


    DSEs, DTEs and DCEs

    The CCITT has defined the following terminology:

    Every DTE must have an associated DCE.

    Note: DTE and DCE are functional definitions. They need not correspond to specific items of equipment. For example, a single device may be a DSE and may also provide multiple DCE interfaces.

    CCITT Recommendation X.25 defines a standard protocol for information exchange in packet mode between a DTE and a DCE. The elements of a packet-switched data network are shown in Figure 1.

    Figure 1. Elements of a packet-switched data network

                           +-----------+
          +--------------->|    DTE    |<------+
          |                +-----+-----+       |
          |                      |             |
          |                +-----+-----+       |
       Virtual             |    DCE    |    Logical
       circuit             +-----+-----+    channel
          |         +------------|----------+  |
          |      +--+      +-----+-----+     \ |
          |     /          |    DSE    |<------+
          |  +-+           +-----------+       \
          |  |                                  +------+
          |  |      X.25 PACKET-SWITCHED NETWORK       |
          |  +            at least one DSE             |
          |   \                                        +
          |    \ +-----------+       +-----------+    /
          |     \|    DSE    |       |    DSE    |<------+
          |      +-----+-----+       +-----+-----+  /    |
          |       +----|-------------------|-------+     |
          |      +-----+-----+       +-----+-----+       |
          |      |    DCE    |       |    DCE    |    Logical
          |      +-----+-----+       +-----+-----+    channel
          |            |                   |             |
          |      X.21 bis/V.24       X.21 bis/V.24       |
          |            |                   |             |
          |      +-----+-----+       +-----+-----+       |
          +----->|    DTE    |       |    DTE    |<------+
                 +-----------+       +-----------+
    
    Every DTE is connected to a DCE by a point-to-point, full-duplex link. Recommendation X.25 describes the physical attachment to this link, the link protocol, and the packet protocol between the DTE and the DCE/DSE. Recommendation X.25 does not specify the structure of, or the protocols used within, the network itself (that is, traffic between the DSEs).

    Levels of X.25

    The X.25 interface has three levels:

    1. Physical level.

    2. Link level.

    3. Packet level.

    Note: A term commonly used when referring to the X.25 interface at all three levels is the DTE/DCE interface. This term can be misleading because the DCE only supports the physical level. The physical access link is from DTE to DCE to DSE, and it is the DSE that has the intelligence to support link-level and packet-level protocols.

    Physical level

    The physical level activates, maintains, and deactivates the physical circuit between a DTE and a DCE.

    This level is defined in CCITT Recommendation X.21 and in CCITT Recommendation X.21 bis. CCITT Recommendation X.21 bis defines the connection of a DTE with a V.24 or a V.35 interface to a DCE as used by IBM X.25 Interface Co-Processor/2.

    Link level

    The link level uses a link access procedure to ensure that data and control information are accurately exchanged over the physical circuit between the DTE and DCE/DSE. Its functions include recovery procedures. The characteristics of this level are based on high-level data-link control (HDLC).

    HDLC defines two link access procedures:

    1. Link access procedure (LAP).

    2. Link access procedure balanced (LAPB).

    Both procedures are synchronous and full-duplex. Once a link is started, either station can transfer information on its own initiative without waiting for permission from the other.

    LAPB is the dominant procedure because it avoids some of the "hung" situations that can occur with LAP.

    In HDLC all commands, responses, and data are transmitted in frames. Each frame has a header containing address and control information, and a trailer containing a frame-check sequence.

    There are three types of frame:

    1. I frame.

    2. S frame.

    3. U frame.
    The format of each frame depends upon its type: The general format of a frame is shown in Figure 2.

    Figure 2. Frame format

    +------+------+------------+-----------------------+------+------+------+
    |      |      |            |                       |      |      |      |
    | FLAG | ADDR |  CONTROL   |     INFORMATION       | FCS1 | FCS2 | FLAG |
    |      |      |            |       (PACKET)        |      |      |      |
    +------+------+------------+-----------------------+------+------+------+
    
    The flag field is 1 byte and its value is always 7Eh.

    The address field is 1 byte in basic mode (modulo 8) and 2 bytes in extended mode (modulo 128) and can be:

    All other values are invalid.

    The control field is 1 byte and contains:

    The control byte is shown in Figure 3. Bit 1 is the lowest order bit and is the first bit to be transmitted.

    The information field is only present in I frames.

    The Frame-Check Sequence (FCS) field is 2 bytes and provides a check on the integrity of the data transmitted over the link.

    Figure 3. Control byte (modulo 8)

           Bit      1           2        3       4      5      6     7      8
    +----------+------------+-----------------------+-------+------------------+
    |          |            |                       |       |                  |
    | I frame  |     0      |        N(S)           |   P   |       N(R)       |
    |          |            |                       |       |                  |
    +----------+------------+----------+------------+-------+------------------+
    |          |                       |            |       |                  |
    | S frame  |     1            0    |  S      S  |  P/F  |       N(R)       |
    |          |                       |            |       |                  |
    +----------+-----------------------+------------+-------+-----------+------+
    |          |                       |            |       |           |      |
    | U frame  |     1            0    |  M      M  |  P/F  | M       M |   M  |
    |          |                       |            |       |           |      |
    +----------+-----------------------+------------+-------+-----------+------+
    
    The symbols have the following meanings:

    Packet level

    The packet-level protocol specifies how virtual circuits between DTEs are established, maintained, and cleared. This level defines how a single physical channel (the access link) can be treated as a set of multiple logical channels each providing a virtual circuit.

    It also defines the structure of data packets, and of the control packets used to establish and manage a virtual circuit between two DTEs in a PSDN.

    The recommendations for the packet level are not as specific as those for the physical and link levels, and network providers have some freedom in implementing the packet level functions.

    For example, some networks do not support the Diagnostic Code field in the Reset and Clear Indication packets.

    A packet is a unit of information transmitted from one DTE to another DTE through the network. It comprises a sequence of data and control elements in a special format that is always transmitted as a whole. The most common (default) packet size is 128 bytes (called octets). (Some networks allow a different default packet size to be specified and/or may allow the packet size to be negotiated at subscription time to the network. It can also be done dynamically on a "per-call" basis.) The maximum packet size can range from 16 to 4096 bytes.

    Each packet contains a header and user data and the general format of a packet is shown in Figure 4. Bit 1 is the low-order bit and is transmitted first.

    Figure 4. General format of a packet

       Bit   8       7       6       5         4       3       2      1
    Byte +--------------------------------+------------------------------+
         |                                |                              |
     0   |    General format identifier   | Logocal channel group number |
         |                                |                              |
         +--------------------------------+------------------------------+
         |                                                               |
     1   |                      Logical channel number                   |
         |                                                               |
         +---------------------------------------------------------------+
         |                                                               |
     2   |                      Packet type identifier                   |
         |                                                               |
         +---------------------------------------------------------------+
         |                                                               |
         |                                                               |
         |                                                               |
         +----                       user data                       ----+
         |                                                               |
         |                                                               |
         |                                                               |
        ===                                                             ===
    
    Each packet is identified by a general format identifier and by a packet type identifier.

    The logical channel group number and the logical channel number together are called the logical channel identifier.

    Packets are grouped into the following categories, according to type:

    Some of the most common control packet exchanges are shown in Figure 5 through Figure 8.

    Figure 5. Establishing a switched virtual circuit

    +-------+ Call Request  +--+----------+--+ Incoming Call +-------+
    |      1|-------------->|D |          |D |-------------->|2      |
    | DTE   | Call Connected|C |   PSDN   |C |               |   DTE |
    |      4|<--------------|E |          |E |<--------------|3      |
    +-------+               +--+----------+--+ Call Accepted +-------+
    
    Figure 6. Clearing a switched virtual circuit
    +-------+ Clear Request +--+----------+--+ Clear Indicate+-------+
    |      1|-------------->|D |          |D |-------------->|2      |
    | DTE   |               |C |   PSDN   |C |               |   DTE |
    |      4|<--------------|E |          |E |<--------------|3      |
    +-------+ Clear Confirm +--+----------+--+ Clear Confirm +-------+
    
    Figure 7. DTE initiated reset
    +-------+ Reset Request +--+----------+
    |      1|-------------->|D |          |
    | DTE   |               |C |   PSDN   |
    |      2|<--------------|E |          |
    +-------+ Reset Confirm +--+----------+
    
    Figure 8. DCE initiated reset
    +-------+ Reset Indication +--+----------+
    |      1|----------------->|D |          |
    | DTE   |                  |C |   PSDN   |
    |      2|<-----------------|E |          |
    +-------+ Reset Confirm    +--+----------+
    

    Data packets

    In data packets the packet header can be either 3 or 4 bytes, depending on the packet modulo used. The packet headers are shown in Figure 9 and Figure 10.

    Figure 9. Data packet with modulo 8

       Bit   8        7         6         5       4      3      2       1
    Byte +-------+---------+---------+---------+----------------------------+
         |       |         |         |         |                            |
     0   |   Q   |    D    |    1    |    0    |Logical Channel Group Number|
         |       |         |         |         |                            |
         +-------+---------+---------+---------+----------------------------+
         |                                                                  |
     1   |                       Logical Channel Number                     |
         |                                                                  |
         +---------------------------+---------+--------------------+-------+
         |                           |         |                    |       |
     2   |         P(R)              |    M    |        P(S)        |   0   |
         |                           |         |                    |       |
         +---------------------------+---------+--------------------+-------+
         |                                                                  |
         |                                                                  |
         |                                                                  |
         +----                        user data                         ----+
         |                                                                  |
         |                                                                  |
         |                                                                  |
        ===                                                                ===
    
    P(R)    = packet receive sequence number
    P(S) = packet send sequence number
    M = more data bit (MDB)
    Q = qualified data bit (Q bit)
    D = delivery confirmation bit (D bit)

    Figure 10. Data packet with modulo 128

       Bit   8         7         6         5      4     3     2       1
    Byte +--------+---------+---------+--------+----------------------------+
         |        |         |         |        |                            |
     0   |   Q    |    D    |    1    |    0   |Logical Channel Group Number|
         |        |         |         |        |                            |
         +--------+---------+---------+--------+----------------------------+
         |                                                                  |
     1   |                     Logical Channel Number                       |
         |                                                                  |
         +--------------------------------------------------------+---------+
         |                                                        |         |
     2   |                          P(S)                          |    0    |
         |                                                        |         |
         +--------------------------------------------------------+---------+
         |                                                        |         |
     3   |                          P(R)                          |    M    |
         |                                                        |         |
         +--------------------------------------------------------+---------+
         |                                                                  |
         |                                                                  |
         |                                                                  |
         +----                       user data                          ----+
         |                                                                  |
         |                                                                  |
         |                                                                  |
        ===                                                                ===
    
    P(R)    = packet receive sequence number
    P(S) = packet send sequence number
    M = more data bit (MDB)
    Q = qualified data bit (Q bit)
    D = delivery confirmation bit (D bit)
    See X.25 Interface for Attaching SNA Nodes to Packet-Switched Data Networks, General Information Manual, GA27-3345 or the X.25 Interface for Attaching IBM SNA Nodes to Packet-Switched Data Networks, General Information, SC30-3409 for further information on the various command packet formats.

    Logical channels

    A physical circuit between a DTE and a DSE can be multiplexed into several logical channels.

    Packet-switched data networks use statistical multiplexing, where time is divided according to the length of a message, and each channel is recognized by a header placed in front of the message. A logical channel can be seen as an independent path that allows data to travel from its origin through the network to its destination.

    A physical circuit connecting a DTE to a DCE/DSE can have up to 4096 logical channels assigned to it. A logical channel identifier is used to identify the flow of data between the DTE and the PSDN. By assigning several logical channels to the single physical connection, one DTE can communicate simultaneously with several other DTEs through the PSDN. (If Systems Network Architecture (SNA) protocols are used, there can be multiple SNA sessions on each logical channel.)

    A DTE must place a logical channel identifier in the header of the packet before sending it to a DCE/DSE. The logical channel identifier associates the packet with a virtual circuit between two DTEs. The PSDN uses this logical channel identifier to route the packet throughout the network to its destination DTE.

    The PSDN administrator assigns a series of logical channel identifiers to each subscriber. These are composed of a logical channel group number (0 to 15) and a logical channel number (0 to 255).


    Virtual circuits

    It can be seen from Figure 1 that a logical channel is defined between a DTE and a DCE/DSE. A virtual circuit is a logical connection between two DTEs attached to the network.

    A virtual circuit consists of:

    A virtual circuit can have a different logical channel identifier at each DTE.

    The source-destination associations defined in the network can either be permanent or only established when the user makes a call. These two modes define the two types of virtual circuit:

    A permanent virtual circuit (PVC) is logically similar to a point-to-point leased line. It represents a permanent association between two DTEs and requires no call setup or call clearing by the DTEs.

    A switched virtual circuit (SVC) is a temporary association between two DTEs. It is initiated by one DTE sending a Call Request packet to the network. Because SVCs are established and released dynamically, the corresponding logical channels are usually allocated from a pool of such resources defined for each DTE/DCE interface.


    Types of logical channels

    The types of logical channels are defined according to the capability of a DTE to initiate a call.


    Chapter 2. Description of the IBM X.25 Interface Co-Processor/2


    General description

    The IBM X.25 Interface Co-Processor/2 is a single-slot, full-length adapter for use in IBM Personal System/2(TM) (PS/2(TM)) computers models 50 through 80. The adapter contains:

    The major components of the adapter are shown in Figure 11.

    Figure 11. Block diagram of IBM X.25 Interface Co-Processor/2

                               Oscillator
                             +-------------+
                             |  14.74 MHz  |
                             +------+------+
                                    |
                                    V           Z8036 Counter
                                  80186         Timer and
         DRAM         PROM    Microprocessor    Parallel I/O Unit
      +--------+   +--------+   +--------+      +--------+          +-----+
      |        |   |        |   |        |      | Port 2 |--------->| LED |
      | 512 Kb |   |        |<--|        |      |        |          +-----+
      |        |   |        |   |        |      |        |                     D-37
      +--------+   +--------+   +--------+  +==>|        |    +-----------+    +--+
            A                       A       |   | Port 1 |<-->|           |    |  |
            |                       |       |   |        |    |           |    |  |
            V                       |       |   | Port 0 |<-->|           |    |C |
        +--------+                  |       |   +--------+    |           |    |O |
        |        |                  |       |                 | X.25      |    |N |
        |        |                  |       |                 | Electrical|<-->|N |
    --->|        |<=================+=======+   +--------+    | Interface |    |E |
    To  |        |                          |   |        |    | Assembly  |    |C |
    PS/2|        |                          |   | Port 0 |<-->|           |    |T |
        +--------+                          |   |        |    |           |    |O |
        Shared Storage                      +==>|        |    |           |    |R |
        Interface Chip                          | Port 1 |--->|           |    |  |
                                                |        |    |           |    |  |
                                                |        |    +-----------+    +--+
                                                +--------+
                                                Z8030 Serial          X.21
                                                Communications        X.21 bis/V.24
                                                Controller            X.21 bis/V.35
    

    Memory space

    Adapter memory consists of 16 KB of programmable read-only memory (PROM) and 512 KB of dynamic random-access memory (DRAM).

    Programmable read-only memory

    Programmable read-only memory (PROM) contains microcode that provides the following support:

    The adapter read-only memory cannot be read by tasks running on the PS/2. See Chapter 6. PROM Microcode Support for details.

    Dynamic random-access memory

    Tasks running on the 80186 microprocessor can access all 512 KB of DRAM. Tasks running on the PS/2 can access adapter DRAM through an 8, 16, 32 or 64 KB memory window. The window starts on 8, 16, 32 or 64 KB boundaries depending on the window size. Although not recommended, the size and location of this shared storage window can be dynamically changed by tasks running on the PS/2 and the adapter. The window is called the shared storage window and is controlled by registers in the shared storage interface chip (SSTIC).

    The SSTIC acts as a dual-ported DRAM controller arbitrating between the 80186 microprocessor and the PS/2 microprocessor for DRAM access. It also:


    Adapter microprocessor

    Processing power is provided by an 80186 microprocessor. The 80186 microprocessor has twice the performance of the 8086 microprocessor and combines several 8086 system components into one package. The microprocessor can be used for:


    Serial communications controller

    The serial communications controller (SCC) provides:

    It provides bit-transparency and error detection for the X.25 communications interfaces. Once initialized by the realtime control microcode (RCM) and support software, the SCC performs a major portion of the X.25 level-1 communications workload.

    Counter/timer and parallel I/O unit

    The counter/timer and parallel I/O unit (CIO) provides:

    The two 8-bit ports are used to control the flow of data through the X.25 interfaces. The watchdog timer uses one timer and the 4-bit I/O port. The remaining two 16-bit timers are available for user tasks.

    Watchdog timer

    A watchdog timer, once activated, counts down towards zero. It must be continually monitored by software to prevent it reaching zero. If the watchdog timer does reach zero, the CIO:


    Shared storage interface chip

    The shared storage interface chip (SSTIC) is an IBM VLSI CMOS gate array of 10,000 gates. The SSTIC provides a high performance interface between the 80186 microprocessor bus and the PS/2 bus. Control bytes, and all data communications between the host system and the adapter, pass through this interface.

    The SSTIC also performs the following functions:


    PS/2 interface

    During initialization, the PS/2 and the adapter communicate via the programmable option select (POS) registers. Thereafter, the PS/2 and the adapter communicate via:

    The POS registers, and the command, status and data registers, are internal registers of the shared storage interface chip.

    Shared storage window

    The shared storage window is an area of memory that appears in the memory space of both the adapter and the PS/2.

    The window must be on the appropriate boundary in adapter memory space, but the operating system and other installed adapters with shared storage windows may impose constraints on where the window may be located in PS/2 memory space. For example, under DOS, the window can only be located between C0000h and DE000h.

    The location of the window in PS/2 memory is specified during configuration; it should not be changed afterward. However, the location of the window in adapter memory, which is initially specified during configuration, can be moved at any time by a task running on the adapter or the PS/2.

    The window size can be 8, 16, 32 or 64 KB; and is initially specified during configuration. Although not recommended, the window size can change at any time by a task running on the adapter or the PS/2. Changing the window size in this manner is not recommended because the software may assume the window size to remain the same.

    The location of the shared storage window is shown in Figure 12.

    Figure 12. Shared storage window size and location.

     PS/2 Memory                         Adapter Memory
    
    +----------+FF FFFFh           F FFFFh+----------+
    |          |\                        /|          |
    |          | \                      / |          |
    |          |  \                    /  |          |
    +----------+   \                  /   +----------+
    |        A |\   \                /   /| A        |
    |        | | \   \              /   / | |        |
    |        | |  \   \            /   /  | |        |
    |LOCREG0 | |   \   +----------+   /   | | CPUPG  |
    |and     | |    \ /| 8, 16, 32|\ /    | | locates|
    |LOCREG1 | |     \ |or 64Kb   | /     | | window |
    |locate  | |    / \|shared Win|/ \    | | in     |
    |window  | |   /   +----------+   \   | | adapter|
    |in PS/2 | |  /   /  INITREG3  \   \  | | memory |
    |memory  | | /   / selects size \   \ | |        |
    |        V |/   /    of window   \   \| V        |
    +----------+   /                  \   +----------+
    |          |  /                    \  |          |
    |          | /                      \ |          |
    |          |/                        \|          |
    +----------+00 0000h           0 0000h+----------+
    

    I/O block location

    The adapter has an I/O block of eight command, status and data registers. One of the registers is a pseudo-register allowing access to a further 12 registers.

    During configuration, this block is mapped into one of sixteen 8-byte slots in I/O space of the PS/2. If several adapters reside in the same PS/2, each must locate its I/O block in a different I/O slot in the PS/2.

    The I/O block locations are shown in Figure 13.

    Figure 13. I/O block locations.

    PS/2 I/O Space
        _   _   _
    |\_/ \_/ \_/ |
    |============|3EA0h\
    |============|3AA0h \
    |============|36A0h  \
    |============|32A0h   \
    |============|2EA0h    \
    |============|2AA0h     \
    |============|26A0h    A \
    |============|11A0h    |  +-------------------+ xxA7h
    |============|1EA0h    |  | Adapter I/O Block |
    |============|1AA0h    |  +-------------------+ xxA0h
    |============|16A0h    V /
    |============|12A0h     /      INITREG3
    |============|0EA0h    /       locates adapter
    |============|0AA0h   /        I/O block in PS/2
    |============|06A0h  /         I/O space
    |============|02A0h /
    |____________|0000h/
    

    Adapter description file

    The option diskette for the IBM X.25 Interface Co-Processor/2 contains an adapter description file (ADF). The ADF enables the user to specify the default values of:


    Communications capabilities

    The adapter provides any one of the following X.25 interfaces (see Chapter 4. X.25 Network Interface for details):

    The adapter provides direct memory access (DMA) between adapter memory and the serial communications controller (SCC) channels.

    The adapter hardware provides no specific X.25 protocol function, other than HDLC. The X.25 packet level must be provided by application software running on the adapter.


    Support functions

    The adapter provides the following support:

    This support is provided by the PROM microcode and by the RCM.

    Each co-processor can relieve its host of most of the processing requirement associated with the common serial communications protocols. Each co-processor contains:


    Other IBM communications co-processors

    The X.25 Interface Co-processor/2 is one of a family of communications co-processors. The others are:

    Note:
    The above information is dynamic. Contact an authorized IBM dealer or marketing representative for the latest list of IBM Co-Processors.

    Chapter 3. Programming Considerations

    This chapter describes the individual components of the IBM X.25 Interface Co-Processor/2, a block diagram of which is on page Figure 11. Each major component is described in terms of its function, its physical characteristics, and its special features. Programming information is provided, or referenced, for those components that are programmable.

    Publications and programs available to support programming the IBM X.25 Interface Co-Processor/2 and the related PS/2-resident code are described in "Related publications".

    Before the adapter can be programmed, the realtime control microcode (RCM), which was stored on fixed disk as ICAAIM.COM during hardware installation, must be loaded. To do this, use the instructions in either the IBM Realtime Co-Processor DOS Support, or the IBM Realtime Interface Co-Processor OS/2 Support. For further information, refer to Software Volume 1 of the IBM Realtime Interface Co-Processor, Realtime Interface Co-Processor Multiport and Realtime Interface Co-Processor Multiport/2 Technical Reference.


    Memory map

    The adapter memory map is shown in Table 1.

    Table 1. Adapter memory map

    +=========================+=========================+=========================+
    | Address                 | Size                    | Use                     |
    +=========================+=========================+=========================+
    | FC000-FFFFFh            | 16 KB                   | PROM                    |
    +-------------------------+-------------------------+-------------------------+
    | 80000-FBFFFh            | 496 KB                  | Reserved                |
    +-------------------------+-------------------------+-------------------------+
    | 00000-7FFFFh            | 512 KB                  | DRAM                    |
    +-------------------------+-------------------------+-------------------------+
    

    Programmable read-only memory

    Programmable read-only memory (PROM) contains the PROM microcode and cannot be read by tasks running on the PS/2.

    Physical characteristics

    Programmable read-only memory is provided by two 28-pin 27C64 devices. Each device provides 8 KB of storage with an access time of 250 nanoseconds.

    Power-on self-test

    Power-on self-test (POST) performs a checksum verification on PROM. A user task can also call the checksum diagnostic subroutine at any time. See "Checksum subroutine" for details.

    Dynamic random-access memory

    Functions

    The shared storage interface chip guarantees a DRAM cycle time of 300 nanoseconds. This implies a maximum data transfer rate of 6.66 Mb per second, but neither microprocessor can access DRAM at this rate. Each microprocessor holds DRAM for 300 nanoseconds before releasing it and making it available to the other microprocessor.

    Physical characteristics

    DRAM consists of two 256K x 9-bit single inline pin (SIP) packages with 120 nanosecond access time. The 512 KB of DRAM are organized as 256K 16-bit words. Each word has two parity bits, one per 8-bit byte.

    Power-on self-test

    Power-on self-test (POST) checks DRAM for size, addressability, and parity. The PROM microcode test subroutines may also be called at any time by user tasks running on the adapter. See Chapter 6. PROM Microcode Support for details.


    Adapter 80186 microprocessor

    Physical characteristics

    The main features of the 80186 microprocessor are:

    Programming considerations

    Programming of the 80186 microprocessor is described in detail in the Intel literature. This section deals with special considerations when programming the 80186 microprocessor for the IBM X.25 Interface Co-Processor/2.

    Interrupt lines

    The 80186 microprocessor has five interrupt lines; only NMI, INT0, and INT1 are used. NMI and INT0 are driven by the SSTIC. INT1 is driven by the SCC and CIO. Nonmaskable interrupts can be masked by appropriately setting the NMIMASK register in the SSTIC.

    The SSTIC issues edge-triggered interrupts on INT0 in fully nested mode. The SCC and CIO issue level-triggered interrupts on INT1 in cascade mode.

    The interrupt vectors for NMI and INT0 are provided internally by the 80186 microprocessor. The interrupt vectors for INT1 are provided by the Zilog Z8030 serial communications controller and the Zilog Z8036 counter/timer and parallel I/O unit.

    The SCC and CIO decide, via hardware, which device supplies the vector during the interrupt acknowledgement cycle. The SCC has a higher interrupt priority than the CIO.

    After a hardware interrupt, the nonspecific end-of-interrupt (EOI) command, 8000h, must be written to the EOI register to reenable interrupts. Interrupts are enabled at the same or lower priority as the previous interrupt.

    EOI is the only command a task should issue to the interrupt controller. Any other command or change could cause unpredictable results.

    Example:

    MOV  AX,08000h ;data value for nonspecific EOI
    MOV  DX,0FF22h ;I/O address of EOI register
    OUT  DX,AX     ;Issue EOI
    

    Interrupt register addresses

    The 15 interrupt controller registers are shown in Table 2.

    Table 2. Interrupt controller register model.

    +======================================+======================================+
    | Register                             | Address                              |
    +======================================+======================================+
    | INT3 control register                | FF3Eh                                |
    +--------------------------------------+--------------------------------------+
    | INT2 control register                | FF3Ch                                |
    +--------------------------------------+--------------------------------------+
    | INT1 control register                | FF3Ah                                |
    +--------------------------------------+--------------------------------------+
    | INT0 control register                | FF38h                                |
    +--------------------------------------+--------------------------------------+
    | DMA1 control register                | FF36h                                |
    +--------------------------------------+--------------------------------------+
    | DMA0 control register                | FF34h                                |
    +--------------------------------------+--------------------------------------+
    | Timer control register               | FF32h                                |
    +--------------------------------------+--------------------------------------+
    | Interrupt status register            | FF30h                                |
    +--------------------------------------+--------------------------------------+
    | Interrupt request register           | FF2Eh                                |
    +--------------------------------------+--------------------------------------+
    | In-service register                  | FF2Ch                                |
    +--------------------------------------+--------------------------------------+
    | Priority mask register               | FF2Ah                                |
    +--------------------------------------+--------------------------------------+
    | Mask register                        | FF28h                                |
    +--------------------------------------+--------------------------------------+
    | Poll status register                 | FF26h                                |
    +--------------------------------------+--------------------------------------+
    | Poll register                        | FF24h                                |
    +--------------------------------------+--------------------------------------+
    | EOI register                         | FF22h                                |
    +--------------------------------------+--------------------------------------+
    

    DMA channel allocation and registers

    The 80186 microprocessor has two integral DMA channels. The registers that control them are described in Table 3 and in the Intel literature. The adapter uses a DMA steering multiplexer to allocate the DMA channels to the four potential requesting sources:

    1. SCC port 0 transmitter (TxREQA)

    2. SCC port 1 transmitter (TxREQB)

    3. SCC port 0 receiver (RxREQA)

    4. SCC port 1 receiver (RxREQB).
    Tasks running on the adapter can write to and read from the DMA allocation logic register (IDAL). See "Internal DMA allocation logic register" for details.

    When using DMA, first enable the SCC through its WR0 register, then enable the DMA channel through the DMA control word register.

    The DMA allocation logic register (IDAL) and the 80186 microprocessor DMA registers are set by the connect DMA channel(s) PROM service subroutine (INT AAh). See "Connect DMA channel(s) subroutine" for details.

    The DMA registers for DMA channel 0 are located at FFC0h through FFCAh and for DMA channel 1 at FFD0h through FFDAh. The DMA controller registers are shown in Table 3. PROM Services subroutines can be used to program the DMA so that the DMA control registers do not have to be accessed directly.

    Table 3. DMA register addresses.

    +======================================================+==========+==========+
    | Register Name                                        | Address  | Address  |
    |                                                      | Channel 0| Channel 1|
    +======================================================+==========+==========+
    | Control word                                         | FFCAh    | FFDAh    |
    +------------------------------------------------------+----------+----------+
    | Transfer count                                       | FFC8h    | FFD8h    |
    +------------------------------------------------------+----------+----------+
    | Destination pointer (high)                           | FFC6h    | FFD6h    |
    +------------------------------------------------------+----------+----------+
    | Destination pointer (low)                            | FFC4h    | FFD4h    |
    +------------------------------------------------------+----------+----------+
    | Source pointer (high)                                | FFC2h    | FFD2h    |
    +------------------------------------------------------+----------+----------+
    | Source pointer (low)                                 | FFC0h    | FFD0h    |
    +------------------------------------------------------+----------+----------+
    

    Peripheral control block

    The 80186 microprocessor peripheral control block is set up by the power-on diagnostics. It is located in adapter I/O space at address FF00h through FFFFh. The only areas of the peripheral control block that should be modified are the DMA descriptors and interrupt controller registers described in the preceding section. Modifying any other register can cause unpredictable results.

    Memory

    PROM and DRAM do not require wait states but are programmed by the RCM to accept an external ready line controlled by the SSTIC. All peripheral devices are programmed for one wait state and to accept an external ready. The peripheral interface register addresses are shown in Table 4.

    Table 4. Peripheral interface register addresses

    +======================================+======================================+
    | Register                             | Address                              |
    +======================================+======================================+
    | UMCS                                 | FFA0h                                |
    +--------------------------------------+--------------------------------------+
    | LMCS                                 | FFA2h                                |
    +--------------------------------------+--------------------------------------+
    | PACS                                 | FFA4h                                |
    +--------------------------------------+--------------------------------------+
    | MMCS                                 | FFA6h                                |
    +--------------------------------------+--------------------------------------+
    | MPCS                                 | FFA8h                                |
    +--------------------------------------+--------------------------------------+
    

    Zilog Z8030 serial communications controller

    Functions

    The primary function of the Z8030 serial communications controller (SCC) is to provide control for the two independent serial communication channels. Each channel supports communications through the X.25 network interface. Each channel has a transmitter and a receiver and may be run in full-duplex or half-duplex mode.

    After initial configuration of the SCC by the realtime control microcode and applications software, a major portion of the serial communications work load is taken from the 80186 microprocessor and performed by the SCC.

    The SCC provides:

    The SCC is a 44-pin plastic chip carrier package and is programmed to satisfy HDLC protocol.

    SCC registers

    Sixteen 8-bit registers for each port must be programmed before the SCC can be used.

    Nine read registers (RR) for each port contain data and the status of the SCC. These are RR0 through RR3, RR8, RR10, RR12, RR13 and RR15.

    Fourteen write registers (WR) for each port are used for control. These are WR0, WR1, WR3 through WR8, and WR10 through WR15.

    Two registers, WR2 and WR9, are shared by both ports. They are set up by the RCM and should not be modified by user tasks.

    The base I/O address of the SCC is 100h.

    Write registers


    Table 5. SCC write register addresses and usage.

    +========+========+========+=================================================+
    | Regist | Offset | Offset | Function                                        |
    | er     | Port 0 | Port 1 |                                                 |
    +========+========+========+=================================================+
    | WR0    | 0020h  | 0000h  | Command register for configuring various modes. |
    +--------+--------+--------+-------------------------------------------------+
    | WR1    | 0022h  | 0002h  | Interrupt conditions to specify wait or DMA.    |
    +--------+--------+--------+-------------------------------------------------+
    | WR2    | 0024h  | 0004h  | Interrupt vector. For adapter use only. If      |
    |        |        |        | modified, results are unpredictable.            |
    +--------+--------+--------+-------------------------------------------------+
    | WR3    | 0026h  | 0006h  | Receiver parameters. These are task controlled. |
    +--------+--------+--------+-------------------------------------------------+
    | WR4    | 0028h  | 0008h  | Transmit/receive parameters.                    |
    +--------+--------+--------+-------------------------------------------------+
    | WR5    | 002Ah  | 000Ah  | Transmit parameters.                            |
    +--------+--------+--------+-------------------------------------------------+
    | WR6    | 002Ch  | 000Ch  | Sync character 1.                               |
    +--------+--------+--------+-------------------------------------------------+
    | WR7    | 002Eh  | 000Eh  | Sync character 2.                               |
    +--------+--------+--------+-------------------------------------------------+
    | WR8    | 0030h  | 0010h  | Transmit data buffer.                           |
    +--------+--------+--------+-------------------------------------------------+
    | WR9    | 0032h  | 0012h  | Master control/reset interrupt. For adapter use |
    |        |        |        | only. This register should never be modified by |
    |        |        |        | a task.                                         |
    +--------+--------+--------+-------------------------------------------------+
    | WR10   | 0034h  | 0014h  | Miscellaneous transmit/receive control bits.    |
    +--------+--------+--------+-------------------------------------------------+
    | WR11   | 0036h  | 0016h  | Clock mode control. Bit 7 (no crystal) should   |
    |        |        |        | always be set to zero because no crystal is     |
    |        |        |        | connected to the receiver clock input.          |
    +--------+--------+--------+-------------------------------------------------+
    | WR12   | 0038h  | 0018h  | Time constant low.                              |
    +--------+--------+--------+-------------------------------------------------+
    | WR13   | 003Ah  | 001Ah  | Time constant high.                             |
    +--------+--------+--------+-------------------------------------------------+
    | WR14   | 003Ch  | 001Ch  | Miscellaneous control bits. Bit 2 is transmit   |
    |        |        |        | DMA request.                                    |
    +--------+--------+--------+-------------------------------------------------+
    | WR15   | 003Eh  | 001Eh  | External status control.                        |
    +--------+--------+--------+-------------------------------------------------+
    

    Read registers

    Table 6. SCC read register addresses and usage.

    +========+========+========+=================================================+
    | Regist | Offset | Offset | Function                                        |
    | er     | Port 0 | Port 1 |                                                 |
    +========+========+========+=================================================+
    | RR0    | 0020h  | 0000h  | Transmit/receive and external status.           |
    +--------+--------+--------+-------------------------------------------------+
    | RR1    | 0022h  | 0002h  | Special receive status.                         |
    +--------+--------+--------+-------------------------------------------------+
    | RR2    | 0024h  | 0004h  | Interrupt vector.                               |
    +--------+--------+--------+-------------------------------------------------+
    | RR3    | 0026h  | -      | Ports 0 and 1 Interrupt pending bits.           |
    +--------+--------+--------+-------------------------------------------------+
    | RR8    | 0030h  | 0010h  | Receive data buffer.                            |
    +--------+--------+--------+-------------------------------------------------+
    | RR10   | 0034h  | 0014h  | Miscellaneous status and parameters.            |
    +--------+--------+--------+-------------------------------------------------+
    | RR12   | 0038h  | 0018h  | Time constant low.                              |
    +--------+--------+--------+-------------------------------------------------+
    | RR13   | 003Ah  | 001Ah  | Time constant high.                             |
    +--------+--------+--------+-------------------------------------------------+
    | RR15   | 003Eh  | 001Eh  | External status control information.            |
    +--------+--------+--------+-------------------------------------------------+
    

    Programming the SCC

    The PROM microcode provides several support subroutines to simplify programming the SCC. Descriptions of these routines may be found in "Diagnostic subroutines".

    Diagnostic subroutine support

    Table 7. Diagnostic subroutines

    +=========+============+=====================================================+
    | INT     | Parms      | Function                                            |
    +=========+============+=====================================================+
    | FEh     | AH=09h     | Reset an SCC port to default configuration.         |
    +---------+------------+-----------------------------------------------------+
    

    PROM services

    Table 8. PROM services

    +=========+============+=====================================================+
    | INT     | Parms      | Function                                            |
    +=========+============+=====================================================+
    | A2h     |            | Reset an SCC port to the hardware default           |
    |         |            | configuration.                                      |
    +---------+------------+-----------------------------------------------------+
    | A4h     |            | General SCC register read/write.                    |
    +---------+------------+-----------------------------------------------------+
    | AAh     |            | Assign the two 80186 microprocessor DMA channels to |
    |         |            | two of the four SCC DMA requests.                   |
    +---------+------------+-----------------------------------------------------+
    | ACh     |            | Configure and initialize DMA transfer types (I/O to |
    |         |            | memory and so on).                                  |
    +---------+------------+-----------------------------------------------------+
    | AEh     |            | Read or write a 12-byte table to define DMA         |
    |         |            | transfer source, destination, and byte count.       |
    +---------+------------+-----------------------------------------------------+
    | B0h     |            | Stop DMA transfer.                                  |
    +---------+------------+-----------------------------------------------------+
    

    Programming considerations

    Consult the Zilog literature when programming the Z8030 SCC. The following are some notes on programming the SCC on the adapter:


    Zilog Z8036 counter/timer and parallel I/O unit

    Functions

    The Zilog Z8036 counter/timer and parallel I/O unit (CIO) is a fully programmable device that provides peripheral I/O support and timer functions for hardware and software. Some features of the Z8036 CIO are:

    The adapter uses the CIO as follows:

    CIO registers

    The main CIO registers are dedicated for use by RCM only and should not be directly written to by applications. The base I/O address of the CIO is 0180h.

    Bit definitions for each register are described in the Zilog Z8036 CIO Counter/Timer and Parallel I/O Unit Technical Manual.

    Table 9. CIO main control registers

    +========+========+==========================================================+
    | Offset | Access | Function                                                 |
    +========+========+==========================================================+
    | 0000h  | R/W    | Master interrupt control register.                       |
    +--------+--------+----------------------------------------------------------+
    | 0002h  | R/W    | Master configuration control register.                   |
    +--------+--------+----------------------------------------------------------+
    | 0004h  | R/W    | Port 0 interrupt vector.                                 |
    +--------+--------+----------------------------------------------------------+
    | 0006h  | R/W    | Port 1 interrupt vector.                                 |
    +--------+--------+----------------------------------------------------------+
    | 0008h  | R/W    | Counter/timer interrupt vector.                          |
    +--------+--------+----------------------------------------------------------+
    | 000Ah  | R/W    | Port 2 data path polarity register.                      |
    +--------+--------+----------------------------------------------------------+
    | 000Ch  | R/W    | Port 2 data direction register.                          |
    +--------+--------+----------------------------------------------------------+
    | 000Eh  | R/W    | Port 2 special I/O control register.                     |
    +--------+--------+----------------------------------------------------------+
    
    Table 10. Frequently accessed registers of the CIO
    +========+========+==========================================================+
    | Offset | Access | Function                                                 |
    +========+========+==========================================================+
    | 0010h  | R/W    | Port 0 command and status.                               |
    +--------+--------+----------------------------------------------------------+
    | 0012h  | R/W    | Port 1 command and status.                               |
    +--------+--------+----------------------------------------------------------+
    | 0014h  | R/W    | Counter/timer 1 command and status.                      |
    +--------+--------+----------------------------------------------------------+
    | 0016h  | R/W    | Counter/timer 2 command and status.                      |
    +--------+--------+----------------------------------------------------------+
    | 0018h  | R/W    | Timer 3 command and status.                              |
    +--------+--------+----------------------------------------------------------+
    | 001Ah  | R/W    | Port 0 data register.                                    |
    +--------+--------+----------------------------------------------------------+
    | 001Ch  | R/W    | Port 1 data register.                                    |
    +--------+--------+----------------------------------------------------------+
    | 001Eh  | R/W    | Port 2 data register.                                    |
    +--------+--------+----------------------------------------------------------+
    
    Table 11. CIO counter/timer registers.
    +========+========+==========================================================+
    | Offset | Access | Function                                                 |
    +========+========+==========================================================+
    | 0020h  | R      | Counter/timer 1 current count MSB.                       |
    +--------+--------+----------------------------------------------------------+
    | 0022h  | R      | Counter/timer 1 current count LSB.                       |
    +--------+--------+----------------------------------------------------------+
    | 0024h  | R      | Counter/timer 2 current count MSB.                       |
    +--------+--------+----------------------------------------------------------+
    | 0026h  | R      | Counter/timer 2 current count LSB.                       |
    +--------+--------+----------------------------------------------------------+
    | 0028h  | R      | Counter/timer 3 current count MSB.                       |
    +--------+--------+----------------------------------------------------------+
    | 002Ah  | R      | Counter/timer 3 current count LSB.                       |
    +--------+--------+----------------------------------------------------------+
    | 002Ch  | R/W    | Counter/timer 1 time constant MSB.                       |
    +--------+--------+----------------------------------------------------------+
    | 002Eh  | R/W    | Counter/timer 1 time constant LSB.                       |
    +--------+--------+----------------------------------------------------------+
    | 0030h  | R/W    | Counter/timer 2 time constant MSB.                       |
    +--------+--------+----------------------------------------------------------+
    | 0032h  | R/W    | Counter/timer 2 time constant LSB.                       |
    +--------+--------+----------------------------------------------------------+
    | 0034h  | R/W    | Counter/timer 3 time constant MSB.                       |
    +--------+--------+----------------------------------------------------------+
    | 0036h  | R/W    | Counter/timer 3 time constant LSB.                       |
    +--------+--------+----------------------------------------------------------+
    | 0038h  | R/W    | Counter/timer 1 mode specification.                      |
    +--------+--------+----------------------------------------------------------+
    | 003Ah  | R/W    | Counter/timer 2 mode specification.                      |
    +--------+--------+----------------------------------------------------------+
    | 003Ch  | R/W    | Counter/timer 3 mode specification.                      |
    +--------+--------+----------------------------------------------------------+
    | 003Eh  | R/W    | Current vector.                                          |
    +--------+--------+----------------------------------------------------------+
    
    Table 12. CIO port 0 specification registers.
    +========+========+==========================================================+
    | Offset | Access | Function                                                 |
    +========+========+==========================================================+
    | 00040h | R/W    | Port 0 mode specification. Bits 3-7 must be zeros to     |
    |        |        | keep the port specified as a bit port. The deskew timer  |
    |        |        | function is not supported. Bit 0 is latched on pattern   |
    |        |        | match.                                                   |
    +--------+--------+----------------------------------------------------------+
    | 00042h | R/W    | Port 0 handshake specification. (This register is always |
    |        |        | zero because handshaking is not used.)                   |
    +--------+--------+----------------------------------------------------------+
    | 00044h | R/W    | Port 0 data path polarity.                               |
    +--------+--------+----------------------------------------------------------+
    | 00046h | R/W    | Port 0 data direction.                                   |
    +--------+--------+----------------------------------------------------------+
    | 00048h | R/W    | Port 0 special I/O control.                              |
    +--------+--------+----------------------------------------------------------+
    | 0004Ah | R/W    | Port 0 pattern polarity.                                 |
    +--------+--------+----------------------------------------------------------+
    | 0004Ch | R/W    | Port 0 pattern transition.                               |
    +--------+--------+----------------------------------------------------------+
    | 0004Eh | R/W    | Port 0 pattern mask (which bits to test).                |
    +--------+--------+----------------------------------------------------------+
    
    Table 13. CIO Port 1 specification registers.
    +========+========+==========================================================+
    | Offset | Access | Function                                                 |
    +========+========+==========================================================+
    | 00050h | R/W    | Port 1 mode specification.                               |
    +--------+--------+----------------------------------------------------------+
    | 00052h | R/W    | Port 1 handshake specification.                          |
    +--------+--------+----------------------------------------------------------+
    | 00054h | R/W    | Port 1 data path polarity.                               |
    +--------+--------+----------------------------------------------------------+
    | 00056h | R/W    | Port 1 data direction.                                   |
    +--------+--------+----------------------------------------------------------+
    | 00058h | R/W    | Port 1 special I/O control.                              |
    +--------+--------+----------------------------------------------------------+
    | 0005Ah | R/W    | Port 1 pattern polarity.                                 |
    +--------+--------+----------------------------------------------------------+
    | 0005Ch | R/W    | Port 1 pattern transition.                               |
    +--------+--------+----------------------------------------------------------+
    | 0005Eh | R/W    | Port 1 pattern mask.                                     |
    +--------+--------+----------------------------------------------------------+
    

    Programming the CIO

    The PROM microcode provides several support subroutines to simplify programming the CIO. Descriptions of these routines may be found in "Diagnostic subroutines".

    Diagnostic subroutines

    Table 14. Diagnostic subroutines

    +=========+============+=====================================================+
    | INT     | Parameter  | Function                                            |
    +=========+============+=====================================================+
    | FEh     | AH=08h     | Initialize a CIO port.                              |
    +---------+------------+-----------------------------------------------------+
    | FEh     | AH=0Bh     | Initialize a CIO timer.                             |
    +---------+------------+-----------------------------------------------------+
    

    PROM services

    Table 15. PROM services
    +=========+============+=====================================================+
    | INT     | Parameter  | Function                                            |
    +=========+============+=====================================================+
    | A6h     |            | Read/write CIO port registers.                      |
    +---------+------------+-----------------------------------------------------+
    | A8h     |            | Timer1 and timer2 control.                          |
    +---------+------------+-----------------------------------------------------+
    

    Programming considerations

    The Zilog literature should be consulted when programming the Z8036 CIO. The following are some notes on programming the CIO on the adapter:

    CIO port assignments and description

    One port and one timer of the CIO are used by the watchdog timer to provide interrupt notification of a runaway CPU. The remaining ports of the CIO are used for the interfaces. Port 0 is used for the X.21 bis/V.24 Interface and the X.21 bis/V.35. Port 1 is used for the X.21 Interface, and port 2 is used for the selection of V.24 or V.35 Interface, as well as the watchdog timer. The following tables show the bit assignments for the CIO: Table 16. CIO bit assignments

    +==========+======+=============================+=============================+
    | Port 0   | Pin  | Signal                      | Description                 |
    |          | No.  |                             |                             |
    +==========+======+=============================+=============================+
    | P0-0     | 37   | DSR                         | Data set ready              |
    +----------+------+-----------------------------+-----------------------------+
    | P0-1     | 36   | Unused                      |                             |
    +----------+------+-----------------------------+-----------------------------+
    | P0-2     | 35   | LLBT                        | Local loopback test         |
    +----------+------+-----------------------------+-----------------------------+
    | P0-3     | 34   | RLBT                        | Remote loopback test        |
    +----------+------+-----------------------------+-----------------------------+
    | P0-4     | 33   | CI                          | Call indicate               |
    +----------+------+-----------------------------+-----------------------------+
    | P0-5     | 32   | TI                          | Test indicate               |
    +----------+------+-----------------------------+-----------------------------+
    | P0-6     | 31   | DTR                         | Data terminal ready         |
    +----------+------+-----------------------------+-----------------------------+
    | P0-7     | 30   | Unused                      |                             |
    +----------+------+-----------------------------+-----------------------------+
    
    Table 17. CIO bit assignments (cont.)
    +==========+======+=============================+=============================+
    | Port 1   | Pin  | Signal                      | Description                 |
    |          | No.  |                             |                             |
    +==========+======+=============================+=============================+
    | P1-0     | 10   | IND                         | Indicate                    |
    +----------+------+-----------------------------+-----------------------------+
    | P1-1     | 11   | CABLE-0                     | Cable ID 0                  |
    +----------+------+-----------------------------+-----------------------------+
    | P1-2     | 12   | CABLE-1                     | Cable ID 1                  |
    +----------+------+-----------------------------+-----------------------------+
    | P1-3     | 13   | RXD 1                       | Receive data                |
    +----------+------+-----------------------------+-----------------------------+
    | P1-4     | 14   | SYNC 1                      | Transmit clock 1            |
    +----------+------+-----------------------------+-----------------------------+
    | P1-5     | 15   | RXTXC 1                     | Receive clock 1             |
    +----------+------+-----------------------------+-----------------------------+
    | P1-6     | 16   | CTRL 1                      | Control                     |
    +----------+------+-----------------------------+-----------------------------+
    | P1-7     | 17   | X.21 Tx                     | X.21 transmit enable        |
    +----------+------+-----------------------------+-----------------------------+
    
    The bit assignments for port 2 are shown in the following watchdog timer section.

    Watchdog timer

    The watchdog timer detects runaway tasks. Once activated, the timer must be continually monitored by software to prevent it timing out. If a task running on the adapter has an unrecoverable error, the watchdog timer times out, and the CIO:

    Table 18. LED operation
    +========+=================================+=================================+
    | P2-2   | P2-0                            | LED                             |
    +========+=================================+=================================+
    | 0      | 0                               | On                              |
    +--------+---------------------------------+---------------------------------+
    | 0      | 1                               | On                              |
    +--------+---------------------------------+---------------------------------+
    | 1      | 0                               | Off                             |
    +--------+---------------------------------+---------------------------------+
    | 1      | 1                               | On                              |
    +--------+---------------------------------+---------------------------------+
    
    The range of the watchdog timer is from 1.1 milliseconds to 72.81659 seconds with a step size of 1.1 milliseconds.

    Timer 3 in the CIO is used as the watchdog timer and its operation is shown in Figure 14. If the watchdog timer is never initialized, the LED remains lit.

    Table 19. Watchdog timer description

    +============+======+============================+============================+
    | Port 2     | Pin  | Signal                     | Description                |
    | (See Note) | No.  |                            |                            |
    +============+======+============================+============================+
    | P2-0       | 19   | WDOG                       | Timer 3 out, watchdog.     |
    +------------+------+----------------------------+----------------------------+
    | P2-1       | 20   | T3CLK                      | Timer 3 clock input 900 Hz.|
    +------------+------+----------------------------+----------------------------+
    | P2-2       | 21   | WD CNTL                    | Watchdog LED control.      |
    +------------+------+----------------------------+----------------------------+
    | P2-3       | 22   | V.24/V.35                  | Selection of V.24 or V.35  |
    |            |      |                            | interface                  |
    +------------+------+----------------------------+----------------------------+
    
    Note:
    Port 2 on the CIO can be programmed by the user.

    Figure 14. Block diagram of the watchdog timer.

                                Vcc
           +-------------+       O
           |             |       |
           | 8036  C10   |    +-----+
           | TIMER       |    |     |
           |             |    |  R  |
           |             |    |     |
           |             |    +--+--+   +-----+   +-----------+
           |             |       |      |     |   |           |   +-----+
           |        P2-0 +-------+------+ INV +---+    AND    |   |     |
           |             |              |     |   |           +---+ LED |
           |             |              +-----+   |           |   |     |
    CLK ---+ P2-1   P2-2 +------------------------+           |   +-----+
           |             |                        |           |
           +-------------+                        +-----------+
    

    Hardware resource allocation

    The following tables show how the various hardware resources are allocated.

    80186 microprocessor interrupts

    Table 20. 80186 microprocessor interrupts.

    +============+=======+=======================================================+
    | Signal     | Pin   | Assignment                                            |
    |            | No.   |                                                       |
    +============+=======+=======================================================+
    | NMI        | 46    | Parity error, watchdog, NMI command, lost refresh,    |
    |            |       | parity channel check, Ctrl-Alt-Del.                   |
    +------------+-------+-------------------------------------------------------+
    | INT0       | 45    | SSTIC                                                 |
    +------------+-------+-------------------------------------------------------+
    | INT1       | 44    | SCC and CIO                                           |
    +------------+-------+-------------------------------------------------------+
    | INT2       | 42    | Reserved                                              |
    +------------+-------+-------------------------------------------------------+
    | INT3       | 41    | Interrupt acknowledge for SCC and CIO.                |
    +------------+-------+-------------------------------------------------------+
    

    80186 microprocessor timer/counters

    Table 21. 80186 microprocessor counter/timers.

    +============+=======+=======================================================+
    | Signal     | Pin   | Assignment                                            |
    |            | No.   |                                                       |
    +============+=======+=======================================================+
    | TIMER0     | 20    | For RCM use, offset 50h-56h.                          |
    +------------+-------+-------------------------------------------------------+
    | TIMER1     | 21    | For RCM use, offset 58h-5Eh.                          |
    +------------+-------+-------------------------------------------------------+
    | TIMER2     | -     | For RCM use, offset 60h-66h.                          |
    +------------+-------+-------------------------------------------------------+
    

    80186 microprocessor DMA channels

    Table 22. 80186 microprocessor DMA channels.

    +============+=======+=======================================================+
    | Signal     | Pin   | Assignment                                            |
    |            | No.   |                                                       |
    +============+=======+=======================================================+
    | DRQ0       | 18    | Allocated by user task running on adapter, offset     |
    |            |       | C0-CAh.                                               |
    +------------+-------+-------------------------------------------------------+
    | DRQ1       | 19    | Allocated by user task running on adapter, offset     |
    |            |       | D0-DAh.                                               |
    +------------+-------+-------------------------------------------------------+
    

    Z8036 CIO timers

    Table 23. Z8036 CIO timers.

    +============+=======+=======================================================+
    | Signal     | Pin   | Assignment                                            |
    |            | No.   |                                                       |
    +============+=======+=======================================================+
    | TIMER1     | 14    | Available for user tasks via RCM                      |
    +------------+-------+-------------------------------------------------------+
    | TIMER2     | 10    | Available for user tasks via RCM                      |
    +------------+-------+-------------------------------------------------------+
    | TIMER3     | 21    | Watchdog.                                             |
    +------------+-------+-------------------------------------------------------+
    

    Shared storage interface chip

    DRAM access

    The SSTIC arbitration unit ensures that DRAM is continually refreshed, and selects which microprocessor has access to DRAM.

    Arbitration

    All control, data, and address lines from the PS/2 microprocessor, the 80186 microprocessor, and DRAM are inputs to the SSTIC. The microprocessor signals are used to initiate memory cycles. After the arbitration unit has selected a microprocessor, the appropriate DRAM signals are generated and a memory cycle is started. The arbitration unit then deselects the current microprocessor and selects the other microprocessor, if it is waiting to use DRAM. Whenever DRAM is needed by both microprocessors, one is selected and the other is held in a wait state. (A wait state is an integral number of 80186 microprocessor clock cycles.) Arbitration is achieved by sampling each microprocessor's request at different times with a 25 Mhz clock. The SSTIC inserts wait states for DRAM.

    The PS/2 microprocessor cannot access PROM, therefore no access contention occurs in this portion of memory, and no wait states are generated.

    PS/2 microprocessor requests are generated from a valid address (an address in the current PS/2 window) and memory read or write. 80186 microprocessor requests are generated from the status lines (S0, S1, S2) when they indicate a memory cycle or instruction fetch.

    The 80186 microprocessor should be programmed to accept the external ready signal for all its memory space.

    Performance considerations

    Transparent to both microprocessors, the SSTIC terminates all memory cycles early, and makes DRAM available for another access. For a memory read cycle, data is latched and made available to the microprocessor until the cycle is finished. For a memory write in which a microprocessor provides the data, no further interaction with the microprocessor is needed once the DRAM write cycle has completed.

    In both cases the SSTIC can internally terminate the present cycle and allow the other microprocessor to access DRAM. This increases the usage (bandwidth) of DRAM.

    Performance of the SSTIC can be measured in terms of DRAM availability (or access time) to the microprocessors. DRAM access times are shown in Table 24.

    Table 24. DRAM access times

    +============+============+============+============+============+============+
    | Device     | Clock      | Access     | Data Width | Typical    | Max.       |
    +============+============+============+============+============+============+
    | DRAM       | 3.33 Mhz   | R/W        | 8-16 bits  | 300ns      | 300ns      |
    +------------+------------+------------+------------+------------+------------+
    | adapter    | 7.37 Mhz   | R/W        | 8-16 bits  | 543ns      | 814ns      |
    +------------+------------+------------+------------+------------+------------+
    | PS/2       | 10 Mhz     | R/W        | 8 16 bits  | 500ns      | 1200ns     |
    +------------+------------+------------+------------+------------+------------+
    
    The DRAM cycle is 300 nanoseconds, therefore data can be accessed at a maximum of 6.66 Mb per second.

    Memory refresh

    The SSTIC can be programmed to refresh DRAM every 7.6 or 15.2 microseconds. The SSTIC also monitors the PS/2 DRAM. If the PS/2 fails to refresh its DRAM for 15.56 milliseconds, the PS/2 bus is disconnected (degated) from the adapter DRAM, and an NMI is raised to the 80186 microprocessor (unless masked in NMIMASK). If the PS/2 recommences to refresh its DRAM, the PS/2 bus is gated to the adapter DRAM again.

    To minimize contention between PS/2 microprocessor access to adapter DRAM, and adapter DRAM refresh, the SSTIC monitors the PS/2 bus activity. The SSTIC attempts to place refresh requests with non-DRAM bus cycles on the 80186 microprocessor. This is performed transparently and the adapter DRAM access time is not affected. That is, no more than two wait states are inserted into the 80186 microprocessor memory cycles.

    The adapter and PS/2 microprocessors perform differently under various conditions. The following examples show the best-case and the worst-case wait states that can be expected.

    Device   Normal  Additional    Total Cycle
    (No Contention)  Wait States   Wait States (Min)  Time (Min)
    ================================================================
    adapter           0             0                  542.5
    80286 PS/2        0             3 or 4             500-600
    80386 PS/2        0             3 or 4             500-600
    
    
    Device   Normal  Additional    Total Cycle
    (No Contention)  Wait States   Wait States (Max)  Time (Max)
    ================================================================
    adapter           0             2                  813.8
    80286 PS/2        0             9                  1100.0
    80386 PS/2        0             9                  1100.0
    
    The shared storage interface chip is designed to provide maximum data throughput using a minimum amount of software on the PS/2. Minimal synchronous operation is required between the PS/2 and the adapter. This asynchronous interface allows PS/2 applications to communicate directly with applications on the adapter through shared storage space.

    Programming considerations

    The adapter uses two types of interrupts. The SCC and CIO interrupt the 80186 microprocessor in cascade mode on INT1. The SSTIC interrupts on INT0 in fully nested mode. INT0 is programmed to be edge-triggered and INT1 is programmed to be level-triggered. INT0 and INT1 should not be reprogrammed.

    SSTIC registers are set up by:

    POST determines the amount of memory on the adapter and programs the SSTIC accordingly. There are no option jumpers or switches.

    For correct operation, the SSTIC must be programmed in a specific sequence:

    All registers are described in "SSTIC register descriptions".

    DRAM integrity cannot be guaranteed for 0.5 seconds after power-on. A half-second loop in PROM microcode prevents access during this time.

    Reset

    IBM Personal System/2 (PS/2) computers have three types of reset:

    1. Power-on reset. This occurs anytime the +5 V supply is interrupted.

    2. Channel reset. This occurs anytime the channel reset signal goes active.

    3. Command reset. This is a PS/2 software command that causes a channel reset.
    Because the adapter is an intelligent device that can handle more critical devices than a PS/2 would normally handle, a channel reset should not be allowed to affect operation of the 80186 microprocessor.

    The effect of a channel reset and a power-on reset is shown in Table 25.

    Table 25. SSTIC reset conditions

    +======================================================+==========+==========+
    | Condition                                            | Channel  | Power-on |
    |                                                      | Reset    | Reset    |
    +======================================================+==========+==========+
    | Degate adapter DRAM from PS/2 bus                    | X        | X        |
    +------------------------------------------------------+----------+----------+
    | Put adapter in "sleep" mode.                         | X        | X        |
    +------------------------------------------------------+----------+----------+
    | Clear parity circuits.                               | X        | X        |
    +------------------------------------------------------+----------+----------+
    | Disable Ctrl-Alt-Del feature                         |          | X        |
    +------------------------------------------------------+----------+----------+
    | Clear internal refresh counters and circuits         |          | X        |
    +------------------------------------------------------+----------+----------+
    | Clear internal interrupt circuits                    |          | X        |
    +------------------------------------------------------+----------+----------+
    | Clear external interrupt circuits                    | X        | X        |
    +------------------------------------------------------+----------+----------+
    
    The effects on each register of a power-on reset and of a command reset are described in "SSTIC register descriptions". The effects of a hardware channel reset are few and are noted appropriately.

    SSTIC register summary

    SSTIC registers control communication between the adapter and the PS/2. All registers are 8-bit read and/or write unless otherwise stated.

    The function of each register is as follows:

    COMREG
    Issues commands from the PS/2 to reset, interrupt, and control the adapter.

    CAD0-CAD2
    Detect a keyboard Ctrl-Alt-Del sequence.

    CPUPG
    Contains the location of the shared storage window in adapter DRAM.

    CRDIDU, CRDIDL
    Contain an ID that identifies the adapter to the PS/2.

    DREG
    Allows access to various registers pointed to by PTRREG.

    GAID
    Identifies the version of SSTIC installed.

    IDAL
    Allocates the DMA channels to the SCC ports.

    INITREG0-INITREG3
    Initialize the SSTIC, set adapter-PS/2 interrupt level, set size of shared storage window and locate adapter I/O block.

    LOCREG0, LOCREG1
    Contain the location of the shared storage windows in PS/2 memory space.

    NMIMASK
    Masks one, or all, of the possible causes of an NMI to the 80186 microprocessor.

    NMISTAT
    Reports the status of all possible causes of an NMI.

    PS/2PAR0-PS/2PAR2
    Stores the equivalent PS/2 address (in the shared storage window) at which a parity error occurred during a read access to adapter DRAM.

    PTRREG
    Points to registers that can be accessed through the pseudo-register, DREG.

    RICPAR0-RICPAR2
    Stores the adapter address (in the shared storage window) at which a parity error occurred during a read access to adapter DRAM.

    TREG
    Passes interrupts to the PS/2, and data between the adapter and the PS/2.

    GEOI
    Clears the internal interrupt circuitry of the SSTIC after INTCOM is accessed by the PS/2.

    INTCOM
    Allows the PS/2 to interrupt and pass a command to the adapter.
    The I/O addresses of each register are shown in Table 26.

    Table 26. SSTIC register addresses in I/O space

    +================+===============+===============+===============+============+
    | Register       | POS Address   | PS/2 Address  | Adapter       | Power-Up   |
    |                |               |               | Address       | Value      |
    +================+===============+===============+===============+============+
    | COMREG         | -             | 06h           | -             | 0000 0000  |
    +----------------+---------------+---------------+---------------+------------+
    | CAD0           | -             | (0Ch)         | -             | 0000 0000  |
    +----------------+---------------+---------------+---------------+------------+
    | CAD1           | -             | (0Dh)         | -             | 0000 0000  |
    +----------------+---------------+---------------+---------------+------------+
    | CAD2           | -             | (0Eh)         | -             | 0000 0000  |
    +----------------+---------------+---------------+---------------+------------+
    | CPUPG          | -             | 05h           | 14h           | uuuu uuuu  |
    +----------------+---------------+---------------+---------------+------------+
    | CRDIDL         | 00h           | -             | -             | 1111 0000  |
    +----------------+---------------+---------------+---------------+------------+
    | CRDIDU         | 01h           | -             | -             | 1110 1111  |
    +----------------+---------------+---------------+---------------+------------+
    | DREG           | -             | 03h           | -             | uuuu uuuu  |
    +----------------+---------------+---------------+---------------+------------+
    | GAID           | -             | (0Fh)         | 18h           | 1100 0000  |
    +----------------+---------------+---------------+---------------+------------+
    | IDAL           | -             | -             | 84h           | 0000 0000  |
    +----------------+---------------+---------------+---------------+------------+
    | INITREG0       | 02h           | (12h)         | 04h           | 0000 1000  |
    +----------------+---------------+---------------+---------------+------------+
    | INITREG1       | -             | (10h)         | 06h           | 0000 0000  |
    +----------------+---------------+---------------+---------------+------------+
    | INITREG2       | -             | (08h)         | -             | 0000 0000  |
    +----------------+---------------+---------------+---------------+------------+
    | INITREG3       | 05h           | (13h)         | 1Ah           | 0000 0000  |
    +----------------+---------------+---------------+---------------+------------+
    | LOCREG0        | 03h           | 00h           | 00h           | uuuu uuuu  |
    +----------------+---------------+---------------+---------------+------------+
    | LOCREG1        | 04h           | 01h           | 02h           | uuuu uuuu  |
    +----------------+---------------+---------------+---------------+------------+
    | NMIMASK        | -             | -             | 08h           | 0011 1111  |
    +----------------+---------------+---------------+---------------+------------+
    | NMISTAT        | -             | -             | 0Ah           | 0000 0000  |
    +----------------+---------------+---------------+---------------+------------+
    | PS/2PAR0       | -             | (0Ah)         | -             | 0000 0000  |
    +----------------+---------------+---------------+---------------+------------+
    | PS/2PAR1       | -             | (0Bh)         | -             | 0000 0000  |
    +----------------+---------------+---------------+---------------+------------+
    | PS/2PAR2       | 05h           | (11h)         | -             | 0000 0001  |
    +----------------+---------------+---------------+---------------+------------+
    | PTRREG         | -             | 02h           | -             | uuuu uuuu  |
    +----------------+---------------+---------------+---------------+------------+
    | RICPAR0        | -             | -             | 0Ch           | 0000 0000  |
    +----------------+---------------+---------------+---------------+------------+
    | RICPAR1        | -             | -             | 0Eh           | 0000 0000  |
    +----------------+---------------+---------------+---------------+------------+
    | RICPAR2        | -             | -             | 10h           | 0000 0000  |
    +----------------+---------------+---------------+---------------+------------+
    | TREG           | -             | 04h           | 12h           | 1111 1111  |
    +----------------+---------------+---------------+---------------+------------+
    | GEOI (2)       | -             | -             | 16h           | N/A        |
    +----------------+---------------+---------------+---------------+------------+
    | INTCOM         | -             | (09h)         | -             | N/A        |
    +----------------+---------------+---------------+---------------+------------+
    
    Notes:
    1. POS address offsets are further encoded with a valid "Carden" signal on the PS/2 bus.

    2. Values given in parentheses are pointer register values. All other values are offsets and should be added to the base address value programmed in INITREG0.

    3. Default power-up values are not applicable.

    4. 0=logical level 0.

    5. 1=logical level 1.

    6. u=undefined.

    Memory mapping

    Adapter memory and I/O space can be relocated in PS/2 memory and I/O space by programming the SSTIC registers. The memory relocation is shown in Figure 12 and the I/O block relocation is shown in Figure 13.

    Relocation and paging

    Tasks running on the PS/2 can access the adapter storage window only on 8, 16, 32, or 64 KB boundaries depending on window size. The window size and location in adapter DRAM is programmable. Adapter memory may be mapped into PS/2 memory space on any boundary equal to the size of the window.

    I/O block location

    The adapter I/O block must be located in one of 16 blocks of eight I/O addresses.

    Adapter description file

    Function

    The adapter description file (ADF) controls the programmable option select (POS) registers. During setup the POS registers set the initial values of:

    POS registers

    The adapter has four registers that support POS in the PS/2. These registers contain three bits that are set by the PS/2 and 27 bits that are set by the user. (All of these bits must be initialized for correct operation.) How these registers relate to the SSTIC registers is described below.

    Figure 15. PS/2 POS register definitions

      +--+--+--+--+--+--+--+--+
      |D7|D6|D5|D4|D3|D2|D1|D0|
      +-++-++-++-++-++-++-++-++
        |  |  |  |  |  |  |  |   POS0 POS1 POS2 POS3 POS4      POS5    POS6  POS7
        |  |  |  |  |  |  |  |
        |  |  |  |  |  |  |  +--- 0    1    SE  A13  A20        W1     NOT   NOT
        |  |  |  |  |  |  +------ 0    1    L1  A14  A21        W2     USED  USED
        |  |  |  |  |  +--------- 0    1    L2  A15  A22        W4
        |  |  |  |  +------------ 0    1    L4  A16  A23        DPLL/321
        |  |  |  +--------------- 1    0    C1  A17  DPLL/320   Local 1
        |  |  +------------------ 1    1    C2  A18  Local 0    DCE/DTE
        |  +--------------------- 1    1    C4  A19  DCE/DTE 0  CKS
        +------------------------ 1    1    C8  00   00         NCKI
    
    POS0 and POS1

    POS0 and POS1 contain the adapter ID, EFF0h. The PS/2 automatic-configuration program uses this ID to identify that an IBM X.25 Interface Co-Processor/2 is installed. These bits are not controlled by the adapter description file.

    POS2

    POS2 is identical to INITREG0, but bits D0-3 are rotated to accommodate SE, which is implemented at bit D0.

    Sleep Enable (SE): When clear, this bit disables the adapter from the PS/2 bus. It is cleared on a channel reset. This bit is normally only used by the automatic-configuration program.

    Interrupt Level (L1, L2, L4): These bits define the level at which the adapter interrupts the PS/2.

    I/O block location (C1, C2, C4, C8): These bits define the base address in PS/2 I/O space at which the adapter I/O block is to be located. If more than one adapter is resident in the PS/2, each adapter must have a different address.

    POS3

    POS3 is identical to LOCREG0. Bit D7 must be 0.

    Address Bits (A13 through A19): These bits locate the shared storage window in PS/2 memory, as follows:

    Any values programmed into the unused bits are ignored; they should be programmed to 0.

    Note: If the window size is changed, the user task must keep track of where the boundary of the window has been moved. For example, if the window is initially 8 KB at PS/2 segment C200h (page 61h) and its size is changed to 16 KB, the boundary is moved to PS/2 segment C000h (page 60h).

    POS4

    Bits D0 through D3: Identical to LOCREG1.

    Clocking options Port 0 (DPLL/32, Local, DCE/DTE)

    These bits configure the clocking options for Port 0 of the SCC. The Transmit clock source is determined by the DCE/DTE bit. The co-processor can be configured to provide Data Terminal Equipment (DTE) sourced transmit clocking (i.e. D6 = 0, the clock is sourced by the co-processor) or Data Computer Equipment (DCE) sourced transmit clocking (i.e. D6 = 1, the clock is sourced from a modem or similar device).

    The RECEIVE clocking options are determined by the LOCAL and DPLL/32 bits. The co-processor Receive (RX) clock can be either local or remote sourced, depending on whether or not a remote clock is used (for example, from a modem or other DCE). The REMOTE clocking option is selected by writing a 0 to bit D5. If the LOCAL clocking option is selected (D5 = 1), then there is a Digital Phase Locked Loop (DPLL) associated with the Receive clock. The DPLL can be programmed to operate at either 16 or 32 times the data rate, depending on the application clocking scheme. The DPLL/32 bit should be programmed according to the clocking selected (i.e D4 = 0 for /16 option and D4 = 1 for /32 option).

    Address Bits (A20 through 23): These bits are a continuation of the address in POS3.

    POS5

    Bits D0 through D2: Identical to INITREG3.

    Clocking options Port 1 (DPLL/32, Local, DCE/DTE)

    These bits configure the clocking options for Port 1 of the SCC. The Transmit clock source is determined by the DCE/DTE bit. The co-processor can be configured to provide Data Terminal Equipment (DTE) sourced transmit clocking (i.e. D5 = 0, the clock is sourced by the co-processor) or Data Computer Equipment (DCE) sourced transmit clocking (i.e. D5 = 1, the clock is sourced from a modem or similar device).

    The Receive clocking options are determined by the LOCAL and DPLL/32 bits. The co-processor Receive (RX) clock can be either local or remote sourced, depending on whether or not a remote clock is used (for example, from a modem or other DCE). The REMOTE clocking option is selected by writing a 0 to bit D4. If the LOCAL clocking option is selected (D4 = 1), then there is a Digital Phase Locked Loop (DPLL) associated with the Receive clock. The DPLL can be programmed to operate at either 16 or 32 times the data rate, depending on the application clocking scheme. The DPLL/32 bit should be programmed according to the clocking selected (i.e D3 = 0 for /16 option and D3 = 1 for /32 option).

    Bit D6 (CKS): Always set to one. The inverse of NCKI (bit D7) is CKI in PS/2PAR2.

    Window Size (W1, W2, W4): These bits define the window size. 8 KB is the default.

    SSTIC register descriptions

    Command register

    Description

    The command register (COMREG) is a PS/2 read/write register that provides some control of the adapter from the PS/2.

    Figure 16. Command register format

      +--+--+--+--+--+--+--+--+
      |D7|D6|D5|D4|D3|D2|D1|D0|                    Reset Conditions
      +-++-++-++-++-++-++-++-++                    ----------------------------
        |  |  |  |  |  |  |  |                      Power-on Reset : 0000 0000
        |  |  |  |  |  |  |  |                      Command Reset  : 0000 0SS0
        |  |  |  |  |  |  |  +--- RC
        |  |  |  |  |  |  +------ NC
        |  |  |  |  |  +--------- DG
        |  |  |  |  +------------ FP               Address
        |  |  |  +--------------- IE               -------------
        |  |  +------------------ IP                PS/2 : 06H
        |  +--------------------- RA                Adapter : -
        +------------------------ 00
    
    Bit description

    Bit 7
    Reserved. Always set this to 0.

    Bit 6 (RA)
    DRAM access error. This is a read-only bit, valid only after an I/O channel check. If this bit is set to 1, a DRAM access error has occurred. If this bit is set to 0, a parity error has occurred. In both cases the address where the error occurred is saved in the PS/2PAR registers.

    Bit 5 (IP)
    Interrupt pending. This is a read-only bit. If this bit is set to 1, an interrupt to the PS/2 is pending. This bit is cleared by the PS/2 reading the task register (TREG), and by a channel reset.

    Bit 4 (IE)
    Interrupt enable. Setting this bit to 1 lets the adapter interrupt the PS/2. Clearing this bit (to 0) disables adapter-to-PS/2 interrupts. If an adapter-to-PS/2 interrupt is pending (IP=1) and this bit is set, the PS/2 is interrupted.

    Bit 3 (FP)
    Force bad parity. This bit and bit 7 of NMIMASK test the parity circuits. It has separate read and write functions.

    This bit is the PS/2 force-bad-parity bit; bit 7 of NMIMASK is the adapter force-bad-parity bit. If both of these bits are set to 0, all data from the PS/2 and the adapter is written with bad parity.

    This bit reads 1 if either this bit or bit 7 of NMIMASK is set to 1. It only reads 0 (active) when the adapter and PS/2 have their respective force-bad-parity bits set to 0, as shown in Figure 17. It does, however, read 0 after a reset but is not active.

    Figure 17. Force-bad-parity control bit

                                                          +-------- PS/2 Read
    PS/2 Write    --------------+                         |
                                |                         V
                                V                         +---+
                         +-------------+      +-----+   | B +-----> Bit 3 COMREG
    Bit 3 COMREG  ------>|    LATCH    +----->|     |   +---+
                         +-------------+      |     |     |
                                              |  OR +-----+----- Force bad parity
                         +-------------+      |     |     |      control bit
    Bit 7 NMIMASK ------>|    LATCH    +----->|     |   +---+
                         +-------------+      +-----+   | B-+-----> Bit 7 MNIMASK
                                A                       +---+
                                |                         A
    Adapter Write --------------+                         |
                                                          +-------- Adapter Read
    
    +==============+==============+=============+
    | Bit 3 COMREG | Bit 7 NMIMASK| Force bad   |
    +-------+------+-------+------+ parity      +
    | Write | Read | Write | Read | control bit |
    +=======+======+=======+======+=============+
    |   0   |  0   |   0   |  0   |      0      |
    |   0   |  1   |   1   |  1   |      1      |
    |   1   |  1   |   0   |  1   |      1      |
    |   1   |  1   |   1   |  1   |      1      |
    +=======+======+=======+======+=============+
    
    Bit 2 (DG)
    Degate DRAM. This bit and bit 6 of NMIMASK degate the PS/2 bus from the adapter DRAM. It has separate read and write functions.

    This bit is the PS/2 degate-DRAM bit; bit 6 of NMIMASK is the adapter degate-DRAM bit. If both of these bits are set to 0, the PS/2 bus is degated from the adapter DRAM.

    This bit reads 1 either this bit or bit 6 of NMIMASK is set to 1. It only reads 0 (active) when the adapter and PS/2 set their respective degate-DRAM bits to 0, as shown in Figure 18. It does, however, read 0 after a reset but is not active.

    If this bit is set during a PS/2 memory read or write operation, the behavior of the SSTIC is unpredictable.

    Figure 18. Degate DRAM control bit

                                                          +-------- PS/2 Read
    PS/2 Write    --------------+                         |
                                |                         V
                                V                         +---+
                         +-------------+      +-----+   | B +-----> Bit 2 COMREG
    Bit 2 COMREG  ------>|    LATCH    +----->|     |   +---+
                         +-------------+      |     |     |
                                              |  OR +-----+-------- Degate DRAM
                         +-------------+      |     |     |         control bit
    Bit 6 NMIMASK ------>|    LATCH    +----->|     |   +---+
                         +-------------+      +-----+   | B-+-----> Bit 6 MNIMASK
                                A                       +---+
                                |                         A
    Adapter Write --------------+                         |
                                                          +-------- Adapter Read
    
    +==============+==============+=============+
    | Bit 2 COMREG | Bit 6 NMIMASK| Degate DRAM |
    +-------+------+-------+------+ control Bit +
    | Write | Read | Write | Read |             |
    +=======+======+=======+======+=============+
    |   0   |  0   |   0   |  0   |      0      |
    |   0   |  1   |   1   |  1   |      1      |
    |   1   |  1   |   0   |  1   |      1      |
    |   1   |  1   |   1   |  1   |      1      |
    +=======+======+=======+======+=============+
    
    Bit 1 (NC)
    NMI command. Setting this bit sets bit 4 of NMISTAT and raises an NMI to the adapter (provided it is not masked in NMIMASK). Clearing this bit does not clear bit 4 of NMISTAT; it is cleared when the adapter reads NMISTAT.

    This bit is affected by bit 0 (reset command) of this register. Bit 0 must not be cleared in the same instruction that sets bit 1 of this register.

    Example

    COMREG contains 0000 0001.
    To clear the reset command and set NMI:
    
    Write(COMREG) 0000 0000  ; Clear reset command
    Write(COMREG) 0000 0010  ; Set NMI
    
    Bit 0 (RC)
    Reset command. Setting this bit causes a partial SSTIC reset and a hardware reset of the adapter. The adapter is held reset until this bit is cleared. This command should be issued for at least 1 microsecond.

    If the PROM Ready bit is cleared before this bit is set, the PROM Ready bit indicates when POST has finished. The following registers are affected:

    The following are also cleared:

    Ctrl-Alt-Del registers

    Description

    The Ctrl-Alt-Del (CAD0, CAD1, CAD2) registers are PS/2 read/write registers. They are programmed with a PS/2 address that is only accessed during a Ctrl-Alt-Del keyboard sequence. They detect a Ctrl-Alt-Del keyboard sequence, by comparing the PS/2 address bus with the values in the Ctrl-Alt-Del registers, on every valid memory read or write cycle. If a Ctrl-Alt-Del sequence is detected, DRAM is degated from the PS/2.

    The "lower 16 MB indicator" is used in the Ctrl-Alt-Del match circuitry. In a PS/2 with more than 16 MB of memory, the Ctrl-Alt-Del match may be of no use.

    The channel reset is ORed with the Ctrl-Alt-Del match signal and therefore degates the DRAM from the PS/2.

    Figure 19. Ctrl-Alt-Del register format

      +--+--+--+--+--+--+--+--+
      |D7|D6|D5|D4|D3|D2|D1|D0|                    Reset Conditions
      +-++-++-++-++-++-++-++-++                    ----------------------------
        |  |  |  |  |  |  |  |   CAD0 CAD1 CAD2     Power-on Reset : 0000 0000
        |  |  |  |  |  |  |  |                      Command Reset  : SSSS SSSS
        |  |  |  |  |  |  |  +--- A0   A8   A16
        |  |  |  |  |  |  +------ A1   A9   A17
        |  |  |  |  |  +--------- A2   A10  A18
        |  |  |  |  +------------ A3   A11  A19    Address
        |  |  |  +--------------- A4   A12  A20    -------------
        |  |  +------------------ A5   A13  A21     PS/2 : [0CH],[0DH],[0EH]
        |  +--------------------- A6   A14  A22     Adapter : -     -     -
        +------------------------ A7   A15  A23
    
    Bit description
    Bits 7-0
    PS/2 address bits.

    CPU page register

    Description

    The CPU page register (CPUPG) is a PS/2 and adapter read/write register. It locates the shared storage window in adapter DRAM.

    Figure 20. CPU page register description

    +--+--+--+--+--+--+--+--+
    |D7|D6|D5|D4|D3|D2|D1|D0|                      Reset Conditions
    +-++-++-++-++-++-++-++-++                      ----------------------------
      |  |  |  |  |  |  |  |  Window Size           Power-on Reset : UUUU UUUU
      |  |  |  |  |  |  |  |    8KB 16KB 32KB 64KB  Command Reset  : SSSS SSSS
      |  |  |  |  |  |  |  +--- A13  A14  A15  A16
      |  |  |  |  |  |  +------ A14  A15  A16  A17
      |  |  |  |  |  +--------- A15  A16  A17  A18
      |  |  |  |  +------------ A16  A17  A18  A19  Address
      |  |  |  +--------------- A17  A18  A19  00   -------------
      |  |  +------------------ A18  A19  00   00    PS/2 : 05H
      |  +--------------------- A19  00   00   00    Adapter : -
      +------------------------ 00   00   00   00
    
    Bit description

    Bit 7
    Reserved. Always programmed to 0.

    Bits 6-0
    Page values. These bits contain the number (0-7Fh) of a page of adapter memory accessible by the PS/2 (the shared storage window).

    Changing the window size changes the page number. For example, if the shared storage window size is 8 KB and the page number is 08h, dynamically changing the window to 16 KB changes the page value to 04h.

    If DRAM is degated by a Ctrl-Alt-Del match, a power-on reset, or a channel reset, the first write instruction to this register gates the DRAM to the PS/2 bus. DRAM is not gated if PS/2 refresh activity is not detected, or if the sleep bit is set. Results are uncertain if the PS/2 and adapter microprocessors attempt to modify this register simultaneously.

    Adapter ID registers

    Description

    The adapter ID registers (CRDIDL and CRDIDU) provide the adapter ID at power-on to allow POS to identify the adapter. The ID for the IBM X.25 Interface Co-Processor/2 and the Realtime Interface Co-Processor Multiport/2 adapters is EFF0h.

    Figure 21. Adapter ID register format

      +--+--+--+--+--+--+--+--+
      |D7|D6|D5|D4|D3|D2|D1|D0|                Reset Conditions
      +-++-++-++-++-++-++-++-++                ----------------------------
        |  |  |  |  |  |  |  |                  Power-on Reset : 11 0000,1110 1111
        |  |  |  |  |  |  |  |   CRDIDL CRDIDH  Command Reset  : SS SSSS,SSSS SSSS
        |  |  |  |  |  |  |  +---  0      1
        |  |  |  |  |  |  +------  0      1
        |  |  |  |  |  +---------  0      1
        |  |  |  |  +------------  0      1    Address
        |  |  |  +---------------  1      0    -------------
        |  |  +------------------  1      1     POS     : 00H,001H
        |  +---------------------  1      1     PS/2    : -    -
        +------------------------  1      1     Adapter : -    -
    
    
    Bit description
    Bits 7-0
    Fixed data bits. The value of these registers cannot be altered.

    Data register

    Description

    The data register (DREG) is a PS/2 pseudo-register; it allows access to the register pointed to by the pointer register PTRREG. Its read and write characteristics are the same as those of the register accessed.

    Figure 22. Data register format

      +--+--+--+--+--+--+--+--+
      |D7|D6|D5|D4|D3|D2|D1|D0|                    Reset Conditions
      +-++-++-++-++-++-++-++-++                    ----------------------------
        |  |  |  |  |  |  |  |                      Power-on Reset : UUUU UUUU
        |  |  |  |  |  |  |  |                      Command Reset  : UUUU UUUU
        |  |  |  |  |  |  |  +--- D0
        |  |  |  |  |  |  +------ D1
        |  |  |  |  |  +--------- D2
        |  |  |  |  +------------ D3               Address
        |  |  |  +--------------- D4               -------------
        |  |  +------------------ D5                PS/2  : 03H
        |  +--------------------- D6                Adapter : -
        +------------------------ D7
    
    Bit description
    Bits 7-0
    Data bits. Data is variable depending on which register is pointed to by PTRREG.

    SSTIC identification register

    Description

    The SSTIC identification register (GAID) contains the ID of the version of the SSTIC installed on the adapter. This is a PS/2 and adapter read register.

    Figure 23. SSTIC identification register format

      +--+--+--+--+--+--+--+--+
      |D7|D6|D5|D4|D3|D2|D1|D0|                    Reset Conditions
      +-++-++-++-++-++-++-++-++                    ----------------------------
        |  |  |  |  |  |  |  |                      Power-on Reset : 1100 0000
        |  |  |  |  |  |  |  |  SSTIC3              Command Reset  : SSSS SSSS
        |  |  |  |  |  |  |  +--- 0
        |  |  |  |  |  |  +------ 0
        |  |  |  |  |  +--------- 0
        |  |  |  |  +------------ 0                Address
        |  |  |  +--------------- 0                -------------
        |  |  +------------------ 0                 PS/2  :  [0FH]
        |  +--------------------- 1                 Adapter : 18H
        +------------------------ 1
    
    Bit description
    Bits 7-0
    Data bits. These provide the ID for the SSTIC installed on the adapter. The ID for SSTIC version 3 is C0h.

    Internal DMA allocation logic register

    Description

    The internal DMA allocation register (IDAL) is the adapter read/write register that controls the DMA steering multiplexer. It assigns the DMA channels of the 80186 microprocessor to the four requesting sources as shown in Figure 25. The four possible DMA requests are from the SCC:

    1. Port 0 transmitter

    2. Port 0 receiver

    3. Port 1 transmitter

    4. Port 1 receiver.
    The hardware cannot resolve a conflicting configuration (such as R3, R2, R1, R0=0000).

    Figure 24. Internal DMA allocation register format

      +--+--+--+--+--+--+--+--+
      |D7|D6|D5|D4|D3|D2|D1|D0|                    Reset Conditions
      +-++-++-++-++-++-++-++-++                    ----------------------------
        |  |  |  |  |  |  |  |                      Power-on Reset : 0000 0000
        |  |  |  |  |  |  |  |                      Command Reset  : 0000 0000
        |  |  |  |  |  |  |  +--- 00
        |  |  |  |  |  |  +------ 00
        |  |  |  |  |  +--------- 00
        |  |  |  |  +------------ XX               Address
        |  |  |  +--------------- R0               -------------
        |  |  +------------------ R1                PS/2  :   -
        |  +--------------------- R2                Adapter : 84H
        +------------------------ R3
    
    Figure 25. DMA allocation logic
                                         +------------+
    +---------+      +---------+         |--+         |
    |         | DMA0 |         |<---Rx---|  |         |
    |  80196  |<-----|   DMA   |         | 0|         |
    |         |      |         |<---Tx---|  |         |
    |         |<-----|  ALLOC  |         |--+         |
    |         | DMA1 |  LOGIC  |         |      SCC   |
    +---+-----+      |         |         |--+         |
        |            |         |<---Rx---| 1|         |
        |            |  (MUX)  |<---Tx---|  |         |
        |            +---------+         |--+         |
        |            |  LATCH  |<---+    |            |
        |            +---------+    |    +------------+
        |                 A         |
        |     DATA BUS    |         |
        +-----------------+        CS
    
         DMA Channel 0 Assignment              DMA Channel 1 Assignment
    +====+====+=======================+   +====+====+=======================+
    | R1 | R0 | SCC Requestion Source |   | R3 | R2 | SCC Requesting Source |
    +====+====+=======================+   +====+====+=======================+
    |  0 |  O | Port 0 Transmitter    |   |  0 |  0 | Port 0 Transmitter    |
    |  0 |  1 | Port 0 Receiver       |   |  0 |  1 | Port 0 Receiver       |
    |  1 |  O | Port 1 Transmitter    |   |  1 |  0 | Port 1 Transmitter    |
    |  1 |  1 | Port 1 Receiver       |   |  1 |  1 | Port 1 Receiver       |
    +====+====+=======================+   +====+====+=======================+
    
    Bit description
    Bits 4-7 (R3-R0)
    DMA allocation control. These bits allocate an SCC port to a DMA channel as shown in Figure 25.

    Bits 3-0
    Reserved. Always set to zero.

    Initialization registers

    Description

    The initialization registers INITREG0, INITREG1 and INITREG2 are PS/2 and adapter read/write registers. INITREG3 is a PS/2 read-only register. These registers initialize the SSTIC.

    INITREG0 and INITREG3 are programmed by POS. INITREG1 should be programmed by POST or a user task.

    The POS registers are shown in Figure 15.

    Figure 26. Initialization register format

    +--+--+--+--+--+--+--+--+
    |D7|D6|D5|D4|D3|D2|D1|D0|                      Reset Conditions
    +-++-++-++-++-++-++-++-++                      ----------------------------
      |  |  |  |  |  |  |  |                        Power-on Reset : 0000 0000
      |  |  |  |  |  |  |  |   REG0 REG1 REG2 REG3  Command Reset  : SSSS SSSS
      |  |  |  |  |  |  |  +--- L1   XX   L1   W1
      |  |  |  |  |  |  +------ L2   XX   L2   W2
      |  |  |  |  |  +--------- L4   XX   L4   W4
      |  |  |  |  +------------ SE   M1   00   00   Address
      |  |  |  +--------------- C1   LN   00   00   -------------
      |  |  +------------------ C2   M2   00   00    PS/2 :  [12H],[10H],[08H],[13H]
      |  +--------------------- C4   RR   00   00    Adapter :04H   06H    -    1AH
      +------------------------ C8   DR   00   00
    
    Note: This register is accesible from PDS, but the format is different.
    
    Bit description

    INITREG0 and INITREG2
    Bits 7-4 (C8-C1)
    Adapter number. These registers specify the base location in PS/2 I/O space of the adapter I/O block. Each adapter should have an address that does not conflict with other adapters in the PS/2. These bits are not available in INITREG2. The actual base addresses selected are shown in Table 27.

    Table 27. I/O block address selection

    +====+====+====+====+============+
    | C8 | C4 | C2 | C1 | Base       |
    |    |    |    |    | Address    |
    +====+====+====+====+============+
    | 0  | 0  | 0  | 0  | 02A0h      |
    +----+----+----+----+------------+
    | 0  | 0  | 0  | 1  | 06A0h      |
    +----+----+----+----+------------+
    | 0  | 0  | 1  | 0  | 0AA0h      |
    +----+----+----+----+------------+
    | 0  | 0  | 1  | 1  | 0EA0h      |
    +----+----+----+----+------------+
    | 0  | 1  | 0  | 0  | 12A0h      |
    +----+----+----+----+------------+
    | 0  | 1  | 0  | 1  | 16A0h      |
    +----+----+----+----+------------+
    | 0  | 1  | 1  | 0  | 1AA0h      |
    +----+----+----+----+------------+
    | 0  | 1  | 1  | 1  | 1EA0h      |
    +----+----+----+----+------------+
    | 1  | 0  | 0  | 0  | 22A0h      |
    +----+----+----+----+------------+
    | 1  | 0  | 0  | 1  | 26A0h      |
    +----+----+----+----+------------+
    | 1  | 0  | 1  | 0  | 2AA0h      |
    +----+----+----+----+------------+
    | 1  | 0  | 1  | 1  | 2EA0h      |
    +----+----+----+----+------------+
    | 1  | 1  | 0  | 0  | 32A0h      |
    +----+----+----+----+------------+
    | 1  | 1  | 0  | 1  | 36A0h      |
    +----+----+----+----+------------+
    | 1  | 1  | 1  | 0  | 3AA0h      |
    +----+----+----+----+------------+
    | 1  | 1  | 1  | 1  | 3EA0h      |
    +----+----+----+----+------------+
    
    Bit 3 (SE)
    Sleep enable. When cleared, this bit disables the adapter from the PS/2 bus. It is cleared by a channel reset.

    Bits 2-0 (L4-L1)
    Interrupt level. These bits specify the level at which the adapter interrupts the PS/2. The levels that may be selected are shown in Table 28.

    Table 28. Interrupt level selection.

    +====+====+====+================+
    | L4 | L2 | L1 | Interrupt      |
    |    |    |    | Level          |
    +====+====+====+================+
    | 0  | 0  | 0  | 3              |
    +----+----+----+----------------+
    | 0  | 0  | 1  | 4              |
    +----+----+----+----------------+
    | 0  | 1  | 0  | 7              |
    +----+----+----+----------------+
    | 0  | 1  | 1  | 9              |
    +----+----+----+----------------+
    | 1  | 0  | 0  | 10             |
    +----+----+----+----------------+
    | 1  | 0  | 1  | 11             |
    +----+----+----+----------------+
    | 1  | 1  | 0  | 12             |
    +----+----+----+----------------+
    | 1  | 1  | 1  | 15             |
    +----+----+----+----------------+
    
    INITREG1
    Bit 7 (DR)
    Double refresh time. Setting this bit refreshes DRAM every 15.6 microseconds. Clearing this bit refreshes DRAM every 7.8 microseconds. DRAM bandwidth gain is only 2% when the slower rate is used.

    Bit 6 (RR)
    PROM ready. This bit is set by POST when it has completed. If an error is found, it is not set. It is cleared by a power-on.

    Bit 5 (M2)
    DRAM size. 1=512 KB. This bit is set by POST; it is irrelevant if M1 is set.

    Bit 4 (LN)
    Lost refresh disable. Setting this bit disables lost refresh detection. Clearing this bit enables lost refresh detection.

    Bit 3 (M1)
    DRAM size. 1=128 KB; 0=512 KB. This bit is set by POST.

    Bits 2-0
    Reserved.
    INITREG3
    Bits 7-3
    Reserved. Always set to zero.

    Bits 2-0 (W4-W1)
    Window size. This value selects the window size that the PS/2 views at any one time. 8 KB is the default. The window size is selected as shown in Table 29.
    Table 29. Shared window size selection.
    +======+======+======+=======================================================+
    | W4   | W2   | W1   | Size                                                  |
    +======+======+======+=======================================================+
    | 0    | 0    | 0    | 8 KB                                                  |
    +------+------+------+-------------------------------------------------------+
    | 0    | 0    | 1    | 16 KB                                                 |
    +------+------+------+-------------------------------------------------------+
    | 0    | 1    | 0    | 32 KB                                                 |
    +------+------+------+-------------------------------------------------------+
    | 0    | 1    | 1    | 64 KB                                                 |
    +------+------+------+-------------------------------------------------------+
    

    Window location registers

    Description

    The window location registers (LOCREG0 and LOCREG1) are PS/2 and adapter read/write registers. They place the shared memory window anywhere in the 16 MB of PS/2 memory on a boundary defined by W4, W2 and W1 in INITREG3. They must not be altered without degating the PS/2 from DRAM. The value of the registers cannot be determined if the PS/2 and adapter try to modify these registers at the same time. These registers are normally initialized by POS3 and POS4 registers (see Figure 15).

    Figure 27. Window location register format

    +--+--+--+--+--+--+--+--+
    |D7|D6|D5|D4|D3|D2|D1|D0|                      Reset Conditions
    +-++-++-++-++-++-++-++-++                      ----------------------------
      |  |  |  |  |  |  |  |                        Power-on Reset : UUUU UUUU
      |  |  |  |  |  |  |  |   LOCREG0   LOCREG1    Command Reset  : SSSS SSSS
      |  |  |  |  |  |  |  +--- A13       A20
      |  |  |  |  |  |  +------ A14       A21
      |  |  |  |  |  +--------- A15       A22
      |  |  |  |  +------------ A16       A23       Address
      |  |  |  +--------------- A17       00        -------------
      |  |  +------------------ A18       00         PS/2   : 00H,01H
      |  +--------------------- A19       00         Adapter: 00H,02H
      +------------------------ 00        00
    
    Note: These registers may be accessed from PDS, but the format is different.
    
    Bit description

    LOCREG0
    Bit 7
    Reserved. Always set to zero.

    Bits 6-0
    Address bits. PS/2 address bits A19 through A13 must match LOCREG0 to access the DRAM. 16 KB boundaries do not use A13; 32 KB boundaries do not use A13 and A14; 64 KB boundaries do not use A13, A14 and A15.

    If the window size is changed, the boundary of the window also changes. For example, if there is an 8 KB window initially at 0C200h (segment 61h) and the size of the window is changed to 16 KB, the new boundary is at 0C000h (segment 60h). The user task must keep track of these changes.

    LOCREG1
    Bits 7-4
    Reserved. Always set to zero.

    Bits 3-0
    Address bits. LOCREG1 is a continuation of LOCREG0.

    NMI mask register

    Description

    The NMI mask register (NMIMASK) is an adapter read/write register. It allows masking of internal nonmaskable interrupts to the 80186 microprocessor. Bits 7 and 6 provide command features for the adapter.

    Figure 28. NMI mask register format

    +--+--+--+--+--+--+--+--+
    |D7|D6|D5|D4|D3|D2|D1|D0|                      Reset Conditions
    +-++-++-++-++-++-++-++-++                      ----------------------------
      |  |  |  |  |  |  |  |                        Power-on Reset : 0011 1111
      |  |  |  |  |  |  |  |                        Command Reset  : 0011 1111
      |  |  |  |  |  |  |  +--- CAD/CRST
      |  |  |  |  |  |  +------ WD
      |  |  |  |  |  +--------- PE
      |  |  |  |  +------------ PS/2C               Address
      |  |  |  +--------------- NC                  -------------
      |  |  +------------------ LR                   PS/2   :  -
      |  +--------------------- DG                   Adapter: 08H
      +------------------------ FP
    
    Bit description

    Bit 7 (FP)
    Force bad parity. This bit and bit 3 of COMREG test the parity circuits. It has separate read and write functions.

    This bit is the adapter force-bad-parity bit; bit 3 of COMREG is the PS/2 force-bad-parity bit. If both of these bits are set to 0, all data from the PS/2 and the adapter is written with bad parity.

    This bit reads 1 if either this bit or bit 3 of COMREG is set to 1. It only reads 0 (active) when the adapter and PS/2 have their respective force-bad-parity bits set to 0, as shown in Figure 17. It does, however, read 0 after a reset but is not active.

    Bit 6 (DG)
    Degate DRAM. This bit and bit 2 of COMREG degate the PS/2 bus from the adapter DRAM. It has separate read and write functions.

    This bit is the adapter degate-DRAM bit; bit 2 of COMREG is the PS/2 degate-DRAM bit. If both these bits are set to 0, the PS/2 bus is degated from the adapter DRAM.

    This bit reads 1 if either this bit or bit 2 of COMREG is set to 0. It only reads 0 (active) when the adapter and PS/2 have their respective degate-DRAM bits set to 0, as shown in Figure 18. It does, however, read 0 after a reset but is not active.

    If this bit is set during a PS/2 memory read or write operation, the behavior of the SSTIC is unpredictable.

    Bit 5 (LR)
    Lost PS/2 refresh mask bit. If the PS/2 stops refreshing its DRAM and this bit is clear, an NMI is raised to the 80186 microprocessor. Setting this bit masks the NMI from the 80186 microprocessor. In either case, a PS/2 lost-refresh indication is posted in NMISTAT.

    Bit 4 (NC)
    NMI command mask bit. The PS/2 can issue an NMI command in COMREG. If this bit is clear (0) an NMI is raised to the 80186 microprocessor. Setting this bit prevents an NMI being raised if the PS/2 issues an NMI command. In either case, a PS/2 NMI command indication is posted in NMISTAT.

    Bit 3 (PS/2C)
    PS/2 I/O channel check mask bit. The SSTIC monitors the PS/2 I/O channel check line. If a channel check occurs and this bit is clear (0) an NMI is raised to the 80186 microprocessor. Setting this bit prevents an NMI being raised if a channel check occurs. In either case, an I/O Channel Check indication is posted in NMISTAT.

    Bit 2 (PE)
    Adapter parity error mask bit. If the 80186 microprocessor detects a parity error or DRAM access error and this bit is clear (0), an NMI is raised to the 80186 microprocessor. Setting this bit prevents an NMI being raised if a parity error or DRAM access error occurs. In either case, a parity error indication is posted in NMISTAT.

    Bit 1 (WD)
    Watchdog timer mask bit. The SSTIC monitors the watchdog timer. If the watchdog times out and this bit is clear (0) an NMI is raised to the 80186 microprocessor, FEh is written to the task register, and an interrupt is raised to the PS/2. Setting this bit prevents all three actions if the watchdog times out. In either case, a timeout indication is posted in NMISTAT.

    Bit 0 (Ctrl-Alt-Del)
    Ctrl-Alt-Del match/channel reset mask bit. When a Ctrl-Alt-Del match is detected, or a PS/2 channel reset occurs during a warm start, and this bit is clear (0), an NMI is raised to the 80186 microprocessor. Setting this bit prevents an NMI being raised. In either case, a Ctrl-Alt-Del error indication is posted in NMISTAT.

    NMI status register

    Description

    The NMI status register (NMISTAT) is an adapter read-only register. It shows the status of the nonmaskable interrupts whether or not they are masked in the NMIMASK register. The internal status latches are edge sensitive. Once a bit has been set, it is not cleared until NMISTAT is read. Bits 7 and 6 provide adapter-to-PS/2 interrupt status, not NMI status.

    Figure 29. NMI status register format

    +--+--+--+--+--+--+--+--+
    |D7|D6|D5|D4|D3|D2|D1|D0|                      Reset Conditions
    +-++-++-++-++-++-++-++-++                      ----------------------------
      |  |  |  |  |  |  |  |                        Power-on Reset : 0000 0000
      |  |  |  |  |  |  |  |                        Command Reset  : 0000 0000
      |  |  |  |  |  |  |  +--- CAD/CRST
      |  |  |  |  |  |  +------ WD
      |  |  |  |  |  +--------- PE
      |  |  |  |  +------------ PS/2C               Address
      |  |  |  +--------------- NC                  -------------
      |  |  +------------------ LR                   PS/2   :  -
      |  +--------------------- IE                   Adapter: 0AH
      +------------------------ IP
    
    Bit Descriptions:
    Bit 7 (IP)
    Interrupt pending. If this bit is set to 1, an adapter-to-PS/2 interrupt is pending. This bit is cleared by the PS/2 reading TREG.

    Bit 6 (IE)
    PS/2 Interrupt enable. If this bit is set to 1, adapter-to-PS/2 interrupts are enabled.

    Bit 5 (LR)
    PS/2 lost refresh status. If this bit is set to 1, the PS/2 has lost refresh. This bit is cleared by the 80186 microprocessor reading this register; this also terminates the NMI.

    Bit 4 (NC)
    NMI command status. If this bit is set to 1, the PS/2 has issued a NMI command. This bit is cleared by the 80186 microprocessor reading this register; this also terminates the NMI.

    Bit 3 (PS/2C)
    PS/2 I/O channel check status. This bit is cleared by the 80186 microprocessor reading this register; this also terminates the NMI.

    Bit 2 (PE)
    Adapter parity error status. If this bit is set to 1, the SSTIC has detected a parity or DRAM access error. This bit is cleared by the 80186 microprocessor reading this register; this also terminates the NMI.

    Bit 1 (WD)
    Watchdog timer error status. If this bit is set to 1, the watchdog timer has timed out. This bit is cleared by the 80186 microprocessor reading this register; this also terminates the NMI.

    Bit 0 (Ctrl-Alt-Del)
    Ctrl-Alt-Del match/channel reset status. If this bit is set to 1, the PS/2 has detected a Ctrl-Alt-Del match or a PS/2 channel reset. This bit is cleared by the 80186 microprocessor reading this register; this also terminates the NMI.

    PS/2 parity-error registers

    Description

    The PS/2 parity registers are PS/2PAR0, PS/2PAR1, and PS/2PAR2. PS/2PAR0 and PS/2PAR1 are adapter read-only registers. PS/2PAR2 is an adapter read-write register. The PS/2PAR registers capture the PS/2 status and PS/2 address at which a parity error occurred. The data in these registers is only valid after an parity error. To enable further parity checking, the PS/2 must write to any location in adapter DRAM.

    These registers can be used in conjunction with CPUPG to determine exactly where a parity error occurred.

    Figure 30. PS/2 parity register format

    +--+--+--+--+--+--+--+--+
    |D7|D6|D5|D4|D3|D2|D1|D0|   Reset Conditions
    +-++-++-++-++-++-++-++-++   ----------------------------
      |  |  |  |  |  |  |  |     Power-on Reset : 0000 0000,0000 0000,0000 0001
      |  |  |  |  |  |  |  |     Command Reset  : SSSS SSSS,SSSS SSSS,SSSS SSSS
      |  |  |  |  |  |  |  |  PS2PAR0 PS2PAR1 PS2PAR2
      |  |  |  |  |  |  |  +--- A0      A8      IEN
      |  |  |  |  |  |  +------ A1      A9      IPS
      |  |  |  |  |  +--------- A2      A10     CKI
      |  |  |  |  +------------ A3      A11     0   Address
      |  |  |  +--------------- A4      A12     0   -------------
      |  |  +------------------ A5      A13     0    PS/2   : [0AH],[0BH],[11H]
      |  +--------------------- A6      A14     0    Adapter:   -     -     -
      +------------------------ A7      A15     0
    
    Note: The inverse of CKI may be accessed by POS5.
    
    Bit description

    PS/2PAR0
    Bits 7-0
    PS/2 address bits. The address at which a parity error occurred.
    PS/2PAR1
    Bits 7-5
    PS/2 address bits. These bits are only valid when the shared window is larger than 8 KB.
    Size        Address Bits
    ------      ---------------------
    8 KB        A13-A15 always zero
    16 KB       A13 valid, A14-A15 a
    32 KB       A13-A14 valid, A15 a
    64 KB       A13-A15 valid
    
    Bits 4-0
    PS/2 address bits. The remainder of the address at which a parity error occurred.
    PS/2PAR2
    Bits 7-3
    Reserved. Always set to zero.

    Bit 2 (CKI)
    I/O channel check status. This is a read-only bit. If this bit is set to 1, an I/O channel check has occurred. This bit is cleared by: This bit always indicates status regardless of the state of bits 0 or 1. This bit is the inverse of NCKI in POS5.

    Bit 1 (IPS)
    I/O channel check pulse mode. If a parity error occurs and this bit is set, an I/O channel check is pulsed. If a parity error occurs and this bit is clear, the I/O channel check stays active low.

    Bit 0 (IEN)
    I/O channel check enable. Setting this bit enables the I/O channel check line to report parity errors. Clearing this bit disables all error reporting, except for errors due to bit 2 of this register being set.

    Pointer register

    Description

    The pointer register (PTRREG) is a PS/2 read/write register. It allows access to other PS/2 registers via the data register DREG. It allows access to the register currently pointed to by PTRREG (see Table 30). Repeated accesses may be made to the register if PTRREG is not changed.

    Figure 31. Pointer register format

      +--+--+--+--+--+--+--+--+
      |D7|D6|D5|D4|D3|D2|D1|D0|                    Reset Conditions
      +-++-++-++-++-++-++-++-++                    ----------------------------
        |  |  |  |  |  |  |  |                      Power-on Reset : UUUU UUUU
        |  |  |  |  |  |  |  |                      Command Reset  : UUUU UUUU
        |  |  |  |  |  |  |  +--- R0
        |  |  |  |  |  |  +------ R1
        |  |  |  |  |  +--------- R2
        |  |  |  |  +------------ R3               Address
        |  |  |  +--------------- R4               -------------
        |  |  +------------------ R5                PS/2  : [02H]
        |  +--------------------- R6                Adapter : -
        +------------------------ R7
    
    Bit description
    Bits R7-R0
    Register value. These bits select the register that can be accessed via DREG. Results are unpredictable if the reserved registers are used.
    Table 30. PTRREG value description.
    +==========+=================================================================+
    | R7-0     | Register/Function                                               |
    +==========+=================================================================+
    | 00-07    | Reserved                                                        |
    +----------+-----------------------------------------------------------------+
    | 08       | INITREG2                                                        |
    +----------+-----------------------------------------------------------------+
    | 09       | Reserved for INTCOM                                             |
    +----------+-----------------------------------------------------------------+
    | 0A       | PS/2PAR0                                                        |
    +----------+-----------------------------------------------------------------+
    | 0B       | PS/2PAR1                                                        |
    +----------+-----------------------------------------------------------------+
    | 0C       | CAD0                                                            |
    +----------+-----------------------------------------------------------------+
    | 0D       | CAD1                                                            |
    +----------+-----------------------------------------------------------------+
    | 0E       | CAD2                                                            |
    +----------+-----------------------------------------------------------------+
    | 0F       | GAID                                                            |
    +----------+-----------------------------------------------------------------+
    | 10       | INITREG1                                                        |
    +----------+-----------------------------------------------------------------+
    | 11       | PS/2PAR2                                                        |
    +----------+-----------------------------------------------------------------+
    | 12       | INITREG0                                                        |
    +----------+-----------------------------------------------------------------+
    | 13       | INITREG3                                                        |
    +----------+-----------------------------------------------------------------+
    | 14-EF    | Reserved                                                        |
    +----------+-----------------------------------------------------------------+
    | F0-F1    | Test register                                                   |
    +----------+-----------------------------------------------------------------+
    | F2-FF    | Reserved                                                        |
    +----------+-----------------------------------------------------------------+
    

    Adapter parity-error registers

    Description

    The adapter parity-error registers are RICPAR0, RICPAR1, and RICPAR2. They are adapter read-only registers. They capture the adapter address and status at which a parity or DRAM access error occurred. The data in these registers is valid only if the PE bit in NMISTAT register is set. This bit is cleared by reading RICPAR2. RICPAR0 and RICPAR1 should be read before RICPAR2 because reading RICPAR2 unlocks all three registers to capture an address, should another error occur.

    Figure 32. Adapter parity error register format

    +--+--+--+--+--+--+--+--+
    |D7|D6|D5|D4|D3|D2|D1|D0|                   Reset Conditions
    +-++-++-++-++-++-++-++-++                   ----------------------------
      |  |  |  |  |  |  |  |                     Power-on Reset : 0000 0000
      |  |  |  |  |  |  |  |                     Command Reset  : SSSS SSSS
      |  |  |  |  |  |  |  |  RICPAR0 RICPAR1 RICPAR2
      |  |  |  |  |  |  |  +--- A0      A8      A16
      |  |  |  |  |  |  +------ A1      A9      A17
      |  |  |  |  |  +--------- A2      A10     A18
      |  |  |  |  +------------ A3      A11     A19  Address
      |  |  |  +--------------- A4      A12     DMA -----------------------
      |  |  +------------------ A5      A13     RA   PS/2   :   -
      |  +--------------------- A6      A14     00   Adapter : 0CH,0EH,10H
      +------------------------ A7      A15     00
    
    Bit descriptions

    RICPAR0 and RICPAR1
    Bits 7-0
    Adapter address bits. The address at which the parity error occurred.
    RICPAR2
    Bits 7 and 6
    Reserved. Always set to zero.

    Bit 5 (RA)
    DRAM access error. If this bit is set to 1, a DRAM access error has occurred. If this bit is set to 0, a parity error has occurred. A DRAM access error is detected when the SSTIC internal 80186 microprocessor SRDY signal is inactive for more than 15 clock cycles. If this occurs:

    DMA
    DMA/microprocessor status. If this bit is set to 1, a DMA cycle created the parity error. If this bit is set to 0, a microprocessor cycle created the error.

    Bits 3-0
    Adapter address bits. The remainder of the address at which the parity error occurred.

    Task register

    Description

    The task register (TREG) is a PS/2 and adapter read/write register. Primarily it passes data from the adapter to the PS/2.

    Writing to this register from either the PS/2 or the adapter raises an interrupt to the PS/2 (maskable by the IE bit in COMREG). The interrupt is cleared by either the adapter or PS/2 reading TREG. This writes FFh to this register.

    A watchdog timer error writes FEh to this register and raises an interrupt to the PS/2 (maskable by the IE bit in COMREG). The interrupt is cleared by either the adapter or the PS/2 reading TREG. Any data written to TREG before or after the watchdog timer error occurred is saved. It may be read (from TREG) after FEh has been read.

    The value of this register is uncertain if the PS/2 and the adapter write to this register at the same time. A channel reset changes the value to FFh.

    Figure 33. Task register format

      +--+--+--+--+--+--+--+--+
      |D7|D6|D5|D4|D3|D2|D1|D0|                    Reset Conditions
      +-++-++-++-++-++-++-++-++                    ----------------------------
        |  |  |  |  |  |  |  |                      Power-on Reset : 1111 1111
        |  |  |  |  |  |  |  |                      Command Reset  : 1111 1111
        |  |  |  |  |  |  |  +--- T0
        |  |  |  |  |  |  +------ T1
        |  |  |  |  |  +--------- T2
        |  |  |  |  +------------ T3               Address
        |  |  |  +--------------- T4               -------------
        |  |  +------------------ T5                PS/2    : 04H
        |  +--------------------- T6                Adapter : 12H
        +------------------------ T7
    
    Bit description
    Bits 7-0
    Task register data. This can be any value except:
    Figure 34. Block diagram of TREG operation
                             +-----------+        +--------+
              FFh ---------->|           |        |Contents|
                             |           |  TREG  |of TREG |-------> To Adapter
    Data Bits 0-7 ---------->|MULTIPLEXER|------->|at time |
                             |           | VALUE  |of Read |-------> To PS/2
              FEh ---------->|           |        |        |
                             +-----------+        +--------+
                                A     A
                                |     |
    Watchdog Error -------------+     |  +----------+----------+--------------+
                                      |  | WGGD     | Data     | TREG Value   |
    Data Present  --------------------+  | Error    | Present  |              |
                                         +----------+----------+--------------+
                                         | No       | No       | FFh          |
                                         | No       | Yes      | Data Bits 0-7|
                                         | Yes      | No       | FEh          |
                                         | Yes      | Yes      | FEh          |
                                         +----------+----------+--------------+
    

    SSTIC end-of-interrupt command register

    Description

    The SSTIC end-of-interrupt register (GEOI) is a command register that can only be written by the adapter; it clears internal interrupt circuitry. It is used after a standard interrupt (INT0 of the 80186 microprocessor) is received. No further standard interrupts can occur until this (EOI) command is given.

    Figure 35. SSTIC end-of-interrupt register format

      +--+--+--+--+--+--+--+--+
      |D7|D6|D5|D4|D3|D2|D1|D0|                    Reset Conditions
      +-++-++-++-++-++-++-++-++                    ---------------------
        |  |  |  |  |  |  |  |                      Power-on Reset : N/A
        |  |  |  |  |  |  |  |                      Command Reset  : N/A
        |  |  |  |  |  |  |  +--- X
        |  |  |  |  |  |  +------ X
        |  |  |  |  |  +--------- X
        |  |  |  |  +------------ X                Address
        |  |  |  +--------------- X                -------------
        |  |  +------------------ X                 PS/2    :  -
        |  +--------------------- X                 Adapter : 16H
        +------------------------ X
    
    Bit descriptions
    Bits 7-0
    Data bits. The value must always be 8000h.

    Interrupt command register

    Description

    The interrupt command register (INTCOM) is a command register that can only be written to by the PS/2. Writing 09h to this register raises interrupt INT0 to the 80186 microprocessor. Repeatedly writing to INTCOM raises multiple interrupts, if the adapter issues GEOI each time.

    Figure 36. Interrupt command register format

      +--+--+--+--+--+--+--+--+
      |D7|D6|D5|D4|D3|D2|D1|D0|                    Reset Conditions
      +-++-++-++-++-++-++-++-++                    ---------------------
        |  |  |  |  |  |  |  |                      Power-on Reset : N/A
        |  |  |  |  |  |  |  |                      Command Reset  : N/A
        |  |  |  |  |  |  |  +--- 1
        |  |  |  |  |  |  +------ 0
        |  |  |  |  |  +--------- 0
        |  |  |  |  +------------ 1                Address
        |  |  |  +--------------- 0                -------------
        |  |  +------------------ 0                 PS/2    : [02H]
        |  +--------------------- 0                 Adapter :   -
        +------------------------ 0
    
    Bit descriptions

    Bits 7-0
    Data bits. The value must always be 09h.

    Chapter 4. X.25 Network Interface

    The general connection of the IBM X.25 Interface Co-Processor/2 to an X.25 public packet-switched network is shown in Figure 37.

    Figure 37. Connecting the adapter to an X.25 public packet-switched network

    +----------------------------------+                       +-----+
    |X.25 Adapter                      |     D-37              |     |
    |              +------------+    +---+  +---+     +---+  +---+   |   |
    |              | X.21 and   |    |   |  |   |     |   |  |   |   |   |X.25
    |              | X.21 bis   +----+   |  |   +-----+   |  |   |DCE+---|
    |              | LOGIC      |    |   |  |   |     |   |  |   |   |   |Network
    |              +------------+    +---+  +---+     +---+  +---+   |   |
    |                                  |                       |     |
    +-------------+  +--+         +----+   |               |   +-----+
                  +--+  +---------+        +-------+-------+
                                                   |
                                         Cable And Connectors
    
    Three network interfaces are available on a common 37-pin D-type male connector on the adapter:
    1. X.21

    2. X.21 bis/V.24(RS232)

      Note: If the HRS signal is required on the RS232 interface, then another cable is required. X.21 bis/V.24 uses the LLBT signal instead of the HRS.

    3. X.21 bis/V.35.
    Each interface fully conforms to the CCITT Recommendation X.25 (1984).

    Four cables are available, each connecting one interface to the data circuit-terminating equipment (DCE) of a packet-switched network. Each cable has a D-37 female connector at the adapter end and one of the following at the DCE end:

    1. D-15 male connector (for X.21).

    2. D-25 male connector (for X.21 bis/V.24).

    3. M/34 block male connector (for X.21 bis/V.35).

    4. M/34 male connector (for X.21 bis/V.35 [France]).
    Using the cables supplied, only one interface may be connected to a DCE at any time.

    Two pins on the adapter end of the cables uniquely identify the type of cable as shown in "Cable identification".


    X.21 interface

    The X.21 interface consists of synchronous full-duplex, balanced, double-current interchange, digital circuits that can operate at signaling rates of up to 64,000 bits per second. The interface fully conforms to CCITT recommendation X.27 (equivalent to recommendation V.11). The interface cable conforms to ISO 4903 at the D-15 connector end. The X.27 recommendation is electrically compatible with EIA RS-422-A. Figure 38 shows the X.21 interface control.

    The data path for the X.21 interface is provided by port 1 of the SCC. The control signals for the interface are provided by port 1 of the CIO. An X.21 transmit-enable signal (X21-TX-EN) is derived from P1-7 of the CIO. This signal must be set to logical 1 before transmission of data.

    The type of interface cable connected can be identified by reading pins 9 and 15 of the D-37 connector (ID0 and ID1). The identifier for an X.21 interface cable is ID0=0, ID1=1. See Table 31 for the identifiers of the other types of cable.

    Figure 38. X.21 interface control

                                                      D37
           Z8030 SCC                               Connector
         +-----------+            +------------+    +----+
         |           |            |            +--->| 10 |T(A)
         |       TxD1+----------->|            +--->| 28 |T(B)
         |           |            |            |<---+ 12 |R(A)
         |           |            |            |<---+ 30 |R(B)
      +=>|       RxD1+----+---<---+            |    |    |
      |  |      _____|    |       |            |    |    |
      |  |      TRxC1+----|----+  |            |    |    |
      |  |           |    |    |  |            |    |    |
      |  |      _____|    |    |  |            |    |    |
      |  |      RTxC1|<---|----+  | X.25       |  +-+  7 |SG
      |  |           |    |    |  | Electrical | GND|    |
      |  |           |    |    |  | Interface  |    |    |
      |  |____  _____|    |    |  | Assembly   |    |    |
      |  |RTSB  SYNC1|<---|-+  |  |            |    |    |
      |  |CTSB       |    | |  |  |            |    |    |
      |  |DCDB       |    | |  |  |            |    |    |
      |  +-----------+    | |  |  |            |    |    |
    ==+                   | |  |  |            |    |    |
      |    Z8036 CIO      | |  |  |            |    |    |
      |  +-----------+    | |  |  |            |<---+ 13 |I(A)
      |  |       P1-3|<---+ |  |  |            |    |    |
      |  |           |      |  |  |            |<---+ 31 |I(B)
      |  |       P1-0|<-----|--|--+            |    |    |
      |  |           |      |  |  |            |<---+ 14 |S(A)
      |  |           |      |  |  |            |    |    |
      |  |       P1-5|<-----|--+--+            |<---+ 32 |S(B)
      |  |           |      |     |            |    |    |
      |  |           |      |     |            +--->| 11 |C(A)
      |  |       P1-6+------|---->|            |    |    |
      |  |           |      |     |            +--->| 29 |C(B)
      +=>|           |      |     |            |    |    |
         |       P1-4+------+     |            |    |    |
         |           |            |            |    |    |
         |           | X.21-TX-EN |            |    |    |
         |       P1-7+----------->|            |    |    |
         |           |            +------------+    |    |
         |           |                              |    |
         |           |               +5V --+----+   |    |
         |           |                    +++  +++  |    |
         |           |                    | |  | |  |    |
         |           |                    +++  +++  |    |
         |       P1-1+---------------------|----+---+  9 |ID0
         |           |                     |        |    |
         |       P1-2+---------------------+--------+ 15 |ID1
         +-----------+                              +----+
    

    X.21 bis/V.24 interface(RS232)

    The X.21 bis/V.24 interface consists of unbalanced, double-current interchange circuits that can operate at signaling rates from 2,400 to 19,200 bits per second. The interface fully conforms to CCITT Recommendation V.28, which is electrically identical to EIA RS-232C. The interface cable conforms to ISO 2110 at the D-25 connector end. Figure 39 shows the X.21 bis/V.24 interface control.

    The data path for the X.21 bis/V.24 interface is provided by port 0 of the SCC. The control signals for the interface are provided by port 0 of the CIO. A select signal, V24 (not V35) is derived from P2-3 of the CIO. This signal must be set to logical 1 before transmission of data. RTS (pin 4) must be set "on" to enable transmission of data at pin 2.

    The type of interface cable connected can be identified by reading pins 9 and 15 of the D-37 connector (ID0 and ID1). The identifier for an X.21 bis/V.24 interface cable is ID0=0, ID1=0. See Table 31 for the identifiers of the other types of cable. At power up, if the cable is installed, the PROM code will read the cable ID and set the select signal appropriately.

    Figure 39. X.21 bis/V.24 interface control

                                                     D-37
           Z8030 SCC                               Connector
         +-----------+            +------------+    +----+
         |           |            |            |    |    |
         |       TxD0+----------->|            +--->|  2 |TXD
         |       ____|            |            |    |    |
         |       RTS0+----------->|            +--->|  4 |RTS
      +=>|       ____|            |            |    |    |
      |  |       RxD0|<-----------+            |<---+  3 |RXD
      |  |       ____|            |            |    |    |
      |  |       CTS0|<-----------+            |<---+  5 |CTS
      |  |       ____|            |            |    |    |
      |  |       DCD0|<-----------+            |<---+  8 |CD
      |  |      _____|            |            |    |    |
      |  |      TRxC0|<-----------+            |<---+ 26 |V24_RX_CLK
      |  |      _____|            |            |    |    |
      |  |      RTxC0|<-----------+            |<---+ 24 |V24_TX_CLK
      |  |      _____|            |            |    |    |
      |  |      SYNC0|-----       |            |    |    |
      |  +-----------+            | X.25       |  +-+  7 |SG
    ==+                           | Electrical | GND|    |
      |    Z8036 CIO       ___    | Interface  |    |    |
      |  +-----------+ V24/V35    | Assembly   |    |    |
      |  |       P2-3+----------->|            |    |    |
      |  |           |            |            |    |    |
      |  |           |            |            |    |    |
      |  |           |   LLBT     |            |    |    |
      |  |       P0-2+------------+            +--->| 27 |LLBT
      |  |           |   DTR      |            |    |    |
      |  |       P0-6+------------+            +--->| 20 |DTR
      |  |           |   RLBT     |            |    |    |
      |  |       P0-3+------------+            +--->| 21 |RLBT
      |  |           |   DSR      |            |    |    |
      +=>|       P0-0+------------+            |<---+  6 |DSR
         |           |   C1       |            |    |    |
         |       P0-4+------------+            |<---+ 22 |CI
         |           |   T1       |            |    |    |
         |       P0-5+------------+            |<---+ 25 |TI
         |           |            +------------+    |    |
         |           |                              |    |
         |           |              +5V ---+----+   |    |
         |           |                    +++  +++  |    |
         |           |                    | |  | |  |    |
         |           |                    +++  +++  |    |
         |       P1-1+---------------------|----+---+  9 |ID0
         |           |                     |        |    |
         |       P1-2+---------------------+--------+ 15 |ID1
         +-----------+                              +----+
    

    X.21 bis/V.35 interface

    The X.21 bis/V.35 interface consists of balanced and unbalanced, double-current, interchange circuits that can operate at signaling rates of up to 56,000 bits per second. Data and timing signals are carried by balanced circuits, which fully conform to CCITT Recommendation V.35. The unbalanced circuits are used for control signals and fully conform to CCITT Recommendation V.28, which is electrically identical to EIA RS-232C. The interface cable conforms to ISO 2593 at the M/34 block connector. Figure 40 shows the X.21 bis/V.35 interface control.

    The data path for the X.21 bis/V.35 interface is provided by port 0 of the SCC. The control signals for the interface are provided by port 0 of the CIO. A select signal V24 (not V35) is derived from P2-3 of the CIO. This signal must be set to logical 0 prior to data transmission. RTS (pin 4) must be "on" to enable data transmission at pins 35 and 17.

    The type of interface cable connected can be identified by reading pins 9 and 15 of the D-37 connector (ID0 and ID1). The identifier for an X.21 bis/V.35 interface cable is ID0=1, ID1=0. See Table 31 for the identifiers of the other types of cable. At power up, if the cable is installed, the PROM code will read the cable ID and set the select signal appropriately.

    Figure 40. X.21 bis/V.35 interface control

                                                      D37
           Z8030 SCC                               Connector
         +-----------+            +------------+    +----+
         |       ____|            |            |    |    |
         |       RTS0+----------->|            +--->|  4 |RTS
         |       ____|            |            |    |    |
         |       CRS0|<-----------+            +--->|  5 |CTS
      +=>|       ____|            |            |    |    |
      |  |       TXD0+----------->|            |<---+ 35 |TXD(A)
      |  |      _____|            |            |    |    |
      |  |      SYNC0+----        |            |<---+ 17 |TXD(B)
      |  |       ____|            |            |    |    |
      |  |       RXD0|<-----------+            |<---+ 37 |RXD(A)
      |  |      _____|            |            |    |    |
      |  |      TRXC0|<-----------+            |<---+ 19 |RXD(B)
      |  |      _____|            |            |    |    |
      |  |      RTXC0|<-----------+            |<---+ 34 |RX CLK(A)
      |  |       ____|            |            |    |    |
      |  |       DCD0|<-----------+            |<---+ 16 |RX CLK(B)
      |  +-----------+            | X.25       |    |    |
    ==+                           | Electrical |<---+ 36 |TX CLK(A)
      |    Z8036 CIO              | Interface  |    |    |
      |  +-----------+            | Assembly   |<---+ 18 |TX CLK(B)
      |  |           |            |            |    |    |
      |  |           |            |            |<---+  8 |CD
      |  |           |  ___       |            |    |    |
      |  |           |  DTR       |            |  +-+    |SG
      |  |       PO-6+----------->|            | GND|    |
      |  |           |  ___       |            |    |    |
      |  |           |  DSR       |            |    |    |
      |  |       P0-0|<-----------+            |    |    |
      |  |           |  __        |            +----+ 20 |DTR
      |  |           |  CI        |            |    |    |
      +=>|       P0-4|<-----------+            |    |    |
         |           |     ___    |            |    |    |
         |           | V24/V35    |            +----+  6 |DSR
         |       P2-3+----------->|            |    |    |
         |           |            |            +----+ 22 |CI
         |           |            +------------+    |    |
         |           |                              |    |
         |           |               +5V --+----+   |    |
         |           |                    +++  +++  |    |
         |           |                    | |  | |  |    |
         |           |                    +++  +++  |    |
         |       P1-1+---------------------|----+---+  9 |D0
         |           |                     |        |    |
         |       P1-2+---------------------+--------+ 15 |D1
         +-----------+                              +----+
    

    Cables and connectors

    A D-37 wrap plug is available for the adapter and each type of cable is supplied with a wrap plug for the connector at the DCE end.

    Cable identification

    Two pins on the D-37 connector are used as a cable identifier. Pull-up resistors on the adapter hold these pins at +5 volts unless they are pulled to ground by connections in the D-37 female connector, as shown in Figure 41.

    Figure 41. Cable ID (X.21 bis/V.24 interface cable connected)

                           -----+------------+------- +5V
                                |            |
                             +--+--+      +--+--+
                             |     |      |     |
                             |     |      |     |
                             |     |      |     |
                             |     |      |     |
                             +--+--+      +--+--+
      +-------------------+     |            |
      |                   |     |            |
      | 8036          ID0 +-----+------------|----/ /----------+
      |                   |                  |                 |
      | CIO           ID1 +------------------+----/ /----------+
      |                   |                                    |
      +-------------------+                                    |
                                                             =====
                                                              ===
                                                               =
    
    Table 31 shows the identifier for the X.21, X.21 bis/V.24 and X.21 bis/V.35 interface cables, and also for the D-37 wrap plug. The X.21 bis/V.35 interface cable and the X.21 bis/V.35 [France] interface cable have the same identifier.

    Table 31. Cable and wrap plug identification

    +================+======+======+
    | Cable          | ID0  | ID1  |
    +================+======+======+
    | X.21 bis/V.24  | 0    | 0    |
    +----------------+------+------+
    | X.21           | 0    | 1    |
    +----------------+------+------+
    | X.21 bis/V.35  | 1    | 0    |
    +----------------+------+------+
    | D-37 Wrap      | 1    | 1    |
    +----------------+------+------+
    
    To test for the presence of a D-37 wrap plug:

    D-37 connector

    The connections to the D-37 for all three interfaces are shown in Figure 42. A wrap plug is supplied to loopback transmitted signals at the D-37 connector (see D-37 wrap plug).

    Figure 42. X.25 network interface connector

    *------*----------------------*--------------*
    | Pin  | Signal Name          | Abbreviation |
    *------+----------------------+--------------*
    |  1   | Reserved             |              |
    |  2   | Transmitted data     | TXD          |
    |  3   | Received data        | RXD          |
    |  4   | Request to send      | RTS          |
    |  5   | Clear to send        | CTS          |
    |  6   | Data set ready       | DSR          |
    |  7   | Signal ground        | GND          |
    |  8   | Carrier detect       | CD           |
    |  9   | Cable ID A           | IDA          |
    | 10   | Transmitted data (A) | T (A)        |
    | 11   | Control (A)          | C (A)        |
    | 12   | Received data (A)    | R (A)        |
    | 13   | Indication (A)       | I (A)        |
    | 14   | Transmit clock (A)   | S (A)        |
    | 15   | Cable ID 1           | IDB          |
    | 16   | Receive clock (B)    | RX CLK (B)   |
    | 17   | Transmitted data (B) | TXD (B)      |
    | 18   | Transmit clock (B)   | TX CLK (B)   |
    | 19   | Received data (B)    | RXD (B)      |
    | 20   | Data terminal ready  | DTR          |
    | 21   | Remote loopback test | RLBT         |
    | 22   | Call indicate        | CI           |
    | 23   | Reserved             |              |
    | 24   | Transmit clock       | TX CLK       |
    | 25   | Test indicate        | TI           |
    | 26   | Receive clock        | RX CLK       |
    | 27   | Local loopback test  | LLBT         |
    | 28   | Transmitted data (B) | T (B)        |
    | 29   | Control (B)          | C (B)        |
    | 30   | Received data (B)    | R (B)        |
    | 31   | Indication (B)       | I (B)        |
    | 32   | Transmit clock (B)   | S (B)        |
    | 33   | Reserved             |              |
    | 34   | Receive clock (A)    | RX CLK (A)   |
    | 35   | Transmitted data (A) | TXD (A)      |
    | 36   | Transmit clock (A)   | TX CLK (A)   |
    | 37   | Received data (A)    | RXD (A)      |
    *------*----------------------*--------------*
    

    X.21 interface cable

    The X.21 interface cable is 3 meters long. It has a D-37 female connector at the adapter end and a D-15 male connector at the DCE end. The cable conforms to Underwriters' Laboratory specification UL 2943.

    Figure 43 shows the X.21 interface cable. A wrap plug is supplied to perform local loopback tests at the D-15 connector.

    Figure 43. X.21 interface cable

      D-37               D-15
    Connector         Connector
    +-------+         +-------+
    |       |         |       |
    |T(A) 10+---------+2  T(A)| Transmitted data (A)
    |       |         |       |
    |C(A) 11+---------+3  C(A)| Control (A)
    |       |         |       |
    |R(A) 12+---------+4  R(A)| Received data (A)
    |       |         |       |
    |I(A) 13+---------+5  I(A)| Indicator (A)
    |       |         |       |
    |S(A) 14+---------+6  S(A)| Transmit clock (A)
    |       |         |       |
    |GND   7+----+----+8  GND | Signal ground
    |       |    |    |       |
    |T(B) 28+----|----+9  T(B)| Transmitted data (B)
    |       |    |    |       |
    |C(B) 29+----|----+10 C(B)| Control (B)
    |       |    |    |       |
    |R(B) 30+----|----+11 R(B)| Received data (B)
    |       |    |    |       |
    |I(B) 31+----|----+12 I(B)| Indicator (B)
    |       |    |    |       |
    |S(B) 32+----|----+13 S(B)| Transmit clock (B)
    |       |    |    |       |
    |ID0   9+----+    |       |
    |       |         |       |
    +-------+         +-------+
    

    X.21 bis/V.24 interface cable

    The X.21 bis/V.24 interface cable is 3 meters long. It has a D-37 female connector on the adapter end and a D-25 male connector at the DCE end. The cable conforms to Underwriters' Laboratory Specification UL 2464.

    The X.21 bis/V.24 interface cable is shown in Figure 44. A wrap plug is supplied to perform local loopback tests at the D-25 connector.

    Figure 44. X.21 bis/V.24 interface cable

        D-37                D-25
     Connector           Connector
    +---------+         +---------+
    |         |         |         |
    |TXD     2+---------+2  TXD   | Transmitted data
    |         |         |         |
    |RXD     3+---------+3  RXD   | Received data
    |         |         |         |
    |RTS     4+---------+4  RTS   | Request to Send
    |         |         |         |
    |XTS     5+---------+5  CTS   | Clear to send
    |         |         |         |
    |DSR     6+---------+6  DSR   | Data set ready
    |         |         |         |
    |GND     7+----+----+7  GND   | Signal ground
    |         |    |    |         |
    |CD      8+----|----+8  CD    | Carrier detect
    |         |    |    |         |
    |TX CLK 24+----|----+15 TX CLK| Transmit clock
    |         |    |    |         |
    |RX CLK 26+----|----+17 RX CLK| Receive clock
    |         |    |    |         |
    |LLBT   27+----|----+18 LLBT  | Local Loopback test
    |         |    |    |         |
    |DTR    20+----|----+20 DTR   | Data terminal ready
    |         |    |    |         |
    |RLBT   21+----|----+21 RLBT  | Remote loopback test
    |         |    |    |         |
    |CI     22+----|----+22 CI    | Call indicate
    |         |    |    |         |
    |TI     25+----|----+25 TI    | Test indicate
    |         |    |    |         |
    |ID0     9+----+    |         |
    |         |    |    |         |
    |ID1    15+----+    |         |
    |         |         |         |
    +---------+         +---------+
    

    X.21 bis/V.35 interface cable

    The X.21 bis/V.35 interface cable is 3 meters long. It has a D-37 female connector at the adapter end and a M/34 block connector on the DCE end. The cable conforms to Underwriters' Laboratory specification UL 2493.

    Figure 45 shows the X.21 bis/V.35 interface cable. A wrap plug is supplied to perform local loopback tests at the M/34 connector.

    Figure 45. X.21 bis/V.35 interface cable

      D-37 Connector            M/34 Connector
    +---------------+         +---------------+
    |               |         |               |
    | GND         7 +----+----+ B  GND        | Signal Ground
    |               |    |    |               |
    | RTS         4 +----|----+ C  RTS        | Request to send
    |               |    |    |               |
    | CTS         5 +----|----+ D  CTS        | Clear to send
    |               |    |    |               |
    | DSR         6 +----|----+ E  DSR        | Data set ready
    |               |    |    |               |
    | CD          8 +----|----+ F  CD         | Carrier detect
    |               |    |    |               |
    | DTR        20 +----|----+ H  DTR        | Data terminal ready
    |               |    |    |               |
    | CI         22 +----|----+ J  CI         | Call indicate
    |               |    |    |               |
    | TXD (A)    35 +----|----+ P  TXD (A)    | Transmitted data (A)
    |               |    |    |               |
    | RXD (A)    37 +----|----+ R  RXD (A)    | Received data (A)
    |               |    |    |               |
    | TXD (B)    17 +----|----+ S  TXD (B)    | Transmitted data (B)
    |               |    |    |               |
    | RXD (B)    19 +----|----+ T  RXD (B)    | Received data (B)
    |               |    |    |               |
    | RX CLK (A) 34 +----|----+ V  RX CLK (A) | Receive clock (A)
    |               |    |    |               |
    | TX CLK (A) 36 +----|----+ Y  TX CLK (A) | Transmit clock (A)
    |               |    |    |               |
    | RX CLK (B) 16 +----|----+ X  RX CLK (B) | Receive clock (B)
    |               |    |    |               |
    | TX CLK (B) 18 +----|----+ AA TX CLK (B) | Transmit clock (B)
    |               |    |    |               |
    | ID1        15 +----+    |               |
    |               |         |               |
    +---------------+         +---------------+
    

    Local loopback-test plugs

    The following wrap plugs are supplied for local loopback tests in accordance with CCITT Recommendation X.150:

    D-37 wrap plug

    The D-37 wrap plug is used to test local loopback at the D-37 connector on the adapter. It has a cable identifier of ID0=1, ID1=1. See "Cable identification" for a method of distinguishing between an open circuit and the presence of a D-37 wrap plug.

    The pin assignment of the D-37 wrap plug is shown in Figure 46.

    Figure 46. Pin assignment of D-37 wrap plug

    +------------------------------------------+
    |Signal    Pin no.      Pin no.  Signal    |
    +------------------------------------------+
    | T (B)      28    -      30    R (B)      |    X.21
    | T (A)      10    -      12    R (A)      |
    | C (B)      29    -      31    I (B)      |
    | C (A)      11    -      13    I (A)      |
    | TXD         2    -       3    RXD        |    X.21 bis/V.24
    | RTS         4    -       5    CTS        |
    | DTR        20    -       6    DSR        |
    | LLBT       27    -      25    TI         |
    | RLBT       21    -      22    CI         |
    | TXD(A)     35    -      37    RXD (A)    |    X.21 bis/V.35
    | TXD(B)     17    -      19    RXD (B)    |
    | ID0         9    -      15    ID1        |    Cable ID
    +------------------------------------------+
    

    D-15 wrap plug

    The D-15 wrap plug is used to test loopback at the DCE end of the X.21 interface cable. The pin assignment of the D-15 wrap plug is shown in Figure 47.

    Figure 47. Pin assignment of D-15 wrap plug

    +---------------------------------+
    |Signal Pin         Pin     Signal|
    +---------------------------------+
    |T(B)    9     -      11    R(B)  |
    |T(A)    2     -       4    R(A)  |
    |C(B)   10     -      12    I(B)  |
    |C(A)    3     -       5    I(A)  |
    +---------------------------------+
    

    D-25 wrap plug

    The D-25 wrap plug is used to test loopback at the DCE end of the X.21 bis/V.24 interface cable. The pin assignment of the D-25 wrap plug is shown in Figure 48.

    Figure 48. Pin assignment of D-25 wrap plug

    +---------------------------------+
    |Signal Pin          Pin    Signal|
    +---------------------------------+
    |TXD      2    -       3    RXD   |
    |RTS      4    -       5    CTS   |
    |DTR     20    -       6    DSR   |
    |LLBT    18    -      25    TI    |
    |RLBT    21    -      22    CI    |
    +---------------------------------+
    

    M/34 wrap plug

    The M/34 wrap plug is used to test loopback at the DCE end of the X.21 bis/V.35 interface cable. The pin assignment of the M/34 wrap plug is shown in Figure 49.

    Figure 49. Pin assignment of M/34 wrap plug

    +---------------------------------+
    |Signal Pin          Pin    Signal|
    +---------------------------------+
    |TXD(A)  P     -      R     RXD(A)|
    |TXD(B)  S     -      T     RXD(B)|
    |RTS     C     -      D     CTS   |
    |DTR     H     -      E     DSR   |
    +---------------------------------+
    

    M/34 wrap plug [France]

    The M/34 wrap plug is used to test loopback at the DCE end of the X.21 bis/V.35 [France] interface cable. It is electrically identical to the M/34 wrap plug.


    Chapter 5. Adapter Characteristics

    This chapter describes the physical and electrical characteristics of the IBM X.25 Interface Co-Processor/2 hardware.


    Physical characteristics

    Adapter technology

    The adapter comprises:

    Adapter connectors

    The adapter has two I/O connectors:

    1. PS/2 connector. This is a 116-way edge connector that lets the adapter be plugged into any I/O socket of the PS/2.

    2. 37-pin D-type (D-37) connector. This is the electrical interface from the adapter to the data network. It must be connected to one of the specific electrical interfaces supported, using a cable with an appropriate socket. See Chapter 4. X.25 Network Interface for more details.

    Electrical characteristics

    Table 32. Power requirements.

    +============+===============================+===============================+
    | Supply     | Current (typical)             | Current (maximum)             |
    | voltage    |                               |                               |
    +============+===============================+===============================+
    | +4.78 V to | 1.4 A                         | 1.7 A                         |
    | +5.25 V    |                               |                               |
    +------------+-------------------------------+-------------------------------+
    | +11.46 V   | 33 mA                         | 35 mA                         |
    | to +12.6 V |                               |                               |
    +------------+-------------------------------+-------------------------------+
    | -10.86 V   | 28 mA                         | 42 mA                         |
    | to -13.2 V |                               |                               |
    +------------+-------------------------------+-------------------------------+
    
    The -5 V power consumption is included in the +5 V figure. The -5 V supply is derived from the +5 V supply via a dc-to-dc converter.

    Environmental characteristics

    Product class assignment

    +--------------------+---------+
    | Acoustic class     | Class 2 |
    +--------------------+---------+
    | Environmental class| Class B |
    |                    | G1      |
    |                    | P1      |
    +--------------------+---------+
    | Vibration and      | V2/S2   |
    | shock              |         |
    +--------------------+---------+
    | EMI limit (FCC     | Class A |
    | rules)             |         |
    +--------------------+---------+
    

    Cooling

    The adapter is cooled by the existing airflow provided by the PS/2 unit. There are no additional cooling requirements.

    Heat output

    The heat output of the adapter is approximately 8 watts, based on typical current consumption.


    Usability characteristics

    The usability of the adapter with regard to communication and data transfer is dependent on the communication application software running on the adapter and the overall usability of the PS/2 in which the adapter is installed.


    Chapter 6. PROM Microcode Support


    Support provided

    The PROM microcode provides support for:


    Power-on self-test

    When the PS/2 is powered on, the PROM microcode:

    1. Clears the PROM-ready bit in the SSTIC.

    2. Tests the 80186 microprocessor flags and conditional jumps.

    3. Tests the 80186 microprocessor registers.

    4. Tests the 80186 microprocessor chip-select registers and sets their default values.

    5. Tests low DRAM (approximately the lowest 1.3 KB used by the PROM microcode). Sets the adapter primary status byte (PSB) to busy (C0h).

    6. Tests stack operation and CALL/RETURN instructions.

      Note: A failure at any of steps through or step is unrecoverable. A failure at step can be recoverable or unrecoverable.

    7. Determines the size of installed DRAM and stores the value in TSIZE in PROM work area.

    8. Puts C9C9h in DBIDS in PROM work area.

    9. Puts ABBAh in ABBA and puts the adapter I/O address in IOADR in PROM work area.

    10. Sets hardware configuration descriptor (HCD) to 0.

    11. Waits until the sleep/enable bit in POS2 is set (to ensure all the POS registers have been initialized) and begins power-on self-test (POST) by:
      1. Setting up the entire vector area.

      2. Checking that any errors in the PROM microcode DRAM test were recoverable.

      3. Calling the test processor diagnostic subroutine (to test 80186 microprocessor timers, DMA channels and interrupts).

      4. Calling the Test SSTIC diagnostic subroutine (to test SSTIC registers).

      5. Testing DMA allocation register.

      6. Calling the checksum memory diagnostic subroutine (to checksum PROM).

      7. Calling the test DRAM diagnostic subroutine (to test DRAM not already tested).

      8. Testing the operation of the DRAM parity circuit.

      9. Calling the Test CIO diagnostic subroutine (to test the basic functions of the CIO).

      10. Calling the Test SCC diagnostic subroutine (to test the basic functions of the SCC).

      11. Turning off the error LED if no errors were detected.

        Note: POST terminates immediately it detects an error, the remaining tests of POST are not run, and the error LED remains lit.

    12. Initializes CIO, SCC, 80186 microprocessor, DMA, and timers.

    13. Puts default values in interface block (PSB=C0h).

    14. Puts size of installed DRAM in TSIZE, puts C9C9h in DBIDS, and HCD in interface block.

    15. Puts extended interface ID in TEMP_IDX in PROM work area.

    16. Puts any POST error data in secondary status area of interface block.

    17. Sets PSB to 00h (no errors, not busy) or 30h (recoverable error).

    18. Sets PROM Ready bit.

    Errors

    Errors are classed as either unrecoverable or recoverable.

    Unrecoverable errors

    When the PROM microcode detects an unrecoverable error it immediately terminates the test, disables I/O, and lights the error LED. A failure at any of steps through , or step is unrecoverable.

    A failure at step can be unrecoverable or recoverable. The low DRAM test is run four times and the number of failed attempts noted. If all four attempts fail, the error is considered to be unrecoverable. The PROM microcode disables I/O and flashes the error LED rapidly to identify this particular error.

    If less than four attempts failed, the error is considered to be recoverable.

    Recoverable errors

    When the first recoverable error is detected, POST terminates, and the PROM microcode executes steps through to set up the normal hardware and software environment. Details of the error are logged in a 7-byte table in the secondary status area in the format shown in Table 33.

    No errors

    If no errors were detected in tests 1 through , the PROM microcode sets the primary and secondary status blocks to all zeros and turns off the error LED.

    Table 33. POST error codes

    +====================================+=====+=====+========+=========+========+
    | Test                               | 0   | 1   | 2-3    | 4-5     | 6      |
    +====================================+=====+=====+========+=========+========+
    | 80186 microprocessor internal      | 01  | 01  |        |         |        |
    | devices                            |     |     |        |         |        |
    +------------------------------------+-----+-----+--------+---------+--------+
    | DRAM                               | 01  | 02  | Offset | Segment | Data   |
    +------------------------------------+-----+-----+--------+---------+--------+
    | PROM checksum                      | 01  | 03  |        |         |        |
    +------------------------------------+-----+-----+--------+---------+--------+
    | CIO                                | 01  | 04  |        |         |        |
    +------------------------------------+-----+-----+--------+---------+--------+
    | SCC                                | 01  | 05  |        |         |        |
    +------------------------------------+-----+-----+--------+---------+--------+
    | SSTIC                              | 01  | 06  |        |         |        |
    +------------------------------------+-----+-----+--------+---------+--------+
    | Parity circuits                    | 01  | 07  |        |         |        |
    +------------------------------------+-----+-----+--------+---------+--------+
    | DMA allocation register            | 01  | 08  |        |         |        |
    +------------------------------------+-----+-----+--------+---------+--------+
    
    Byte 0 indicates an error during POST. Byte 1 indicates the device that failed.

    Bytes 2 through 5 give the location of DRAM failure. If the low DRAM test failed this is the location of the last failure. Byte 6 contains the incorrect bit mask (error bits are 1).


    Diagnostic subroutines

    Fifteen diagnostic subroutines are resident in the adapter PROM. They are available for:

    The diagnostic subroutines are independent of the RCM.

    List of diagnostic subroutines

    Number     Function
    ---------------------------------------------------------------
    00h        Tests specified area of DRAM
    01h        Checksums specified area of DRAM
    02h        Returns size of installed DRAM
    03h        Tests timers, DMA channels, and interrupts
    04h        Tests basic function of CIO
    05h        Tests basic function of SCC
    06h        Tests basic function of SSTIC
    07h        Identifies port on electrical interface assembly on adapter
    08h        Reconfigures CIO port
    09h        Reconfigures SCC port
    0Ah        Reconfigures DMA channel
    0Bh        Reconfigures CIO timer
    0Ch        Initializes watchdog timer
    0Dh        Swaps interrupt priorities of SSTIC and SCC/CIO
    0Eh        Identifies X.25 electrical interface assembly on adapter.
    

    General invocation

    The diagnostic subroutines are called by placing the number of the desired subroutine in the AH register and then calling INT FEh. Other registers are used to pass various other parameters.

    General error handling

    The subroutines perform only limited error checking. They set the carry flag to logical 1 if:

    The calling task should check the carry flag on return to see if an error occurred.

    Note: Subroutines do not check that the calling task owns the resource to be tested.

    Test DRAM subroutine

    Invocation

    INT FEh, AH=00h

    Function

    This subroutine tests each byte of a specified block of adapter DRAM for:

    If an error is detected, the subroutine terminates immediately.

    Notes:

    1. Resource ownership is not tested; this subroutine assumes the calling task owns the specified memory block.

    2. This test disables the watchdog timer.

    Entry parameters

    AH
    = 00h
    ES
    = Segment in which to begin testing
    CX
    = Number of paragraphs (16-byte blocks) to test

    Exit parameters

    Carry flag =   0 if no error detected
                   1 if error detected
    

    Errors

    ES:DI
    = Address of detected error
    AL
    = bit pattern at error location

    Registers affected

    ES, AX, BX, CX, DX, SI, DI

    Memory affected

    Tested DRAM

    Example call

    ;assumes memory block 0 allocated before call
    MOV  AH,00h         ;parameter required for DRAM test
    MOV  BX,CS:STOR0SEG ;test segment of memory block 0, set by RCM
    MOV  ES,BX          ;store in ES
    MOV  CX,01h         ;test paragraph 1 of memory block 0
    INT  0FEh           ;request for service
    JC   ERROR_HAN      ;if error, AL=error bits
                        ;and ES:DI=error address
    

    Checksum subroutine

    Invocation

    INT FEh, AH=01h

    Function

    This subroutine performs a byte-additive checksum on a specified area of adapter DRAM. A 16-bit checksum value must be placed in the last two bytes of the specified area. This value is compared with the least significant 16 bits of the sum of all the other bytes. If the two values are not identical, the carry flag is set to 1. This is a cumulative test, no specific error indicators are returned.

    Notes:

    1. Resource ownership is not tested; this subroutine assumes the calling task owns the specified DRAM.

    2. This test disables the watchdog timer.

    Entry parameters

    AH
    = 01h
    ES
    = Segment in which to begin checksum
    CX
    = Number of bytes to checksum (64 KB maximum)

    Exit parameters

    Carry flag =   0 if no error
                   1 if error
    

    Errors

    Checksum failed if carry flag=1

    Registers affected

    None

    Memory affected

    None

    Example call

    ;assumes memory block 0 allocated before call
    MOV  AH,01h         ;parameter required for checksum
    MOV  BX,CS:STOR0SEG ;test segment of memory block in 0, set by RCM
    MOV  ES,BX
    MOV  CX,15          ;check 15 bytes
    INT  0FEh           ;request for service
    JC   ERROR_HAN      ;if error, handle it
    

    Get memory size subroutine

    Invocation

    INT FEh, AH=02h

    Function

    This subroutine returns the size of the installed DRAM in paragraphs (16-byte blocks). The value is read from the PROM work area variable TSIZE at location 0 0408h. TSIZE is calculated during POST.

    Entry parameters

    AH = 02h

    Exit parameters

    AX          =  Number of paragraphs (16-byte blocks) of installed
                   DRAM
    Carry flag  =  0
    

    Errors

    None (carry flag always reset to zero)

    Registers affected

    AX

    Memory affected

    None

    Example call

    MOV  AH,02h  ;parameter required
    INT  0FEh    ;request for service
                 ;after int., AX=size of installed DRAM in paragraphs
    

    Test microprocessor subroutine

    Invocation

    INT FEh, AH=03h

    Function

    This subroutine tests the basic function of the timers, DMA channels and interrupts of the 80186 microprocessor. The calling task must provide a 128-byte block of DRAM for the DMA channel tests. Before terminating, the subroutine reconfigures the microprocessor to its default state.

    This is not an exhaustive test. If any error is detected, the subroutine sets the carry flag and terminates immediately. No specific error indicators are returned.

    Notes:

    1. This subroutine destroys the entire setup of the 80186 microprocessor and must only be called in a diagnostic environment. The adapter must be reinitialized before resuming normal operation.

    2. This subroutine disables the watchdog timer.

    Entry parameters

    AH   =  03h
    DS   =  Segment pointer to 128-byte block to be
            used for DMA test
    SI   =  Offset pointer to 128-byte block to be
            used for DMA test
    

    Exit parameters

    Carry flag =   0 if no error
                   1 if error
    

    Errors

    A basic function failed if carry flag=1

    Registers affected

    None

    Memory affected

    128-byte block used for DMA test

    Example call

    ;assumes memory block zero allocated before call
    MOV  AH,03h           ;parameter required for processor test
    MOV  BX,CS:STOR0SEG   ;DRAM block for DMA test
    MOV  DS,BX
    MOV  SI,0             ;Offset 0 within segment
    INT  0FEh             ;request for service
    JC   ERROR_HAN        ;if error, processor test failed
    

    Test CIO subroutine

    Invocation

    INT FEh, AH=04h

    Function

    This subroutine tests the basic functions of the CIO. If a failure is detected, the subroutine terminates immediately. Before terminating, the subroutine reconfigures the CIO to its default state.

    Notes:

    1. This subroutine destroys the entire setup of the CIO; it must only be called in a diagnostic environment.

    2. This subroutine disables the watchdog timer.

    Entry parameters

    AH
    = 04h
    AL
    = 00h

    Exit parameters
    Carry flag =   0 if test successful
                   1 if failure detected
    

    Errors

    A basic function failed if carry flag=1

    Registers affected

    None

    Memory affected

    None

    Example call

    MOV  AH,04h     ;parameter required
    MOV  AL,00h     ;parameter required
    INT  0FEh       ;request for service
    JC   ERROR_HAN  ;if error, CIO test failed
    

    Test SCC subroutine

    Invocation

    INT FEh, AH=05h

    Function

    This subroutine tests the basic functions of the SCC. If an error is detected, the subroutine terminates immediately. Before terminating, the subroutine reconfigures the SCC and the CIO to their default states.

    This subroutine uses both DMA channels and the PROM work area. The DMA allocation registers must be reinitialized before commencing normal operation.

    Notes:

    1. This subroutine destroys the entire setup of the SCC and CIO; it must only be used in a diagnostic environment.

    2. This subroutine disables the watchdog timer.

    Entry parameters

    AH
    = 05h
    AL
    = 00h

    Exit parameters

    Carry flag =   0 if no test successful
                   1 if failure detected
    

    Errors

    A basic function failed if carry flag=1

    Registers affected

    None

    Memory affected

    PROM work area 0:0416h to 0:041Bh

    Example call
    MOV   AH,05h     ;parameter required
    MOV   AL,00h     ;test SCC
    INT   0FEh       ;request for service
    JC    ERROR_HAN  ;if error, SCC test failed
    

    Test SSTIC subroutine

    Invocation

    INT FEh, AH=06h

    Function

    This subroutine tests access to the registers of the shared storage interface chip (SSTIC). If an error is detected, the subroutine terminates immediately.

    Notes:

    1. This subroutine destroys the setup of the shared storage interface chip. This can affect: The adapter must be reconfigured to its power-on self-test (POST) state after executing this subroutine.

    2. This subroutine disables the watchdog timer.

    Entry parameters

    AH=06h

    Exit parameters

    Carry flag =   0 if no error
                   1 if error
    

    Errors

    A basic function failed if carry flag=1

    Registers affected

    None

    Memory affected

    None

    Example call

    MOV  AH,06h     ;parameter required
    INT  0FEh       ;request for service
    JC   ERROR_HAN  ;if error, test failed
    

    Get communications port identity subroutine

    Invocation

    INT FEh, AH=07h

    Function

    This subroutine is provided for compatibility with earlier releases of the PROM microcode. In earlier releases, this subroutine returns the identity of the ports on the electrical interface assembly fitted to the adapter. In this release, the subroutine returns C9h as the identifier for both ports. C9h is the identifier of the X.25 electrical interface assembly.

    Entry parameters

    AH = 07h

    Exit parameters

    CH
    = C9h
    CL
    = C9h
    Carry flag
    = 0

    Errors

    None (carry flag is always reset to zero)

    Registers affected

    CX

    Memory affected

    None

    Example call

    MOV  AH,07h   ;parameter required
    INT  0FEh     ;request for service
    

    Configure CIO port subroutine

    Invocation

    INT FEh, AH=08h

    Function

    This subroutine resets and reconfigures either port 0 or port 1 of the CIO, only the specified port being affected. The port is reconfigured to its normal reset state, except that the following registers are written to as shown in Table 34.

    Table 34. CIO port registers

    +=============================+================+=============================+
    | Register                    | Reconfiguration| Remarks                     |
    |                             | value          |                             |
    +=============================+================+=============================+
    | Port Mode Specification     | 0000 0110      | Bit port; OR-PEV mode       |
    +-----------------------------+----------------+-----------------------------+
    | Port Handshake Spec.        | 0000 0000      | Ignored - bit port          |
    +-----------------------------+----------------+-----------------------------+
    | Port Data Path Polarity     | 1111 1111      | All inverting               |
    +-----------------------------+----------------+-----------------------------+
    | Port Data Direction         | 0011 1011      | output bits: 7, 6, 2, input |
    |                             |                | bits: 5, 4, 3, 1, 0         |
    +-----------------------------+----------------+-----------------------------+
    | Port Special I/O Control    | 0000 0000      | All normal                  |
    +-----------------------------+----------------+-----------------------------+
    | Port Pattern Polarity       | 0000 0000      | All normal                  |
    +-----------------------------+----------------+-----------------------------+
    | Port Pattern Transition     | 0000 0000      | All disabled                |
    +-----------------------------+----------------+-----------------------------+
    | Pattern mask                | 0000 0000      |                             |
    +-----------------------------+----------------+-----------------------------+
    
    The interrupt pending (IP), the interrupt enable (IE) and interrupt under service (IUS) bits are reset. The port interrupt vector registers are unaffected and the specified port is left disabled.

    Refer to the Zilog Z8036 CIO Counter/Timer and Parallel I/O Unit: Technical Manual for further details of these registers.

    Note: Resource ownership is not tested; this subroutine assumes the calling task owns the specified port.

    Entry parameters

    AH
    = 08h
    AL
    = CIO port (00h for port 0, 01h for port 1)

    Exit parameters

    Carry flag=0

    Errors

    None. Carry flag is always reset to 0.

    Registers affected

    None

    Memory affected

    None

    Example call

    MOV  AH,08h  ;parameter required
    MOV  AL,00h  ;configure CIO port 0
    INT  0FEh    ;request for service
    

    Configure SCC port subroutine

    Invocation

    INT FEh, AH=09h

    Function

    This subroutine reconfigures a specified SCC port. Only the specified port is affected. The port is reconfigured to the normal reset state except that the following registers are written to as shown:

    Register  Reconfiguration Value
    --------  ----------------------------------------------------
    WR0       0001 0000
    WR1       0000 0000
    WR2       0010 0000
    WR3       1100 0000  8 bits/character, receive disabled
    WR4       0100 1100
    WR5       0110 0000  8 bits/character, transmit disabled
    WR6       0000 0000  Address search character
    WR7       0000 0000  Flag character
    WR8       0000 0000  Transmit buffer
    WR9       0000 1001  Enable master interrupt
    WR10      0000 0000  Force NRZ mode
    WR11      0101 0000  Rx and Tx clock from Baud Rate Generator
    WR12      0000 1010  9600 baud
    WR13      0000 0000
    WR14      0000 0011  Select and enable Baud Rate Generator
    WR15      1100 0000  enable Bk and Tx underrun
    
    Refer to the Zilog Z8030/Z8530 Serial Communications Controller: Technical Manual for further details of these registers.

    Note: Resource ownership is not tested; this subroutine assumes the calling task owns the specified SCC port.

    Entry parameters

    AH
    = 09h
    AL
    = SCC port (00h=port 0, 01h=port 1)

    Exit parameters

    Carry flag=0

    Errors

    None. Carry flag is always reset to 0.

    Registers affected

    None

    Memory affected

    None

    Example call

    MOV  AH,09h   ;parameter required
    MOV  AL,00h   ;configure SCC port 0
    INT  0FEh     ;request for service
    

    Configure DMA channel subroutine

    Invocation

    INT FEh, AH=0Ah

    Function

    This subroutine reconfigures a specified DMA channel of the 80186 microprocessor. Only the specified channel is affected. The selected channel is reconfigured to the following state:

    Register             Reconfiguratn Value
    -------------------  ------------------------------
    Source pointer       0040Dh    (PROM work area)
    Destination pointer  0040Dh    (PROM work area)
    Transfer count       0000h     (Move 0 bytes)
    Control word         FE04h     (Memory to memory transfer
                                   with no increment or decrement;
                                   transfer count indicated with
                                   interrupt disabled; no synchronization;
                                   timer request disabled;
                                   stop DMA; byte transfers)
    
    (For more information, refer to the Intel iAPX 86/88, 186/188: User's Manual Hardware Reference.)

    Note: Resource ownership is not tested; this subroutine assumes the calling task owns the specified DMA channel.

    Entry parameters

    AH
    = 0Ah
    AL
    = DMA channel number (00h or 01h)

    Exit parameters

    Carry flag=0

    Errors

    None (carry flag always reset to zero)

    Registers affected

    None

    Memory affected

    None

    Example call

    MOV  AH,0Ah   ;parameter required
    MOV  AL,00h   ;configure DMA channel 0
    INT  0FEh     ;request for service
    

    Configure CIO timers subroutine

    Invocation

    INT FEh, AH=0Bh

    Function

    This subroutine reconfigures either timer 1 or timer 2 of the CIO, without resetting the CIO, or affecting timer 3 or any of the ports. The selected timer is stopped, enabled, and the registers are written to as shown in Table 35.

    Table 35. CIO timers

    +===============================+============+===============================+
    | Register                      | Value      | Description                   |
    +===============================+============+===============================+
    | Mode Specification            | 0000 0101  | Single-cycle, one-shot,       |
    |                               |            | retriggerable                 |
    +-------------------------------+------------+-------------------------------+
    | Command/Status                | 1110 0000  | stop timer, clear IE          |
    +-------------------------------+------------+-------------------------------+
    | Timer Constant MSB            | 1111 1111  | Maximum count                 |
    +-------------------------------+------------+-------------------------------+
    | Timer Constant LSB            | 1111 1111  | Maximum count                 |
    +-------------------------------+------------+-------------------------------+
    | Command/Status                | 0010 0000  | clear IP and IUS              |
    +-------------------------------+------------+-------------------------------+
    
    The interrupt enabled (IE), the interrupt pending (IP), and the interrupt under service (IUS) flags are reset to zero.

    Note: Resource ownership is not tested; this subroutine assumes the calling task owns the specified timer.

    Entry parameters

    AH
    = 0Bh
    AL
    = Timer number (00h for timer 1, 01h for timer 2)

    Exit parameters

    Carry flag=0

    Errors

    Carry flag always reset to 0

    Registers affected

    None

    Memory affected

    None

    Example call

    MOV  AH,0Bh   ;parameter required
    MOV  AL,00h   ;configure hardware timer 1
    INT  0FEh     ;request for service
    

    Configure watchdog timer subroutine

    Invocation

    INT FEh, AH=0Ch

    Function

    This subroutine initializes timer 3 (the watchdog timer) and port 2 of the CIO, without resetting the CIO or affecting the other ports or timers. The subroutine disables the watchdog timer and resets any resulting interrupt.

    After initialization, timer 3 output enable is off, the timer is not running, and the error LED is off.

    For normal operation of the watchdog, timer 3 output enable (EOE) must be set to logical 1 after the timer is started.

    The subroutine writes to timer 3 registers as shown in Table 36. and to port 2 registers as shown in Table 37.

    Table 36. Watchdog timer

    +===============================+============+===============================+
    | Register                      | Value      | Description                   |
    +===============================+============+===============================+
    | Command/Status                | 1110 0000  | Stop timer, clear IE          |
    +-------------------------------+------------+-------------------------------+
    | Mode Specification            | 0010 0101  | Single-cycle, one-shot,       |
    |                               |            | retriggerable, external count |
    |                               |            | disabled, external output     |
    |                               |            | disable                       |
    +-------------------------------+------------+-------------------------------+
    | Timer Constant MSB            | 1111 1111  | Maximum count                 |
    +-------------------------------+------------+-------------------------------+
    | Timer Constant LSB            | 1111 1111  | Maximum count                 |
    +-------------------------------+------------+-------------------------------+
    | Command/Status                | 0010 0000  |                               |
    +-------------------------------+------------+-------------------------------+
    
    Table 37. Port 2 registers
    +===============================+============+===============================+
    | Register                      | Value      | Description                   |
    +===============================+============+===============================+
    | Data Path Polarity            | 0000 1111  | All inverting                 |
    +-------------------------------+------------+-------------------------------+
    | Data Direction                | 0000 1010  | Outputs bits 0 and 2, input   |
    |                               |            | bits 1 and 3                  |
    +-------------------------------+------------+-------------------------------+
    | Special I/O control           | 0000 0000  | Normal                        |
    +-------------------------------+------------+-------------------------------+
    | Port 2 Data Register          | 0000 0001  | LED control bit 2 off, bit 0  |
    |                               |            | on                            |
    +-------------------------------+------------+-------------------------------+
    

    Entry parameters

    AH=0Ch

    Exit parameters

    Carry flag=0
    Watchdog timer is enabled but stopped
    Error LED is off
    

    Errors

    None (carry flag always reset to zero)

    Registers affected

    None

    Memory affected

    None

    Example call

    MOV   AH,0Ch  ;parameter required
    INT   0FEh    ;request for service
                  ;After int, watchdog timer is enabled but stopped
                  ;error LED is off
    

    Switch interrupt priorities subroutine

    Invocation

    INT FEh, AH=0Dh

    Function

    For diagnostic purposes it may be necessary to have the SSTIC interrupt at a higher priority than the SCC/CIO. By default, the SCC and CIO both interrupt at level 0 and the SSTIC interrupts at level 2. This subroutine reverses the interrupt priority levels of the SCC/CIO and the SSTIC.

    Entry parameters

    AH   =  0Dh
    AL   =  00h SCC/CIO interrupt at level 0, SSTIC interrupts
            at level 2
            01h SSTIC interrupts at level 0, SCC/CIO interrupt
            at level 2
    

    Exit parameters

    Carry flag=0

    Errors

    None (carry flag always reset to zero)

    Registers affected

    None

    Memory affected

    None

    Example call

    MOV  AH,0Dh   ;parameter required
    MOV  AL,01    ;give SSTIC higher priority
    INT  0FEh     ;request for service
    

    Get X.25 electrical interface assembly identifier subroutine

    Invocation

    INT FEh, AH=0Eh

    Function

    This subroutine returns C9h, the identifier of the X.25 electrical interface assembly.

    Entry parameters

    AH = 0Eh.

    Exit parameters

    CX
    = C9h
    Carry flag
    = 0

    Errors

    None (carry flag is always reset to 0)

    Registers affected

    CX

    Memory affected

    None

    Example call

    MOV  AH,0Eh  ;parameter required
    INT  0FEh    ;request for service
                 ;After int:
                 ;CX=C9h
    

    PROM services

    PROM services reside in the adapter's read-only storage. These services are accessible to the realtime control microcode (RCM) and adapter tasks.

    General invocation

    PROM Services are invoked through interrupt vectors between INT A0h and CCh.

    List of PROM services

    +===============================================================+============+
    | Function                                                      | Interrupt  |
    |                                                               | Number     |
    +===============================================================+============+
    | Interrupt PS/2                                                | A0h        |
    +---------------------------------------------------------------+------------+
    | Reset an SCC port                                             | A2h        |
    +---------------------------------------------------------------+------------+
    | Access SCC registers                                          | A4h        |
    +---------------------------------------------------------------+------------+
    | Access CIO registers                                          | A6h        |
    +---------------------------------------------------------------+------------+
    | Timer support                                                 | A8h        |
    +---------------------------------------------------------------+------------+
    | Connect DMA channel                                           | AAh        |
    +---------------------------------------------------------------+------------+
    | DMA support                                                   | ACh        |
    +---------------------------------------------------------------+------------+
    | Access DMA registers                                          | AEh        |
    +---------------------------------------------------------------+------------+
    | Stop DMA channel                                              | B0h        |
    +---------------------------------------------------------------+------------+
    | Translate logical to physical address                         | B2h        |
    +---------------------------------------------------------------+------------+
    | Translate segment to page                                     | B6h        |
    +---------------------------------------------------------------+------------+
    | Translate page to segment                                     | B8h        |
    +---------------------------------------------------------------+------------+
    | Point to conversion tables                                    | C0h        |
    +---------------------------------------------------------------+------------+
    | Convert EBCDIC to ASCII                                       | C2h        |
    +---------------------------------------------------------------+------------+
    | Convert ASCII to EBCDIC                                       | C4h        |
    +---------------------------------------------------------------+------------+
    | Add element to ring (intrasegment)                            | C6h        |
    +---------------------------------------------------------------+------------+
    | Remove element from ring (intrasegment)                       | C8h        |
    +---------------------------------------------------------------+------------+
    | Add element to ring (intersegment)                            | CAh        |
    +---------------------------------------------------------------+------------+
    | Remove element from ring (intersegment)                       | CCh        |
    +---------------------------------------------------------------+------------+
    

    Interrupt PS/2 subroutine

    Invocation

    INT A0h

    Function

    This subroutine raises an interrupt request to the PS/2. Options are to wait for a response from the PS/2, or not. This option should be used with caution. This subroutine may be interrupted only if the option to wait for the PS/2 response is selected. Otherwise, this subroutine does not enable interrupts. If the Interrupt ID byte (INTID) indicates a prior request still pending, the (new) request is immediately rejected. (INTID is at offset 0441h in the Interface Block on page 0 of adapter memory.)

    Note: Waiting for PS/2 response while polling may cause long delays.

    Entry parameters

    AL    =  Interrupting task number (1 through 255).
    AH    =  xxxx xxxa (bits 1 through 7 not used).
    a=0,     Do not wait for interrupt response from PS/2.
    a=1,     Wait for interrupt response by continuous monitoring
             the Interrupt ID (INTID) byte
    

    Exit parameters

    AH    =  xxx xxxb (bits 1 through 7 unpredictable).
    b=0,     Interrupt raised to PS/2 normally.
    b=1,     Request rejected because prior interrupt still in process.
    

    Errors

    None.

    Registers affected

    AH.

    Example call

    MOV   AL,01h     ;task 1 to interrupt PS/2
    MOV   AH,00h     ;don't wait for PS/2 response
    INT   0A0h       ;request for service
    TEST  AH,01h     ;if AH=00, no error; if
    JNZ   ERROR_HAN  ;AH=01, error and jump
    

    Reset an SCC port subroutine

    Invocation

    INT A2h

    Function

    This subroutine resets a selected SCC port to the normal reset state.

    Entry parameters

    AH = SCC port (00h=port 0, 00h=port 1)

    Exit parameters

    AH = 00h if no error; 01h if invalid port specified

    Registers affected

    AX, DX

    Example call

    MOV    AH,00h    ;reset SCC port 0
    INT    0A2h      ;request for service
    TEST   AH,01h    ;if AH=00, no error;, if
    JNZ    ERROR_HAN ;AH=01, error and jump
    

    Access SCC registers subroutine

    Invocation

    INT A4h

    Function

    This subroutine accesses either the read registers or the write registers of a specified SCC port.

    The calling task must provide a pointer to a parameter table. The first byte of the table must be the number of registers to be accessed (must not be zero). The remainder of the table consists of pairs of bytes for each register to be accessed.

    The first byte of each pair is a pointer to the register to be accessed. If write access is requested, the second byte must contain the value to be written. If read access is requested, the second byte is overwritten with the value that was read.

    Notes:

    1. Registers WR2 (interrupt vector register) and WR9 (master control register) should not be written to, because changing these registers may give unpredictable results. The subroutine does not check for accesses to these registers because this more than doubles the execution time of this subroutine.

    2. This subroutine does not:

    Entry parameters

    AL=SCC port (00h=port 0, 01h=port 1)
    Bit 15 of AX=0 for write access
    Bit 15 of AX=1 for read access
    DS=segment pointer to parameter table
    SI=offset pointer to parameter table
    

    Exit parameters

    AH
    = 00h if no error
    AH
    = 01h if invalid port specified
    The Parameter table contains the values that were read if read access was requested.

    Registers affected

    AX, SI, BX, CX, DX

    Example call

    ;table used to store the SCC register values
    SCC_RDTA     DB                 02
                 DB                 12,?
                 DB                 13,?
    MOV          AL,00h             ;read port 0 registers
    MOV          AH,80h             ;read request
    MOV          BX,CS              ;COM file implementation
    MOV          DS,BX              ;DS=CS
    MOV          SI,OFFSET SCC_RDTA    ;place values read in table
    INT          0A4h               ;request for service
    TEST         AH,01h             ;if AH=00, no error; if
    JNZ          ERROR_HAN          ; AH=01, error and jump
    

    Access CIO registers subroutine

    Invocation

    INT A6h

    Function

    This subroutine enables, disables, and/or accesses the registers of, either port 0 or port 1 of the CIO. All read registers may be read from, and all write registers (except for the Interrupt vector register and the Command and status register) may be written to.

    The calling task must provide a pointer to a parameter table. The first byte of the table must be the number of registers to be accessed (must not be zero). The remainder of the table consists of pairs of bytes for each register to be accessed.

    The first byte of each pair is a pointer to the register to be accessed. If write access is requested, the second byte must contain the value to be written. If read access is requested, the second byte is overwritten with the value that was read.

    The pointers do not correspond directly with the Z8036 CIO register address specification. The following list gives the pointers for the registers.

       00h  Data register
       01h  Mode specification register
       02h  Handshake register
       03h  Polarity register
       04h  Direction register
       05h  Special I/O register
       06h  Pattern polarity register
       07h  Pattern transition register
       08h  Pattern mask register
       09h  Command/status register (read-only)
       0Ah  Interrupt vector register (read-only)
    
    All registers can be read from or written to unless otherwise stated.

    The subroutine does not allow write access to a register with a pointer greater than 8, or read access to a register with a pointer greater than 10. If access to an invalid register is requested, the subroutine terminates immediately with the CIO unaffected and AH=01h.

    Note: This subroutine does not:

    Entry parameters

    AL   =  CIO port (00h for port 0, 01h for port 1)
    AH   =  00xx xxx0 Disable port
            01xx xxx0 Enable port
            10xx xxx0 Disable port and write registers
            11xx xxx0 Disable port, write registers and enable port
            xxxx xxx1 Read registers
    DS   =  Segment pointer to parameter table
    SI   =  Offset pointer to parameter table
    

    Exit parameters

    AH
    = 00h if no error
    AH
    = 01h if invalid port or register specified
    The parameter table contains the values read, if read access is requested

    Registers affected

    AX, SI, BX, CX, DX

    Example call

    ;READ TABLE FOR CIOREGS
    CIO_RDTA  DB      09          ;number of registers to read
              DB      00,?        ;byte pairs of register
              DB      01,?        ; offsets and register
              DB      02,?        ; values to be read
              DB      03,?
              DB      04,?
              DB      05,?
              DB      06,?
              DB      07,?
              DB      08,?
    
    MOV       AL,01h              ;select port 1
    MOV       AH,01h              ;read port 1 registers
    MOV       BX,CS               ;COM file implementation
    MOV       DS,BX               ;DS=CS
    MOV       SI,OFFSET CIO_RDTA  ;place values read in table
    INT       0A6h                ;request for service
    TEST      AH,01h              ;if AH=00, no error; if
    JNZ       ERROR_HAN           ; AH=01, error and jump
    

    CIO timer support subroutine

    Invocation

    INT A8h

    Function

    This subroutine performs any combination of the following on timer 1 or timer 2 of the CIO:

    Reconfiguration of the cycle mode (continuous or single) and/or the time-out value does not occur until the first trigger after the timer is restarted.

    Entry parameters

    AL =  Selected
    AH =  xxxx xxx1  Activate bit 2; set single or continuous mode
          xxxx x0x1  Stop timer and set single cycle mode
          xxxx x1x1  Stop timer and set continuous cycle mode
    AH =  x1xx xxxx  Activate bit 7; set restart or retrigger
          01xx xxxx  Restart timer (start count from where it left off
                     with same options)
          11xx xxxx  Retrigger timer (reloads count with new options)
    AH =  xx1x xxxx  Activate bit 4; enable/disable interrupts
          xx10 xxxx  Disable timer interrupts
          xx11 xxxx  Enable timer interrupts
    AH =  xxxx xx1x  Read timer count into CX
    CX =  0          Do not change time-out value
    CX <> 0          Set new ttime-out value for CX
                     (in 543-nanosecond increments)
    
    Note: The bits of register AH may be used in any combination and not all possibilities are shown. For example AH=1111 xx10 with CX = 0 will retrigger the timer, enable timer interrupts, and return the current timer count in CX.

    Exit parameters

    AH
    = 00h if no error
    AH
    = 01h if invalid timer specified
    CX
    = Current timer count (when AH=xxxx xx1x)

    Otherwise, CX is unchanged

    Registers affected

    AL, CX, BX, DX

    Example call

    MOV   AL,01h      ;select timer 1
    MOV   AH,0C1h     ;set single cycle, and ;retrigger timer
                      ;with count in CX
    MOV   CX,0500h    ;new timeout=695.04 microsec
    INT   0A8h        ;request for service
    TEST  AH,01h      ;if AH=00, no error; if
    JNZ   ERROR_HAN   ; AH=01, error and jump
                      ;If here, CX=time-out value
    

    Connect DMA channel(s) subroutine

    Invocation

    INT AAh

    Function

    This subroutine connects either or both of the 80186 microprocessor DMA channels to any of the following:

    The subroutine enables one DMA channel to be connected without disturbing the other (provided a valid connection is made).

    Note: This subroutine does not:

    Entry parameters

    AH   =  selected DMA channel (00h=ch 0, 01h=ch 1,
            FFh=both channels)
    AL   =  xxxx aabb
    
    When only a single DMA channel is to be connected, aa is ignored.
    
    When both channels are to be connected at the same time, aa refers to
    DMA channel 1, and bb refers to DMA channel 0.
    
    Values of aa and/or bb may be:
         00: connect DMA channel to SCC port 0 transmitter
         01: connect DMA channel to SCC port 0 receiver
         10: connect DMA channel to SCC port 1 transmitter
         11: connect DMA channel to SCC port 1 receiver
    

    Exit parameters

    AL and AH contain the new and prior value respectively of the 4-bit DMA allocation register.

    AL  = new value=aabb 0000    (aa=DMA channel 1, bb=DMA channel 0)
    AH  = prior value=aabb 0000  (aa=DMA channel 1, bb=DMA channel 0)
    
    aa and bb have the meanings shown above.
    
    Note: If only a single channel is changed, only the bits for that channel are returned.

    Registers affected

    AX

    Example call

    MOV  AH,00h   ;connect DMA channel 0
    MOV  AL,00h   ;to SCC port 0 transmitter
    INT  0AAh     ;request for service
                  ;After int:
                  ;AL=New value of DMA allocation register
                  ;AH=Old value of DMA allocation register
    

    Set up and start DMA channel subroutine

    Invocation

    INT ACh

    Function

    This subroutine sets up and starts one of the two DMA channels of the 80186 microprocessor. It sets up all six registers (for the selected channel) in the DMA control block. It writes to the control word register last, so that the desired DMA operation starts immediately the subroutine terminates.

    The transfer can be in one of the following directions:

    I/O to I/O transfer is not supported. The calling task must provide: This subroutine optionally converts memory addresses from segment:offset format to the physical address required by the 80186 microprocessor DMA registers.

    This subroutine does not check the validity of input parameters. This is the responsibility of the calling task.

    Entry parameters

    AH=cnnx xxxx
    where cnn has the following meanings:
          x00  not valid
          x01  I/O to memory transfer
          x10  memory to I/O transfer
          x11  memory to memory transfer
          0xx  convert memory address(es) to physical address(es)
          1xx  physical address(es) supplied - no conversion necessary
    BX =  DMA
    CX =  I/O
    DX =  I/O
    S =   Seg
    SI =  Off
    
    The parameter table for each of the possible transfers is shown below. The table pointer points to the uppermost parameter.

    Configuration desired Parameter table

    I/O to Memory (segment:offset)
    AH=001x xxxx
    Table pointer + 0 Destination offset
    Table pointer + 2 Destination segment
    Table pointer + 4 Number of bytes/words to transfer

    Memory to I/0 (segment:offset)
    AH=010x xxxx
    Table pointer + 0 Source offset
    Table pointer + 2 Source segment
    Table pointer + 4 Number of bytes/words to transfer

    Memory to Memory (segment:offset)
    AH=011x xxxx
    Table pointer + 0 Source offset
    Table pointer + 2 Source segment
    Table pointer + 4 Destination offset
    Table pointer + 6 Destination segment
    Table pointer + 8 Number of bytes/words to transfer

    I/O to Memory (physical address)
    AH=101x xxxx
    Table pointer + 0 Low 16 bits of destination
    Table pointer + 2 High 4 bits of destination
    Table pointer + 4 Number of bytes/words to transfer

    Memory to I/O (physical address)
    AH=110x xxxx
    Table pointer + 0 Low 16 bits of source
    Table pointer + 2 High 4 bits of source
    Table pointer + 4 Number of bytes/words to transfer

    Memory to Memory (physical address)
    AH=111x xxxx
    Table pointer + 0 Low 16 bits of source
    Table pointer + 2 High 4 bits of source
    Table pointer + 4 Low 16 bits of destination
    Table pointer + 6 High 4 bits of destination
    Table pointer + 8 Number of bytes/words to transfer

    Exit parameters

    AH=xxxx xxxB (bits 1-7 unpredictable)
                  B=0, Normal operation
                  1, Request rejected; invalid request parameters in Ah
    

    Registers affected

    AX, CX, DX, SI

    Example call

    ;REQUIRED DECLARATIONS
    ;
    SCR_BUFF DB 20 DUP(0) ;source buffer
    DES_BUFF DB 20 DUP(0) ;destination buffer
    ;DMA TABLE FOR MEMORY TO MEMORY TRANSFER
    ;
    DMA0_TBL1 DW      OFFSET SRC_BUFF ;source
    SET_CS1   DW      0
              DW      OFFSET DES_BUFF ;destination
    SET_CS2   DW      0
              DW      20h             ;word count
    MOV   BX,0D707h    ;control word
    MOV   DX,0FFC0h    ;address for DMA port 0
    PUSH  CS           ;COM file implementation
    POP   DS           ;DS=CS
    LEA   SI,DMA0_TBL1 ;pointer to DMA table 0
    MOV   AH,60h       ;memory to memory move
    INT   0ACh         ;request for service
    TEST  AH,01h       ;if AH=00, no error; if
    JNZ   ERROR_HAN    ;AH=01, error and jump
    

    Access DMA channel registers subroutine

    Invocation

    INT AEh

    Function

    This subroutine reads from or writes to all registers in the DMA control block for one DMA channel. The calling task must provide a parameter table in the following format:

    Table pointer + 0  Lowest 16 bits of source address
    Table pointer + 2  Highest 4 bits of source address
    Table pointer + 4  Lowest 16 bits of destination address
    Table pointer + 6  Highest 4 bits of destination address
    Table pointer + 8  Byte or word count (depends on control word value)
    Table pointer + 10 control word
    
    The registers are accessed in the following order:
    1. Source pointer
    2. Destination pointer
    3. Transfer count
    4. Control word.
    This subroutine does not check the validity of passed parameters. When writing to the registers, the table must contain data precisely as specified in the Intel manuals. (Source and destination must be physical memory and/or I/O addresses).

    Entry parameters

    AH  bit 7=0    write access requested
        bit 7=1    read access requested
    DX  = address of DMA channel to be accessed
    ES  = segment address pointer to parameter table (read requests only)
    DI  = offset address pointer to parameter table (read requests only)
    DS  = segment address pointer to parameter table (write requests only)
    SI  = offset address pointer to parameter table (write requests only)
    

    Exit parameters

    Returned data in read table if read requested; otherwise, none

    Registers affected

    DX, SI (if write), DI (if read)

    Example call

    ;READ TABLE FOR CHANNEL 0
    MA0_TBL1 DW          ?  ;put values of DMA registers into table
               DW           ?
               DW           ?
               DW           ?
               DW           ?
               DW           ?
    MOV        AH,80h       ;read DMA registers
    MOV        DX,0FFC0h    ;address for DMA port 0
    PUSH       CS           ;COM file implementation
    POP        ES           ;ES=CS
    LEA        DI,DMA0_TBL1 ;pointer to DMA table 0
    INT        0AEh         ;request for service
                            ;After int:
                            ;DMA channel 0 register data read into
                            ;DMA0_TBL1
    

    Stop DMA channel subroutine

    Invocation

    INT B0h

    Function

    This subroutine immediately stops a DMA channel regardless of the type of operation in progress. After a short settling delay, it reads the byte/word count register and returns the value in AX. No parameter checking is done. Unpredictable results may occur if an invalid parameter is passed.

    Entry parameters

    DX =  port address of DMA channel to stop
          FFC0h if DMA channel 0
          FFD0h if DMA channel 1
    

    Exit parameters

    AX = residual byte count

    Registers affected

    AX, DX

    Example call

    MOV    DX,0FFC0h    ;DMA channel 0 selected
    INT    0B0h         ;request for service
                        ;After int:
                        ;AX=residual byte count
    

    Convert logical to physical address subroutine

    Invocation

    INT B2h

    Function

    This subroutine reads a four-byte segment:offset address from memory, converts it into a 20-bit physical address, and overwrites the input with the result. The physical address is also returned in DX and AX.

    Entry parameters

    DS
    = segment of pointer to address to be converted
    SI
    = offset of pointer to address to be converted

    Exit parameters

    Four bytes changed in memory
     
    AX
    = Lowest 16 bits of address
    DX
    = Highest 4 bits of address (000xh)

    Registers affected

    AX, DX

    Example call

    ;REQUIRED DECLARATIONS
    ;BUFFER     DW       100 DUP(0)     ;data buffer
    ;TABLE FOR DMAADDR
    ;
    BUFFER@     DW       OFFSET BUFFER  ;offset of buffer
                DW       00             ;segment of buffer initialized
                                        ;to CS
    PUSH        CS                      ;COM file implementation
    POP         DS                      ;DS=CS
    MOV         SI,OFFSET BUFFER@       ;pointer to address
    INT 0B2h             ;request for service
                         ;After int:
                         ;AX=Lowest 16 bits of result
                         ;DX=Highest 4 bits of result (000xh)
    

    Convert segment to page subroutine

    Invocation

    INT B6h

    Function

    This subroutine converts a memory address from segment and offset notation to page and offset notation. A page may be 8, 16, 32 or 64 KB. Its size is dynamically set by register INITREG3. The returned page number and offset is relative to the current setting of INITREG3 (starting at top of memory).

    Entry parameters

    ES
    = Segment to be converted
    DX
    = Offset to converted

    Exit parameters

    ES
    = Page number
    DX
    = Offset into page

    Registers affected

    AX, BX, DX, ES

    Example call

    MOV   BX,0200h   ;segment to be converted
    POP   ES,BX      ;ES=BX
    MOV   DX,0001h   ;offset to be converted
    INT   0B6h       ;request for service
                     ;After int:
                     ;ES=Page number ; DX=Offset into pagED
    

    Convert page to segment subroutine

    Invocation

    INT B8h

    Function

    This subroutine converts a memory address from page and offset notation into segment and offset notation. The resulting segment is the value nearest to the converted address relative to the current page size (set in INITREG3). The returned offset is always less than 16.

    Entry parameters

    ES
    = Page number to be converted (bits 7-15 not used)
    DX
    = Offset to be converted (bits 13-15 not used)

    Exit parameters

    ES
    = Resulting segment
    DX
    = Resulting offset

    Registers affected

    AX, DX, ES

    Example call

    MOV     BX,0001h   ;page to be converted
    MOV     ES,BX      ;ES=BX
    MOV     DX,0001h   ;offset to be converted
    INT     0B8h       ;request for service
                       ;After int, ES=Segment ; DX=Offset
    

    Pointer to EBCDIC-ASCII tables

    Invocation

    Not applicable

    Function

    This is not a routine. Absolute location 0:0300h contains a segment:offset pointer to the low-address end of the EBCDIC-ASCII conversion tables in PROM. The pointer may be used directly for EBCDIC-to-ASCII conversion; 256 must be added to the pointer for ASCII-to-EBCDIC conversion. The table layout is as follows:

     pointer + 0      00h to FFh    EBCDIC to ASCII
     pointer + 256    00h to 7Fh    ASCII to EBCDIC
     pointer + 384    80h to FFh    ASCII to EBCDIC
    
    The two ASCII-to-EBCDIC sections are identical so that the high-order bit of an ASCII character may be ignored when performing ASCII-to-EBCDIC conversions.

    Entry parameters

    Not applicable

    Exit parameters

    Not applicable

    Registers affected

    Not applicable

    Example

    MOV    AH,42h     ;read vector call
    MOV    AL,0C0h    ;read interrupt vector C0h
                      ;pointer to EBCDIC-to-ASCII table
    INT    56h        ;interrupt RCM
                      ;INT 56 cannot be used until RCM is loaded
    JC     ERROR_HAN  ;if error, AL=error code
                      ;If here: ; ES:DX=Pointer to EBCDIC-ASCII table
    

    Convert EBCDIC string to ASCII subroutine

    Invocation

    INT C2h

    Function

    This subroutine converts an EBCDIC string from memory to an ASCII string also in memory. The calling task must provide pointers to both source and destination string locations; if the pointers are identical, ASCII bytes overwrite the input EBCDIC bytes.

    Entry parameters

    CX
    = Byte count (zero invalid)
    DS
    = Segment pointer of source (EBCDIC) string
    SI
    = Offset pointer of source (EBCDIC) string
    ES
    = Segment pointer of destination (ASCII) string
    DI
    = Offset pointer of destination (ASCII) string

    Exit parameters

    AH =   xxxx xxxB (Bits 1-7 unpredictable)
          where: B=0 if normal operation;
          1 if request rejected due to zero byte count
    Data returned in destination table
    

    Registers affected

    AX, BX, CX, SI, DI

    Example call

    ;data strings to be converted
    CON_EBCDIC DB  00,01,02,03,04,05,06,07,08,09,10
    CON_ASCII DB   11 DUP(?)
    ;destination table of converted string
    MOV    CX,11                   ;string (byte) count
    PUSH   CS                      ;DS=CS
    POP    DS                      ;DS:SI points to EBCDIC string
    MOV    SI,OFFSET CON_EBCDIC
    PUSH   CS                      ;ES=CS
    POP    ES                      ;ES:DI points to destination string
    MOV    DI,OFFSET CON_ASCII
    INT    0C2h                    ;request for service
    TEST   AH,01h                  ;if AH=00, no error;
    JNZ    ERROR_HAN               ;if AH=01, error and jump
                                   ;After int:
                                   ;Conversion values returned in
                                   ;destination table CONV_ASCII
    

    Convert ASCII string to EBCDIC subroutine

    Invocation

    INT C4h

    Function

    This subroutine converts an ASCII string from memory to an EBCDIC string also in memory. The calling task must provide pointers for both source and destination string locations; if both pointers are identical, EBCDIC bytes overwrite the input ASCII bytes

    Entry parameters

    CX
    = Byte count (zero invalid)
    DS
    = Segment pointer of source (ASCII) string
    SI
    = Offset pointer of source (ASCII) string
    ES
    = Segment pointer of destination (EBCDIC) string
    DI
    = Offset pointer of destination (EBCDIC) string

    Exit parameters

    AH =  xxxx xxxB (Bits 1-7 unpredictable)
          where: B=0 normal operation;
          = 1 error, zero byte count in CX
    Data returned in destination table
    

    Registers affected

    AX, BX, CX, SI, DI

    Example call

    ;data strings to be converted
    ALPA       DB        'This is an ASCII string'
    CON_EBCDIC DB     23 DUP(?)
    ;destination table of converted string
    MOV        CX,23            ;string (byte) count
    PUSH       CS               ;DS=CS
    POP        DS               ;DS:SI points to source ASCII string
    MOV        SI,OFFSET ALPHA
    PUSH       CS               ;ES=CS
    POP        ES               ;ES:DI points to destination string
    MOV        DI,OFFSET CON_EBCDIC
    INT        0C4h             ;request for service
    TEST       AH,01h           ;if AH=00, no error; if
    JNZ        ERROR_HAN        ; AH=01,error and jump
                                ;After int:
                                ;Conversion values returned in destination
                                ;table CONV_EBCDIC
    

    Add element to intrasegment ring subroutine

    Invocation

    INT C6h

    Function

    This subroutine adds an element to a ring structure with 16-bit forward and backward pointers. It assumes the existence of one element in the ring. If the ring contains only one element, both the forward and backward pointers for that element point to itself. Register BX is used to indicate the location of the forward pointer within the element. The backward pointer is assumed to be two bytes past the forward pointer (BX+2).

    Entry parameters

    BX  = Displacement of the forward pointer within the element
    DX  = Offset of the element before which the new element is
        to be inserted
    DI  = Offset of the new element to be inserted
    DS  = Segment in which the ring is located
    

    Exit parameters

    None

    Example call

    ;data tables used to set up ring
    START_RNG DW      $            ;Forward pointer
              DW      $-2          ;Forward pointer
              DW      100 DUP(0)   ;Data area
    SEC_ELM DW        $            ;Forward pointer
              DW      $-2          ;Backward pointer
              DW      100 DUP(0)   ;Data area
    MOV       BX,0000              ;pointers at offset 0 in elements
    MOV       DX,OFFSET START_RNG  ;point to element in ring
    MOV       DI,OFFSET SEC_ELM    ;DI points to next element
    PUSH      CS                   ;DS=CS=segment in which ring
                                   ;element is located
    POP       DS      ;INT  0C6h   ;request for service
    

    Remove element from intrasegment ring subroutine

    Invocation

    INT C8h

    Function

    This subroutine removes an element from a ring structure with 16-bit forward and backward pointers.

    Entry parameters

    BX
    = Displacement of the forward pointer within the element
    DI
    = Offset of the element to remove
    DS
    = Segment in which the ring is located

    Exit parameters

    Carry flag  = 1 if error detected
                = 0 if no error
    Zero flag   = 1 if requested element is the last one in the ring
                (not an error) 0 if more than one element in ring
    

    Errors

    Carry flag set if next and/or previous pointers in user element are incorrect.

    Registers affected

    None

    Example call

    SEC_ELM DW                 ;forward pointer
    DW-2                       ;backward pointer
    DW      100 DUP(0)         ;data area
    MOV     BX,0000            ;pointers at offset 0 in elements
    PUSH    CS                 ;DS=CS=segment in which element
                               ;is located
    POP     DS
    MOV     DI,OFFSET SEC_ELM  ;offset of ring element
    INT     0C8h               ;request for service
    JC      ERROR_HAN          ;if error, handle it
    JZ      LAST_ELEMENT       ;if this is last element
    

    Add element to intersegment ring subroutine

    Invocation

    INT CAh

    Function

    This subroutine adds an element to a ring structure with 32-bit forward and backward pointers. It assumes the existence of one element in the ring. If the ring contains only one element, both the forward and backward pointers for that element point to itself. Register BX is used to indicate the location of the forward pointer within the element. The segment of the forward pointer is at BX+2. The offset of the backward pointer is at BX+4 and the segment of the backward pointer is at BX+6.

    Entry parameters

    BX      =  Displacement of the forward pointer within the element
    ES:DX   =  Location of the element before which the new element
               is inserted
    DS:DI   =  Location of the new element to insert
    

    Exit parameters

    None

    Registers affected

    None

    Example call

    ;data tables required to set up a ring
    START_RNG DW $                 ;forward pointer offset
               DW   0              ;forward pointer segment
               DW   $-4            ;backward pointer offset
               DW   0              ;backward pointer segment
               DW   100 DUP(0)     ;data area
    SEC_ELEM DW  $                 ;forward pointer offset
               DW   0              ;forward pointer segment
               DW   $-4            ;backward pointer offset
               DW   0              ;backward pointer segment
               DW   100 DUP(0)     ;data area
    MOV        BX,0000             ;pointers at offset 0 in elements
    MOV        AX,CS               ;DS=CS=segment of next ring element
    MOV        ES,AX
    MOV        DX,OFFSET START_RNG ;DX=offset of next ring element
    MOV        DS,AX               ;ES=CS=segment of element to add
    MOV        DI,OFFSET SEC_ELM  DX=offset of ring element to add
    INT        0CAh                ;request for service
    

    Remove element from intersegment ring subroutine

    Invocation

    INT CCh

    Function

    This subroutine removes an element of a ring structure with 32-bit forward and backward pointers.

    Entry parameters

    BX         = Displacement of the forward pointer within the element
    DS:DI      = Offset of the element to remove
    

    Exit parameters

    Carry flag =  1 if any errors are detected;
                  0 if no errors Zero flag=1 if requested element was the
                  last one in the ring (not an error);
                  0 if more than one element in ring
    

    Errors

    Carry flag set if next and/or previous pointers in user element are incorrect

    Registers affected

    None

    Example call

    SEC_ELM   DW   $            ;forward pointer
              DW   0
              DW   $-2          ;backward pointer
              DW   100 DUP(0)   ;data area
              MOV  BX,0000      ;forward pointer at offset 0
              MOV  AX,CS        ;DS=CS=segment of ring
              MOV  DS,AX        ;element to remove
    MOV       DI,OFFSET SEC_ELM ;offset of element to remove
    INT       0CCh              ;request for service
    JC        ERROR_HAN         ;if error, handle it
    JZ        LAST_ELEMENT      ;if last element in queue
    

    Bootstrap loader subroutine

    The bootstrap loader first initializes:

    It then waits for an interrupt from the PS/2. The RCM is task zero. When an interrupt occurs the loader checks the task number of the interrupting task. If the task number is other than zero, the loader: The bootstrap loader supports only the Initialization, Load task, Start task, and Free buffer commands. All other commands cause an invalid command error.

    Dump facility

    The PROM microcode contains two routines to enable a dump of memory, microprocessor registers, and I/O ports. After using the dump facility, the hardware of the adapter must be reset and the microcode reloaded before normal use can be continued.

    Dump1 subroutine

    Dump1 is entered through location FC003h. It performs the following:

    Dump2 subroutine

    Dump2 is entered via the jump vector at FC006h in PROM. It performs the following:


    Chapter 7. Glossary

    B

    bis
    Describes a secondary recommendation as an alternative to a primary recommendation.

    bps
    Bits per second. This is used to describe data transfer rates.

    C

    call-accepted packet
    The packet type that a DTE transmits after receiving an incoming-call packet to show acceptance of the call.

    call request packet
    The packet type that the calling DTE transmits to request the network to establish a virtual call to the remote DTE whose network address is specified in the packet.

    cause code
    A one-byte code present in clear and reset packets.

    CCITT
    International Telegraph and Telephone Consultative Committee. An organization of common carriers and PTTs that recommends standards for the interconnection of communications equipment.

    CIO
    Counter/timer and parallel I/O port. The device used on IBM X.25 Interface Co-Processor/2 is the Zilog 8036.

    clear indication packet
    The packet type a DCE transmits to a DTE to signal that a virtual call has been cleared. Cause code and diagnostic code bytes present on the packet may show the reason for the clearing.

    closed user group
    A group of network subscribers that can communicate with one another, but whose access is normally barred to and from all other subscribers of the service. Many networks offer closed user groups with incoming and outgoing access allowed.

    communications co-processor
    A hardware adapter that controls the physical link to the network. It has intelligence and processing power to support additional communications-related functions.

    D

    data packet
    The packet used for data exchange on a virtual circuit. The logical channel identifier in the data packet header shows the origin or destination of the data. Sequence numbers in the header allow bidirectional flow control and error checking. The Q, D, and M-bits in the packet header perform special control functions.

    DCE
    Data circuit-terminating equipment. The network equipment that provides the physical connection to which the communications adapter is attached.

    delivery confirmation bit (D-bit)
    A bit in the data-packet header that instructs the network to wait until delivery to the remote DTE has been confirmed before confirming delivery to the sending DTE. Usually, confirmation is returned to the sending DTE when its packets have been transmitted to the network.

    diagnostic code
    A one-byte code that may be present on clear or reset request packets.

    DMA
    direct memory access

    DRAM
    dynamic random access memory. IBM X.25 Interface Co-Processor/2 has 512 KB of DRAM.

    DTE
    Data terminal equipment. That part of a data station that serves as a data source, data sink, or both.

    duplex link
    A communications line that can simultaneously send and receive data.

    F

    flag sequence
    A unique bit sequence used to delimit the beginning and ending of a frame. A single flag is sufficient to end one frame and begin another.

    frame
    The contiguous sequence of eight-bit bytes delimited by beginning and ending flags. Frames are used to perform control functions, data transfers, and transmission checking on the link.

    frame level
    See X.25 link level.

    H

    half-duplex link
    A communications line that can transfer data in only one direction at a time.

    handshake
    Any protocol sequence that must be executed before productive data transfer can take place.

    HDLC
    High-level data-link control. This is a subset of SDLC.

    I

    IB
    interface block.

    incoming call packet
    The packet type that the DCE transmits to the DTE to show that a remote DTE has initiated a virtual call. The calling DTE's network address may be on the packet. There may also be facility codes and call user data.

    ISO
    International Organization for Standardization. A voluntary activity of the national standardization organization of each member country.

    L

    LAP (link access procedures)
    The link level elements used for data interchange between data circuit-terminating equipment (DCE) and data terminal equipment (DTE) operating in user classes of service 8 to 11, as specified in CCITT Recommendation X.1.

    LAPB (link access protocol - balanced)
    A protocol used for accessing an X.25 network at the link level. LAPB is a duplex, asynchronous, symmetric protocol, used in point-to-point communication. It supersedes the earlier LAP protocol.

    LEPB
    Low-end parallel bus. The bus architecture of IBM PC and PS/2 computers.

    link level
    See X.25 link level.

    logical channel
    A channel across which virtual calls are placed. When subscription is made to a network, the number of logical channels needed is specified. Twenty is the maximum supported by the adapter code. Logical channels are assigned statically to permanent virtual circuits or dynamically to virtual calls.

    M

    more data bit (M-bit)
    A bit in a data packet header showing that the next data packet being sent over a logical channel is logically concatenated to the previous data packet transmitted over that channel.

    N

    network user address (NUA)
    A field of up to 15 binary-coded decimal digits showing the DTE. On a call request packet it shows the destination address; on an incoming call packet it shows the originating address.

    O

    octet
    A group of eight bits (also known as a byte).

    optional network facilities
    Facilities a network user may request when establishing a virtual circuit.

    P

    packet
    A data transmission information unit. A header on the front shows the destination of the packet. Commonly used packet lengths are 128 or 256 bytes.

    packet switching
    The routing of data packets to the destination DTE. Packet switching differs from circuit switching in that network transmission resources are allocated dynamically as needed for a specific packet transmission.

    permanent virtual circuit (PVC)
    A permanent virtual circuit is a static point-to-point logical connection between two DTEs. Call establishment and clearing protocol are therefore not required. It is the packet network equivalent of a leased line.

    POST
    Power-on self-test. These are the adapter diagnostics that are performed when the adapter is reset or powered on.

    protocol
    A convention or rule governing the format and control of transmission between two programs. Protocols exist to make communications orderly and efficient.

    PSDN (packet-switched data network)
    A communications network that uses packet switching as a means of transmitting data.

    PROM
    Programmable read-only memory. This term covers all types of programmable read-only memory. IBM X.25 Interface Co-Processor/2 has 16KB of PROM.

    PROM services
    A local basic input/output system

    PSB
    Primary status byte.

    PTT
    Post Telephone and Telegraph Administration.

    Q

    qualifier-bit (Q-bit)
    A bit in the data packet header showing the type of information contained in the packet. 1 for data and 0 for control information.

    R

    RCM
    Realtime control microcode. Firmware supplied with the adapter hardware.

    ready state
    A logical channel state. A logical channel is in the ready state when no call is established, or is being established, on the logical channel. The logical channel is ready to be assigned to an Incoming Call or a Call Request.

    Recommendation X.25
    The CCITT document that outlines standards for the connection of processing equipment operating in packet mode to a public data network.

    Reset procedure
    A procedure, using the reset request and reset confirmation packets, that allows a DTE to reinitialize the flow control procedure on a logical channel. Data and interrupt packets in transit at the time of resetting may be discarded, but the connectivity of the logical channel is preserved.

    Restart procedure
    A procedure used by the DTE or DCE to clear all virtual calls and reset all permanent virtual circuits.

    RM/OSI
    Reference model/Open System Interconnection defined by ISO.

    S

    SCC
    Serial communications controller. The device used on IBM X.25 Interface Co-Processor/2 is the Zilog 8030.

    SDLC
    Synchronous data-link control. An IBM standard for serial data transmission.

    SSTIC
    Shared storage interface chip. The specific name given to the gate array on IBM X.25 Interface Co-Processor/2.

    SVC
    Supervisor call.

    switched virtual circuit (SVC)
    See Virtual Call.

    T

    tariff
    The network charges a user for sending packets. The tariff is usually based on the number of packets sent over the network.

    V

    Virtual Call
    In addition to the protocols for transferring data that are available to a permanent virtual circuit, additional protocols must be followed to allow for the dynamic setting-up and clearing of the virtual call. It is the packet network equivalent of a dialled line. Also called "Switched Virtual Circuit (SVC)".

    virtual circuit
    A virtual circuit is a logical, duplex, point-to-point connection between two DTEs. Data and signals may be transferred on a virtual circuit according to protocols. A virtual circuit only requires network transmission resources when data is actually transmitted.

    V.24
    A CCITT Recommendation that lists definitions for interchange circuits between Data Terminal Equipment and Data Communicating Equipment.

    V.28
    A CCITT Recommendation that specifies electrical characteristics for unbalanced double-current interchange circuit.

    V.35
    A CCITT Recommendation for data transmission at 48 KBps using 60 to 108 kHz group band circuits.

    W

    window
    The maximum number of frames or packets that the DTE at any given time is authorized to transmit and have outstanding. The window is the basic flow control mechanism in X.25 that protects the network from accepting packets faster than they can be accepted by the remote DTE, or frames faster than they can be accepted by the DCE.

    X

    X.21
    A standard that defines the interface between a DCE and a DTE for synchronous operation on a public data network.

    X.21 bis
    An interim standard that allows existing V-series equipment to be connected to public data networks.

    X.25
    See Recommendation X.25.

    X.25 link level (level 2)
    A part of recommendation X.25 that defines the link protocol used to get data accurately and efficiently into and out of the network across the duplex link connections between subscriber's machine and the network node. LAPB is the link access protocol used by the adapter code.

    X.25 network
    A service providing packet-switched data transmission that conforms to Recommendation X.25 adopted by the CCITT.

    X.25 packet level (level 3)
    A part of recommendation X.25 that defines the protocol for establishing end-to-end logical connections between two DTEs and for transferring data on these connections.

    X.25 physical level (level 1)
    A standard that defines the electrical, physical, functional, and procedural methods used to control the physi

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