Content by David L. Beem (original HERE). Edited by Tomáš Slavotínek.
Last update: 19 Jan 2021 (synced with David's version dated 2 Jan 2012).

The CPUID (or "Reset Signature") is an encoded value reported from the chip to denote the particular CPU Family, Series, and Stepping of the CPU. Most Intel 486 CPUs with copyright dates of '92 or later (with the exception of the 486SL CPUs) support retrieving the CPUID at any point ("OTF", or "On-The-Fly") when the processor is operating. Otherwise the CPUID has to be gained from the system BIOS saving the Reset Signature away early on in the boot process. This isn't done by all 486 BIOS versions, but as a general rule IBM PS/2s (and later IBM products) do.

The first digit of the 486 CPUID denotes the processor type on Intel CPUs. Other manufacturers like IBM (Where it is the letter "A") use it as a vendor indication. The only Pentium-class CPUs listed here are the "POD (Pentium Overdrive) for 486" (CPUID 153xh) that fit in an extension of the 486 socket. The "Second CPU" (CPUID 2xxxh) value does not come into definition here & is ignored:

The second digit denotes the CPU Family. This will be "4" for all the 486s on this page, with the sole exception of the PODs that have a Pentium-class core & able to run a Pentium instruction set. In those cases it will be "5".

The third digit denotes the particular 486 processor series, with the exception of the POD CPUs (The PODs multiply the base processor clock by 2.5 and have an onboard Floating Point Unit, or "FPU" math coprocessor):

The fourth digit is an encoded value of the stepping depending on the processor series. I have listed the steppings for the different CPUIDs. In many cases I have only been able to narrow the CPUID and S-spec down to a range of stepping values. On a few Intel 486 processors with L1 cache that can be set to either Write-Through (WT) or Write-Back (WB) modes, the CPU will shift CPUIDs to show which mode the L1 cache is in at the time.

There can be confusion between the CPUID used on some Intel 486 processors, and those of it's competitor's 486 (AMD, Cyrix/TI, & UMC) models. In most cases the emulation of Intel CPUIDs was deliberate: They wanted the software unaware of whether it was running on a true Intel processor or their version. This is undoubtedly why Intel made the OTF CPUID function return a 'Vendor ID' string (Intel's value is "GenuineIntel"). For earlier 486 CPUs not supporting the Vendor ID there is a couple ways to tell the common CPUIDs apart. One is that Intel removed the 'UMOV' instruction that was on the 286 and 386 from their 486 CPUs. It is still present on the AMD models, although it has been made hard to detect in some cases. Cyrix/TI models also don't have the 'UMOV', but there are documented ways of telling them apart from other vendor's CPUs.

The Intel "S-spec" notation (only left off two 486 CPUs rebranded to IBM) is a 5-character marking in the form "S", uppercase letter (usually "X" on the 486 CPUs), digit, digit, digit. It is simply a batch version encoding and doesn't otherwise represent any processor capabilities on it's own. The numbers may not be necessarily ordinal, but for the early 486 CPUs they are somewhat in order of production. Each unit of a particular S-spec always has the same capabilities and CPU stepping, but there may be more than one S-spec for a particular CPUID or stepping. Intel also paired certain S-specs together, the lower value representing one speed and the next representing the other speed.

The 486 steppings cover a few different CPU core types. The original core is usually encoded by an uppercase letter followed by a digit (as in "A2"), although there was single uppercase letters (i.e. "D") at the end of the cycle. Later "SL Enhanced" cores (lower power requirements) are encoded lowercase letter, uppercase letter, digit (as in "aB0"). The last Intel 486 core had only one stepping, "A", that denoted the CPU had either a 8 or 16 KB L1 cache that is settable to Write-Back mode (earlier 486 have an 8 KB L1 cache in Write-Through mode). The POD cores (with two separate 8 KB data & code L1 caches, settable to Write-Back or Write-Through modes) are in a completely different stepping notation much like the early 486s: Uppercase letter-digit.

I know the purpose of only one 486 stepping change, although a little background is needed: When Intel initially produced the 32-bit 80386 (before even the "DX" marking came into place), they had added an instruction that was later removed (The 'XBTS', or 'Extract Bit String'). Since the instruction was only present in the 386 'A' step, some programmers began to check for it in software to know if the CPU was the 'A' step or a later 386 that had some initial bugs fixed. Intel inadvertently selected the same location of the removed 'XBTS' opcode for a new 'CMPXCHG' ('Compare, Exchange') 486 instruction. When the code to detect the 386 'A' step was falsely identifying the 486 chip 'A' step version, the CMPXCHG instruction was moved elsewhere for the 'B' step 486. I am currently working on code to detect the stepping based on the CMPXCHG opcode position when the BIOS CPUID & OTF CPUID (signifying an older 486) are not available.

Further Reading

• Official Intel Processor Identification & CPUID documents
• INT 15h Function C9h - "Get CPU Type and Mask Revision" (by David Beem)