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Documentation
Systems Using the 82385 Controller
82385 64 KB Support PALs
82385 64 KB Support Block Diagram
Documentation
Datasheets
82385 High Performance 32-Bit Cache Controller, Dec 1990 (290143-006)
82385 High Performance 32-Bit Cache Controller, Nov 1989 (290143-004; Advance Information)
82385 High Performance 32-Bit Cache Controller, Jul 1987 (290143-001; Advance Information)
AP-404 80386 Cache Memory Example (231978) (missing)
Patents
US5045998 Method and apparatus for selectively posting write cycles using the 82385 cache controller (Google)
US5125084 Control of pipelined operation in a microcomputer system employing dynamic bus sizing with 80386 processor and 82385 cache controller (Google)
US5129090 System bus preempt for 80386 when running in an 80386/82385 microcomputer system with arbitration (Google)
US5175826 Delayed cache write enable circuit for a dual bus microcomputer system with an 80386 and 82385 (Google)
US5327545 Data processing apparatus for selectively posting write cycles using the 82385 cache controller (Google)
US5450559 Microcomputer system employing address offset mechanism to increase the supported cache memory capacity (Google)
EP0398191A2 Quad word, multiplexed, paged mode and cache memory (Compaq) (Google Patents only)
"Intel provided an application note describing in general terms a method for using a 64 kbyte cache memory with the 82385"
Systems
Model 70 Technical Reference, 4th Ed, Oct 1990
Other
Langston, Jim, "Interfacing to Intel's 82385 Cache Controller", Intel
Corporation, Microcomputer Solutions, May/June 1988, page 20
Systems Using the 82385 Controller
There are four 386DX-based IBM MCA systems that include the 82385 cache
controller:
The three variants with 64 KB cache have to use a few extra components to
support a two-way, set-associative, store-through, 64 KB cache SRAM (for both
instructions and data).
The Type 0 Plus complex is the only one that uses the 82385 in its default
configuration with 32 KB of cache SRAM.
82385 64 KB Support PALs
All 64 KB implementations have six PLCC-20 PAL devices. The IBM Japan
devices use different part numbers compared to the IBM US devices, but they
appear to be directly equivalent. Please note that this has only been partially
verified.
| 5570-Vxx/8580-Axx Planar | 5551-Vxx CPU Module | 8570-Axx CPU Module | Device | Selected Connections |
|---|
| U125 93X4998 PCACHE3R | U26 93X4998 CHE3R | U7 15F7647 | 16L8 | 82385 A21 |
| U100 93X4996 PCACHE11 | U15 93X4996 CHE11 [HS] | U11 15F7645 | 16R8 | 80386 NA#, U21/U12 FCT244 -OE |
| U126 93X4997 PCACHE12 | U22 93X4997 CHE12 | U5 15F7646 | 16R4 | 82385 CWEA#, CWEB#, WBS |
| U? 93X4999 | U14 93X4999 CHE14 | U3 15F7648 | | 82385 BT/R#, READY0#, BRDYEN#; DOE#, F543s -OEAB |
| U84 93X5000 PCACHE15 | U24 93X5000 CHE15 [HS] | U6 15F8374 | 16R8? | 82385 BADS# |
| U85 93X5001 PCACHE16 | U16 93X5001 CHE16 | U4 15F7650 | 16R4 | 80386 NA#, U17/U30 AS373 1Q |
Notes:
[HS] — indicates a heatsink glued to the PAL device
82385 64 KB Support Block Diagram
Source: US5450559 Patent
C1,C2 PAL device
G1-G7 two input AND gates
O1 OR gate
D1 Latch
PAL C1 and PAL C2 provide for a second or hidden memory
cycle.
Note: The diagram above doesn't exactly match the
actual six-PAL implementation.
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