This is a collection of PS/2 and Micro Channel related patents held by IBM
and other companies. If you find any other relevant patents please
Let Us Know.
Gathered by Tomáš Slavotínek and Louis Ohland. Last update: 10 Sep 2022
Patent No.,
Local PDF | Patent Title | Google Patents | Subject, Notes |
|---|
| EP0281999B1 | Data processing system with pluggable option card | [link] | MCA/POS |
| EP0282637B1 | Computer system accepting feature cards | [link] | MCA adapters |
| EP0283580B1 | Computer system with direct memory access channel arbitration | [link] | |
| EP0288607B1 | Computer system having a multi-channel direct memory access arbitration | [link] | |
| EP0343768B1 | Microcomputer system incorporating a cache subsystem using posted writes | [link] | |
| EP0343770B1 | Multi-bus microcomputer system with bus arbitration. | [link] | |
| EP0402054B1 | Command delivery for a computing system | [link] | SCB |
| EP0419004B1 | Computer system with program loading apparatus and loading method | [link] | IBL/IML |
| EP0426330B1 | Enclosure for a computer | [link] | Model 85/95 |
| EP0434267A2 | Shared hardware interrupt circuit for personal computers. | [link] | MCA |
| EP0468625B1 | Personal computer system with protected storage for interface and system utility programs | [link] | |
| EP0472274A1 | Data processing apparatus having connectors to receive system components | [link] | 386SX/DX socket |
| EP0478119B1 | Personal computer system with interrupt controller | [link] | |
| EP0508685A2 | Power-on control system for a computer. | [link] | |
| EP0511769A1 | Method and apparatus for processing interrupts in a computer system | [link] | |
| EP0517406A2 | Computer system for enabling a choice of error detection technologies | [link] | |
| EP0518504B1 | Personal computer with local bus arbitration | [link] | |
| EP0567237A1 | Method and apparatus for increasing usable memory space | [link] | L40SX? |
| EP0576241A1 | Computer system and system expansion unit | [link] | |
| EP0654742A2 | Multiple bus interface | [link] | ISA/MCA/PCMCIA |
| EP0656586A1 | Method and system for switching between a processor upgrade card and a planar processor | [link] | |
| EP0661632A1 | Booting of operating systems in computers | [link] | |
| EP0661638A1 | Method and apparatus for transferring data in a computer | [link] | |
| EP0661640A1 | System and method for accessing data in a computer system including a cache controller and a memory controller connected in parallel | [link] | |
| US4118611 | Buckling spring torsional snap actuator | [link] | Model M K/B |
| US4692691 | Test system for keyboard interface circuit | [link] | |
| US4890219 | Mode conversion of computer commands | [link] | |
| US4901234 | Computer system having programmable DMA control | [link] | |
| US4928237 | Computer system having mode independent addressing | [link] | |
| US5004866 | Self-contained grounding strip | [link] | Model 85/95 chassis |
| US5008829 | Personal computer power supply | [link] | Model 90/95 (and other) |
| US5021922 | Portable personal computer | [link] | Model P70 |
| US5022077 | Apparatus and method for preventing unauthorized access to BIOS in a personal computer system | [link] | |
| US5032952 | Pivoting power supply | [link] | Model 85/95 PSU |
| US5034917 | Computer system including a page mode memory with decreased access time and method of operation thereof | [link] | |
| US5038142 | Touch sensing display screen apparatus | [link] | Touchselect |
| US5038239 | Integrated electronic card-frame assembly for a rigid disk drive | [link] | |
| US5038320 | Computer system with automatic initialization of pluggable option cards | [link] | POS |
| US5040993 | Interchangeable adapter module for electronic devices | [link] | |
| US5043877 | Architecture converter for slave elements | [link] | MCA to EISA adapter bridge |
| US5043931 | Wrap test system and method | [link] | ACPA? |
| US5045998 | Method and apparatus for selectively posting write cycles using the 82385 cache controller | [link] | 80386/82385 |
| US5047898 | Deflectable contact for providing positive surface contact for shielding electromagnetic interference | [link] | |
| US5051096 | Planar board support structure | [link] | Model 85/95 planar |
| US5054360 | Method and apparatus for simultaneous output of digital audio and MIDI synthesized music | [link] | ACPA? |
| US5063496 | Signaling attempted transfer to protected entry point BIOS routine | [link] | |
| US5067041 | Apparatus for reducing electromagnetic radiation from a computer device | [link] | Model 85/95 chassis |
| US5083931 | Device grounding spring | [link] | |
| US5098175 | Removable guide apparatus for a rail-mounted device employed in a computer | [link] | Model 85/95 chassis/DASD |
| US5100215 | Enclosure apparatus for retaining devices within a computer | [link] | Model 85/95 chassis/DASD |
| US5109490 | Data transfer using bus address lines | [link] | MCA: 64-bit streaming |
| US5109506 | Microcomputer system including a microprocessor reset circuit | [link] | |
| US5112119 | Support structure for devices in a computer apparatus | [link] | Model 85/95 chassis/DASD |
| US5119498 | Feature board with automatic adjustment to one of two bus widths based on sensing power level at one connection contact | [link] | MCA adapters |
| US5125080 | Logic support chip for at-type computer with improved bus architecture | [link] | |
| US5125084 | Control of pipelined operation in a microcomputer system employing dynamic bus sizing with 80386 processor and 82385 cache controller | [link] | 80386/82385 |
| US5128995 | Apparatus and method for loading a system reference diskette image from a system partition in a personal computer system | [link] | conv. partition, IBL/IML |
| US5129090 | System bus preempt for 80386 when running in an 80386/82385 microcomputer system with arbitration | [link] | 80386/82385 |
| US5131082 | Command delivery for a computing system for transfers between a host and subsystem including providing direct commands or indirect commands indicating the address of the subsystem control block | [link] | SCB |
| US5136465 | Personal computer with tandem air flow dual fans and baffle directed air cooling | [link] | Model 90 |
| US5136713 | Apparatus and method for decreasing the memory requirements for BIOS in a personal computer system | [link] | 2-stage IBL/IML |
| US5138706 | Password protected enhancement configuration register for addressing an increased number of adapter circuit boards with target machine emulation capabilities | [link] | POS extension |
| US5142447 | Grounding apparatus for rail-mounted devices employed in a computer | [link] | Model 85/95 DASD cage |
| US5146582 | Data processing system with means to convert burst operations into memory pipelined operations | [link] | |
| US5161218 | Memory controller for using reserved DRAM addresses for EMS | [link] | |
| US5162979 | Personal computer processor card interconnect system | [link] | Processor Complex |
| US5170471 | Command delivery for a computing system for transferring data between a host and subsystems with busy and reset indication | [link] | SCB |
| US5170481 | Microprocessor hold and lock circuitry | [link] | |
| US5175822 | Apparatus and method for assigning addresses to SCSI supported peripheral devices | [link] | Spock card edge? |
| US5175826 | Delayed cache write enable circuit for a dual bus microcomputer system with an 80386 and 82385 | [link] | 80386/82385 |
| US5185864 | Interrupt handling for a computing system with logical devices and interrupt reset | [link] | SCB |
| US5187781 | Shared hardware interrupt circuit for personal computers | [link] | |
| US5187792 | Method and apparatus for selectively reclaiming a portion of RAM in a personal computer system | [link] | |
| US5191544 | Personal computer enclosure with shielding | [link] | Model 90 |
| US5193161 | Computer system having mode independent addressing | [link] | |
| US5193170 | Methods and apparatus for maintaining cache integrity whenever a CPU write to ROM operation is performed with ROM mapped to RAM | [link] | |
| US5193174 | System for automatically redirecting information to alternate system console in response to the comparison of present and default system configuration in personal computer system | [link] | Model 85/95 serial console |
| US5210875 | Initial BIOS load for a personal computer system | [link] | IBL/IML |
| US5214695 | Apparatus and method for loading a system reference diskette image from a system partition in a personal computer system | [link] | IBL/IML |
| US5226134 | Data processing system including a memory controller for direct or interleave memory accessing | [link] | complex |
| US5230052 | Apparatus and method for loading BIOS into a computer system from a remote storage location | [link] | |
| US5235602 | Synchronous/asynchronous i/o channel check and parity check detector | [link] | |
| US5237676 | High speed data transfer system which adjusts data transfer speed in response to indicated transfer speed capability of connected device | [link] | MCA: Streaming |
| US5237690 | System for testing adaptor card upon power up and having disablement, enablement, and reconfiguration options | [link] | MCA: SLOTFLAG |
| US5239631 | CPU bus allocation control | [link] | |
| US5241661 | DMA access arbitration device in which CPU can arbitrate on behalf of attachment having no arbiter | [link] | |
| US5245615 | Diagnostic system and interface for a personal computer | [link] | |
| US5255374 | Bus interface logic for computer system having dual bus architecture | [link] | T3+ complex |
| US5265255 | Personal computer system with interrupt controller | [link] | |
| US5276864 | Personal computer with alternate system controller error detection | [link] | |
| US5280588 | Multiple input/output devices having shared address space | [link] | |
| US5287460 | Bus interface circuit for dual personal computer architecture peripheral adapter board | [link] | |
| US5287519 | LAN station personal computer system with controlled data access for normal and unauthorized users and method | [link] | C2 security |
| US5289477 | Personal computer wherein ECC and parity error checking can be selectively chosen for memory elements installed in the system, memory elements enabling selective choice of error checking, and method | [link] | ECC |
| US5293493 | Preemption control for central processor with cache | [link] | |
| US5299315 | Personal computer with programmable threshold FIFO registers for data transfer | [link] | |
| US5301282 | Controlling bus allocation using arbitration hold | [link] | T3+ complex |
| US5307482 | Computer, non-maskable interrupt trace routine override | [link] | |
| US5307491 | Layered SCSI device driver with error handling circuit providing sense data from device directly to the driver on the occurrence of an error | [link] | SCSI ABIOS |
| US5313475 | ECC function with self-contained high performance partial write or read/modify/write and parity look-ahead interface scheme | [link] | ECC |
| US5313592 | Method and system for supporting multiple adapters in a personal computer data processing system | [link] | |
| US5313593 | Personal computer system with bus noise rejection | [link] | |
| US5313627 | Parity error detection and recovery | [link] | T3+ complex |
| US5319770 | Data processing method and apparatus for verifying adapter description file choices | [link] | |
| US5325264 | Device for removing a direct access storage device from a personal computer | [link] | |
| US5325492 | System for asynchronously delivering self-describing control elements with a pipe interface having distributed, shared memory | [link] | |
| US5327531 | Data processing system including corrupt flash ROM recovery | [link] | |
| US5327545 | Data processing apparatus for selectively posting write cycles using the 82385 cache controller | [link] | 80386/82385 |
| US5329634 | Computer system with automatic adapter card setup | [link] | POS for ISA |
| US5333274 | Error detection and recovery in a DMA controller | [link] | T3+ DMA |
| US5341422 | Trusted personal computer system with identification | [link] | C2 security |
| US5341487 | Personal computer having memory system with write-through cache and pipelined snoop cycles | [link] | |
| US5353202 | Personal computer with shielding of input/output signals | [link] | Model 90 (and other) |
| US5353417 | Personal computer with bus interface controller coupled directly with local processor and input/output data buses and for anticipating memory control changes on arbitration for bus access | [link] | |
| US5355489 | BIOS load for a personal computer system having a removable processor card | [link] | Model 90/95 |
| US5375084 | Selectable interface between memory controller and memory SIMMs | [link] | |
| US5379304 | Method and structure for providing error correction code and parity for each byte on SIMM's | [link] | ECC, EOS |
| US5379342 | Method and apparatus for providing enhanced data verification in a computer system | [link] | |
| US5379386 | Micro channel interface controller | [link] | MCA |
| US5379400 | Method and system for determining memory refresh rate | [link] | |
| US5381538 | DMA controller including a FIFO register and a residual register for data buffering and having different operating modes | [link] | T3+ DMA |
| US5381541 | Computer system having planar board with single interrupt controller and processor card with plural processors and interrupt director | [link] | Processor Complex |
| US5388156 | Personal computer system with security features and method | [link] | C2 security |
US5388228
US5506972 | Computer system having dynamically programmable linear/fairness priority arbitration scheme | [link] | |
| US5396597 | System for transferring data between processors via dual buffers within system memory with first and second processors accessing system memory directly and indirectly | [link] | |
| US5396619 | System and method for testing and remapping base memory for memory diagnostics | [link] | POST |
| US5404452 | Personal computer bus and video adapter for high performance parallel interface | [link] | |
| US5410699 | Apparatus and method for loading BIOS from a diskette in a personal computer system | [link] | floppy IBL/IML |
| US5420760 | Microcomputer enclosure with interrupted wedge locking arrangement and shielding liner | [link] | Model 90 (and other) |
| US5423045 | System for distributed power management in portable computers | [link] | L40SX? |
| US5430847 | Method and system for extending system buses to external devices | [link] | |
| US5432939 | Trusted personal computer system with management control over initial program loading | [link] | C2 security |
| US5432946 | LAN server personal computer with unattended activation capability | [link] | remote pwr-on |
| US5442629 | Token ring speed detector | [link] | |
| US5446869 | Configuration and RAM/ROM control of PCI extension card residing on MCA adapter card | [link] | MCA/PCI |
| US5446898 | Method and apparatus for configuring and installing a loadable ABIOS device support layer in a computer system | [link] | |
| US5450559 | Microcomputer system employing address offset mechanism to increase the supported cache memory capacity | [link] | 80386/82385 |
| US5452429 | Error correction code on add-on cards for writing portions of data words | [link] | |
| US5459839 | System and method for managing queue read and write pointers | [link] | |
| US5459842 | System for combining data from multiple CPU write requests via buffers and using read-modify-write operation to write the combined data to the memory | [link] | ECC |
| US5465357 | Method and apparatus for an automated dynamic load of an ABIOS device support layer in a computer system | [link] | |
| US5469577 | Providing alternate bus master other publications with multiple cycles of bursting access to local bus in a dual bus system including a processor local bus and a device communications bus | [link] | Gearbox |
| US5471585 | Personal computer system with input/output controller having serial/parallel ports and a feedback line indicating readiness of the ports | [link] | I/O controller |
| US5477242 | Display adapter for virtual VGA support in XGA native mode | [link] | XGA |
| US5481552 | Method and structure for providing error correction code for 8-byte data words on SIMM cards | [link] | ECC-P |
| US5481709 | Method and apparatus for providing a modular ABIOS device support layer in a computer system | [link] | |
| US5481724 | Peer to peer computer-interrupt handling | [link] | |
| US5481754 | Apparatus and method for bios interface to features in multiple adapter cards in one operation using registers with bits distributed across the adapter cards | [link] | |
| US5495611 | Method and apparatus for dynamic load of an ABIOS device support layer in a computer system | [link] | |
| US5499378 | Small computer system emulator for non-local SCSI devices | [link] | |
| US5500934 | Display and control system for configuring and monitoring a complex system | [link] | LANACS |
| US5504904 | Personal computer having operating system definition file for configuring computer system | [link] | |
| US5504905 | Apparatus for communicating a change in system configuration in an information handling network | [link] | |
| US5509120 | Method and system for detecting computer viruses during power on self test | [link] | |
| US5515474 | Audio I/O instruction interpretation for audio card | [link] | ACPA? |
| US5522064 | Data processing apparatus for dynamically setting timings in a dynamic memory system | [link] | T1+ Mem. Ctrl. |
| US5524267 | Digital I/O bus controller circuit with auto-incrementing, auto-decrementing and non-incrementing/decrementing access data ports | [link] | |
| US5530887 | Methods and apparatus for providing automatic hardware device identification in computer systems that include multi-card adapters and/or multi-card planar complexes | [link] | POS |
| US5537607 | Field programmable general purpose interface adapter for connecting peripheral devices within a computer system | [link] | |
| US5539912 | Computer system having a selectable memory module presence detect information option | [link] | |
| US5541941 | Method and structure for providing automatic parity sensing | [link] | ECC, EOS |
| US5544346 | System having a bus interface unit for overriding a normal arbitration scheme after a system resource device has already gained control of a bus | [link] | T3+ complex |
| US5544334 | Micro channel bus computer system with IDE hard drive interface | [link] | Lacuna |
| US5548786 | Dynamic bus sizing of DMA transfers | [link] | T3+ DMA |
| US5551009 | Expandable high performance FIFO design which includes memory cells having respective cell multiplexors | [link] | T3+ complex |
| US5553306 | Method and apparatus for controlling parallel port drivers in a data processing system | [link] | |
| US5555373 | Inactivity monitor for trusted personal computer system | [link] | C2 security |
| US5557784 | Power on timer for a personal computer system | [link] | |
| US5568611 | Unauthorized access monitor | [link] | Server 95 |
| US5574786 | Securing trusted personal computer system against unauthorized movement | [link] | Model 56/57, Model 76/77 |
| US5586327 | Extended initialization for personal data processing systems | [link] | IPL |
| US5598542 | Method and apparatus for bus arbitration in a multiple bus information handling system using time slot assignment values | [link] | PCI/MCA |
| US5600793 | Method and system of bi-directional parallel port data transfer between data processing systems | [link] | |
| US5630078 | Personal computer with processor reset control | [link] | |
| US5634137 | Method and apparatus for updating system configuration based on open/closed state of computer housing cover | [link] | |
| US5644729 | Bidirectional data buffer for a bus-to-bus interface unit in a computer system | [link] | T3+ complex |
| US5651139 | Protected system partition read/write access on a SCSI controlled DASD | [link] | IBL/IML partition |
| US5655106 | Personal computer with riser connector for expansion bus and alternate master | [link] | |
| US5659696 | Method and apparatus for determining address location and taking one of two actions depending on the type of read/write data transfer required | [link] | T3+ complex |
| US5671372 | Data processing system with microprocessor/cache chip set directly coupled to memory bus of narrower data width | [link] | C5/C8, T4 consideration? |
US5678019
US5829008 | Real-time clock with extendable memory | [link] | |
| US5680288 | Hot plugging of an adapter card | [link] | MCA |
| US5684960 | Real-time ring bandwidth utilization calculator by sampling over a selected interval latch's states set by predetermined bit pattern on the transmission medium | [link] | TR TAP |
| US5692190 | Bios emulation of a hard file image as a diskette | [link] | |
| US5726922 | Assembly for removably connecting data storage devices | [link] | Model 95A RAID bay |
| US5732280 | Method and apparatus for dynamically assigning programmable option select identifiers | [link] | POS |
| US5742758 | Password protecting ROM based utilities in an adapter ROM | [link] | |
| US5754821 | Method and system for providing access to a protected partition of a memory device utilizing a passthru command | [link] | IBL/IML partition |
| US5761533 | Computer system with varied data transfer speeds between system components and memory | [link] | T3+ complex |
| US5765008 | Personal computer with riser card PCI and micro channel interface | [link] | PC 700 riser |
| US5802363 | Bios dynamic emulation of multiple diskettes from a single media | [link] | |
| US5826075 | Automated programmable firmware store for a personal computer system | [link] | flash update |
| US5850562 | Personal computer apparatus and method for monitoring memory locations states for facilitating debugging of post and BIOS code | [link] | |
| US5873129 | Method and apparatus for extending physical system addressable memory | [link] | |
| US5878256 | Method and apparatus for providing updated firmware in a data processing system | [link] | flash update |
| US5898857 | Method and system for interfacing an upgrade processor to a data processing system | [link] | CPU upgrade |
| US5918007 | Trusted personal computer system with limited accessibility | [link] | C2 security |
| US5966728 | Computer system and method for snooping date writes to cacheable memory locations in an expansion memory device | [link] | T3+ complex |
| US5980275 | Electronic circuit board interface mounting bracket | [link] | MCA bracket |