Type 4 "N" Complex

Rf90954a.exe Reference disk for Type 4 Complexes
Rd9095a.exe Common Diagnostics for all 859x / 959x Systems

Type 4 Common Devices
Complex Features
BIOS Updates
   BIOS Levels
   Flashing to BIOS 05 and up from 03 or Lower
FDIV Replacement
Support for Convenience Partition on >3.94GB Drives

"N" / Upgrade 486DX2 66 MHz
   "N" Complex Front
   "N" Complex Back
Memory supported, cache
ECA0002 01291500 Errors
Possible -xNx Overclock?
-xNx Upgrades?


"N" / Upgrade 486DX2 66 MHz (61G2343, FCC ID ANOIBM486C66)

"N" Complex Front *

CR1,2 Diagnostic LEDs
CR3 Schottky Diode B54 (Flash Vpp)
J6 Serial Diagnostics Link to Op Panel
J4 Debug Port
J? SDL POST Diag Jumper
JMP5 Flash ROM Bank Switch
L1 Inductor 47 uH (Flash Vpp)
U3 Flash ROM BIOS 61G2347
U10 Flash ROM BIOS 61G2350
U11 MACH210-12JC CPLD, 61G4030
U19,20,26,38,42 i82490DX Cache SRAM
U22 169-pin LIF Socket for 486DX2-66
U29 i82495DX Cache Controller
U31 40.0000 MHz Osc (Local Bus)
U33 33.3300 MHz Osc (CPU)
U47 50G8192 SynchroStream Controller
U48 MACH210-12JC CPLD, 60G9845
U85 LT1085CT Voltage Regulator
U89 MACH210-12JC CPLD, 61G4032

U85 LT1085CT Adjustable Voltage Regulator with max. output current 3.0 A. The regulator is set to 3.7 (3.75) V and powers the SynchroStream Controller.

Supports 041xh and 043xh CPUIDs. HERE David Beem put some thought into steppings.

"N" Complex Back

Nothing really interesting, mostly just 74xx glue logic and bypass caps. No cache chips on the back side - "N" has only 5 chips (4 + 1 parity) on the component side.

U1 LT1109-12 DC/DC Conv. (Flash Vpp)
C14 Tantalum Cap 10 uF / 20 V (Flash Vpp)

U1, CR3, L1, C14 (plus some other passives) are part of a local 12 V voltage generator. This additional "programming voltage" (Vpp) is required by the Flash memory to perform erase/write operations. Its general topology closely replicates the "Flash Memory VPP Generator" circuit from the LT1109 datasheet (page 1). A local 12 V generator is necessary because the processor complex is supplied with 5 V only.


Memory

RAM:
   PS/2 72-pin SIMMs, ECC or Parity, 70 ns Presence Detect
   Min/Max on system board: 8/64 MB Parity, 8/256 MB ECC

ROM:
   256 KB (2 x 128 KB) Flash ROM

Cache:
   L1: 8 KB (486DX2)
   L2: 128 KB write-back


ECA0002

   If you get Intermittent 01291500 errors and intermittent hangs, or SYS000915 errors under OS/2 using an N complex, FRU 61G2343, then this ECA probably applies.
Note: the upgrade Type 1 DX2-66 FRU 92F0145 is NOT affected.
   To check if your complex is affected, note the manufacturing P/N on a sticker just below the CPU. If the manufacturing number is 82G3513, 06H3368, or 61G4072 with no patch wire on the back [described below], it is affected.
Note: I have a 61G4072 with a patch wire on the front. It seems to work. But the U69 and U60 ICs do not match.
Complexes 06H7263, 06H7264, and 06H7265 with the wire patch are not affected.
Complexes with FRU 06H7266 are not affected. (Ed. New level production?)

Wire Patch on Back
   There are two ICs, U60 and U69. U60 is 74F04D, 14 pin and U69 is 74ABT374D, 20 pin. The patch wire runs from the top left of U69 across to the right, then down to R1, then from the bottom of R1 to the left, where it connects to the bottom right of U60. If your 61G2343 does not match the U69 (74ABT374D) and U60 (74F04D), then this ECA does not apply.


-xNx Overclock?

From Tatsuo Sunagawa:
   The board accepts 40.00 MHz oscillator instead of 33.33 MHz without any changes of BIOS. But with 45.00 MHz, it doesn't work. I don't have same type oscillator, so I'm using square metal package oscillator with socket.
   (Ed. Does this mean an AMD/Cyrix 486DX-80 might work? The 486DX-80 was for systems with a 40 MHz clock... Watch the voltage! The DX-80 was a 3.45 V chip, FAIK...)

-xNx Upgrades?

From Tim Clarke:
Type-4 DX2-66 will take:

  • Intel/IBM DX2-66 (5 V parts, x2 clocking)
  • Intel DX2-66ODPR (5 V parts, x2 clocking)
  • All others *fail* to reach 'logo' screen (presumed BIOS 'sensitivity')

> But is overclocking possible with this?

   Yes, the 'sensitivity' I remarked upon was in relation to x3 clocking ratios and above, *not* increasing the 'base clock' and staying with x2 clocking. My initial reaction is that a 40 MHz x2 (i.e. 80 MHz) chip would work very well, especially those with the 'bigger' 16 KB L1 on-chip cache.

Editor: Please report experiences... Also, do be careful - the parts may be able to take the overclock... Make sure the side fan works. Keep the complex clean.

Current N Upgrade Attempts

   I tried a Socket 3 transplant onto an N (procedure performed by Jim Shorney). At the same time, a 40 MHz oscillator was tried. The 40 MHz oscillator wasn't cooperation. At present, the Socket 3 modified complex will not respond on a 9590. Possibly too crude of a planar?
   Complex refuses to run on a model 90, but came up on an M class 95 planar. Still refused to complete booting with anything other than a DX2-66. Interposer failed to enable booting with a POD. Possible timing or cache related problems.


9595 Server 95 (AKA "Server 95 466") (Type 4 ref. disk)

1NG - 486DX2-66, 16/256 MB (ECC), 540 MB SCSI-2, 2.88 MB floppy
1NT - 486DX2-66, 16/256 MB (ECC), 1 GB SCSI-2, 2.88 MB floppy
1NV - 486DX2-66, 16/256 MB (ECC), 2 GB SCSI-2, 2.88 MB floppy

9595 Server 95 Array (called 95A) (9 drive bays - Type 4 ref. disk)

3NG - 486DX2-66, 16/256 MB (ECC), 3 x 540 MB SCSI-2, 2.88 MB floppy
3NT - 486DX2-66, 16/256 MB (ECC), 3 x 1 GB SCSI-2, 2.88 MB floppy


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