52G9619 1993 BIOS Original Mitsubishi M5M27C201 PLCC32
Note: The M complex has the functional equivalence of the SynchroStream controller, but in discrete chips and it doesn't operate quite as fast as the single-chip solution.
Base Board (sticker 71G6207 or 61G9343)
U27 BIOS ROM Mitsubishi 27C201 (256K x 8)
Base Board Back
To remove the daughtercard you have to first loosen the SCREW on the back side of the high speed connector J2 (see above). Then unlatch the standoff 1 from the front side of the daughtercard (see below). You may also have to push through the other smaller standoff 2. Now you should be able to separate the two boards without any trouble.
Daughtercard (sticker 71G6190)
I have seen one card with the older BIOS 41G9251 ('92) that has NO rework. The three DX50 I have with the new BIOS 52G9619 ('93) all have the rework. Why? Haven't a clue.
Ed: The bodge wires are associated with the additional PAL that was added to the SP1 position on some boards. It connects the array to the rest of the logic.
(Click on picture to enlarge)
The 50-MHz Type 3 complex in a 90/95, has two LEDs; CR1 and CR2. During POST, CR1 comes on momentarily and CR2 stays off. If the LEDs work any other way, suspect that the processor board is defective.
Use the LEDs to help differentiate between
a processor board or a system board failure. If you are
instructed to replace one of the boards, and the problem
still exists, replace the other board (also reinstall
the first board). (Ed.
Reports coming in make me wonder about any of this. If
the board passes diagnostics, and works normally, do you
really care about the LEDs?)
Greatly simplified block diagram of the "M" complex:
Enhanced Memory Parts
Enhanced dual path memory design (Dual Bus Interleave). Although Base 1 allows both the processor and busmasters to access memory concurrently through two paths, the Base 3 and 4 has buffers at both paths to provide better performance. Also the buffer on the adapter side (I/O buffer) uses packet data transfers for writes. This means 16 bytes are collected and this packet is written in one cycle to memory as opposed to writing for every 4 bytes received (as with unbuffered systems).
Why Double Deck?
The "M" is the only "double-decker" complex (if we don't count the Type 1 L2 cache daughtercards).
With this complex IBM introduced a set of new features, so the architecture was quite complex compared to the earlier processor board designs. With the technological processes used it clearly wasn't possible to fit all the required logic to a single board. IBM therefore split the design in half, used the base board for the interface, memory and DMA logic, and moved the CPU subsystem to a daughtercard.
Incompatibility with Network Streamers
The downlevel processor card FRU 57F1597 is identified by the lack of a module in position SP1. This card may cause data loss or undetected change in the:
The upgraded FRU with SP1 is FRU 82G2484 and should be used with these cards.
BIOS stored in EPROM.
Support for >1 GB Disks as IML Drive
The M complex supports >1GB drives as the IML source. No complex BIOS upgrade is needed (or available). However, the SCSI controller needs the enhanced SCSI BIOS of 92F2244 / 92F2245 to IML properly.
More information HERE.
BIOS ROM Burning
Rick Ekblaw plays deep safety:
So, the good news is that you could use
almost any 2Mb PLCC32 EPROM or PROM that you can find to
act as a replacement for the M5M27C201JK as the BIOS
chip in your M complex (where it is only being read by
the system). For programming the EPROM/PROM, you
have to choose a part for which you have appropriate
algorithms in your programmer, because they vary.
H097075 Unsuccessful 50 MHz Processor Installation
Interesting challenge on VCF, the OP was unable to boot with an M on a single serial / single parallel planar. I personally have never had such an issue, but for the love of God...
Display showed CP80, and I9990021, I9990011 the IML codes were related to the wrong IML on the SCSI HD and the wrong refdisk... OP had the correct refdisk, the HD was an 0662-S12 [1,004MB, below 1,024MB], three can Spock [44/45 SCSI BIOS], and of course, the M [comes stock with enhanced complex BIOS]. System complaining about the wrong IML code...
"AH-HA! IT LIVES AT LAST! Swapping the position of jumper J16 solved the issue and got it to finally read from the RefDisk! It only took close to eighteen months to reach this point but man, does it feel good. Thanks for your help with this last hiccup, I never would have guessed I'd need to swap a jumper after installing an M complex."
The RETAIN tip says:
Remove the existing complex, then move the override jumper, [8590 - J10, 8595 - J16], so that it connects the center pin and the pin on the opposite end of the connector. Leave the jumper in this position. [It does not matter if you change the complex before or after moving the jumper].
Note: The system detects any change in the Override Jumper position from the last power on, and if it detects a change, it FORCES it to read the Ref Disk on the next boot -ONLY-. It is a one-shot wonder.
The system will detect this change and read the Initial Machine Load (IML) image from the new reference diskette.
False ARTIC diag error
SYMPTOM: When running diagnostics on the
ARTIC Portmaster Adapter/A in an 8590 or 8595 with the
486/50MHZ processor card installed, a false 14220, E0DE
error may occur.
I was all set to install a Trinity PowerStacker 5x86 133 MHz on my DX 50 in the 9595-OMT. I for some reason decided to RTFM while having a cuppa. They say the PowerStacker will not work with DX 50. What CPU can I use to juice up the DX 50?