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rf90952a Reference Disk for Type 2
07G0463.BIN Original BIOS for earlier Hs - seen mostly with 92F1428 DMA Controller
Specifications
Japanese 486SX 25 MHz / 486DX2 50 MHz Complex Specifications Memory RAM: ROM: Cache: Features
Complex Origins The Type 2 complex was most likely designed by IBM Japan. This is supported by the following facts:
"H" and "L" Complex Identification Both H and L have no L2 cache socket or solder pads for one. H models (92F0079) came with a 486SX-25 in U8 and have a second socket (U9) for a 487 copro or a 486DX2-50 ODP upgrade chip. They will accept a Turbochip if the DMA controller is the good one. L models (92F0161) came with a 486DX2-50 in U8 and have only solder pads at the U9 location. They will take a ODPR or (with the good DMA controller) a Turbochip. "H" / Upgrade 486SX 25 MHz (92F0079, FCC ID ANOIBM486SXB25)
"L" / Upgrade 486DX2 50 MHz (92F0161, FCC ID ANOIBM486SXB25)
Rear of "H" / "L"
U23 Motorola XAA212 or empty J1 Jumper I just noticed J1 in April 2020. What is it for?
U6 Variants and Kingston Turbochip Some Type 2 (92F0079) suffer from an "incompetent DMA-chip",
which is P/N 92F1428 at position U6 on the card. Working Type 2s 92F0079 have
a DMA-chip P/N 10G7808 at U6. If U6 is 10G7808 Kingston Turbochip should work
fine. The earlier Type 2 use the 92F1428 - which ends the experiment in
odd results (permanent I9990044, 605, 165 errors, and inability to read
from FDD). Known U6 variants:
Running DX4-100 on L (Requires U23) Jay Bodkin said: Peter Wendt replies: All "L" complexes have U23. The presence of a Motorola XAA212 chip at position U23 (on the solder side of the board) seems also be a critical point: if it is there the board is made in 1992, earlier 1991-manufactured board lack this chip - and failed to work with anything faster than a DX2-25/50 (Or a DX2-33/66, which will run as a 25/50 there only anyway). DX4s or Evergreen, Kingston and such like based on a quad-clocked AMD 5x86 failed with no exception on the earlier ones. There should be a silk-screened "Date of MFG" number somewhere on the platform, like e.g. 2092A0700 - which means 20th week 1992 (first 4 digits). If yours is a 1991 platform or early 1992 without the U23 chip - forget about it. On these boards I had a failure-rate of 100% (about 20 out of 20...). > Interestingly, putting back the 486 DX-2 50 doesn't work now either. It still gets stuck on the 96-8N1, even after removing the battery for a couple of minutes! IBM wrote in the HMM "Remove the battery, then wait 5 minutes..." (HMM, September 1993, P/N 71G9316, page 300, "96 8N1 Error Message") but empirical research showed that this doesn't work fairly often. Shortening the battery connectors (with the battery removed of course) *and* toggling the startup password jumper seems to be the only fast cure. There seems to be a board logic, that ANDs the two conditions after a power-on and deletes the entire setup from the CMOS. At least during the "hot phase" when the Mod. 90s and
95s can be found in larger amounts at the customers this
procedure was the only one that worked in a sufficiently
fast way. And I had quite a lot 95s under service...
;-) (Some are mine now) 3172-002 93F1666
The 3172-002 uses a 95 single serial planar and an "H" complex with a 3172 flavor complex BIOS (93F1667). This particular 3172-002 complex is the later version with a 10G7808 DMA controller and U23 on the back. They will happily accept the 41g9361.zip BIOS. Overclock attempt Swapping a 66.667 MHz osc in for the 50 MHz one will result in a 00010200 code in the upper left hand of the screen and a system hang. The Y1 Oscillator drives both the data bus and the DMA controller. 0001 02XX ROM checksum or timer error. ODP vs. ODPR The 169 pin is the ODP-version - substitutes a
487SX with the 486SX still in place. Important on
boards with soldered CPU or a second socket. ODP in Original Socket Dr. Jim, can the 169th pin be bent/removed and the CPU used? Yep. The socket I just put into my P75 has an empty hole to allow that extra pin to pass. I've drilled similar holes in older 486 sockets myself. Carefully. BTW, I've been informed that it is NOT the SX disable pin, just a key pin. The SX disable is elsewhere. Jose Duran: In Defense of the L Actually Tony Ingenoso said: Complex BIOS BIOS stored in EPROM. Support for >1 GB Disks as IML Drive Type 2 complexes require the combination of BIOS 41G9361 and SCSI BIOS 92F2244/45 in order to handle IML drives >1GB (new limit is 3.94GB). The upgrade BIOS incorporates the "Enhanced IML" which supports IML from a drive >1GB and "Search IML" which allows IML from a drive other than ID6. The SCSI BIOS 44/45 pair supports drives well over 8GB. (Ed. You OS may have other ideas...) The old' complex ROMs' IML support somehow does not make (proper) use of "Enhanced IML", possibly due to bad bit-shifting and/or masking when translating the cylinder/head/sector information to and from the SCSI "logical block/sector" value. More information HERE. 171 POST Errors Symptom: A 00017100 (171) error occurs on POST (Power-On System Test). This problem may occur on 8595/9595 models xLx or xHx systems during the installation of a LANStreamer MC32, MC16 or EtherStreamer MC32 in slot 8. Fix: Do not install any of the above referenced adapters in slot 8. Relocate the adapter to one of the other Micro Channel slots. No further engineering action is planned. Diskette Data Loss (ECA100) This problem may allow bad data to be read from or written to a device WITHOUT any error indications or other evidence of system failure. This affects any device attached to the floppy controller that is "seen" as a floppy drive, such as some tape backup devices. Affected Systems: All systems using the 486SX/25 MHz complex FRU P/N92F0079. Notes: The following are no longer supported: 5.25" Diskette Adapter/A (6451007), 4869-001 360 KB and 4869-002 1.2 MB External Floppy. These adapters use a separate device driver (not BIOS), and DMA verify. Updating the system partition will NOT cure the problem. |
