84F9154 SOD Type 1 with socket -OR- solder pads for Weitek 4167
A utility to alter the number of sectors for a SCSI drive
and convert them to a 3.94GB drive! Bob Eager, you have
answered a prayer!
"G" 486SX 20 MHz
Info on Weitek 4167
* DMA controller originally limited to 16MB. Fixed by the last BIOS update (unknown how).
On the 20 MHz board, jumper 2 must be on 1
and 2 if a 487SX processor is installed in position U1.
If there isn't a 487SX in U1, the jumper must be on 2
installing a CPU, align beveled corner with the beveled
outline on the board.
Note: The "G" is
the only Type 1 complex to lack a 160 pin L2 Cache
"J" 486DX 25 MHz (64F0201, old 84F8036, FCC ID ANOIBM486A25)
191-052 IBM PS/2 486/25 AND 486/33 PROCESSOR UPGRADE OPTIONS
J1 The 160 position connector is AMP 650756-1, dtd 9145.
J8 The "J" complex has been seen in three guises:
Looking into the functionality of a Weitek 4167 "Abacus"
in the U8 position. From this VERY limited sample, it
seems you need 54F2958 Data Iface/Buffer (RAM) (old) in U16,
20, and 30 to support the Weitek 4167.
Info on Weitek 4167
Applications that took advantage of the Weitek Abacus were
scarce. AutoShade, Autodesk Renderman, 3-D Studio were the
most prominent to use a Weitek coprocessor.
If you happen to own one, you might actually use or at
least test it... so here's the official test-suite from
Weitek. It contains these tools:
copro16a.txt The best source of technical information about the 4167 is the highly recommended copro16a.txt by Norbert Juffa in 1994.
190-186 IBM PERSONAL SYSTEM/2 486/33 PROCESSOR UPGRADE OPTION
J8 The "K" complex has been seen in three guises:
"Special K" (American breakfast cereal)
Non-SOD Ks (Nothing where U8 was, just green resist)
What is the SOD?
What exactly is this "Square Of Death" (SOD)?
It is the mark of the beast. This square of solder pads is actually the binary equivalent of 666.
David Beem responds:
>Regarding the sensitivity of this complex, has anyone ever tried to swap the BIOS with another Type 1 complex that is known to work with the faster CPUs?
Despite the complexes being
very similar & using the same reference disk,
fundamental changes for things like the Weitek
coprocessor could really mess things up. IBM would issue
a whole complex if there were problems, not just a BIOS
change. Other than the T4 'N' I have seen no evidence of
other complex types checking things like CPUID.
Practically the SOD can be judged as an
analog to the "spare" dual-in-line artifact solder spots
that can be found on many cards, where the developers
planned to build "something" but weren't sure what it
could be and how it should look. Reserve spots in a way
suitable for add-ons or patches, barely attached to the
whole board - apart from power, GND and some basic
address / data / signal lines. The outline matches the
Weitek math-co, but it is (after my knowledge) not
supported from neither the glue logic nor the platform
SOD Limitations (from Tim Clarke)
The limitation of the 'poor DMA controller'
for the Type 1 SOD board appears to be that you can't
run a Cyrix/IBM 5x86 at greater that 'x2 clocking' (i.e.
50Mhz in a Type 2, 66Mhz in a Type 1) or an AMD 586 at
greater than 'x3 clocking' (i.e. 75Mhz in a Type 2,
100Mhz in a Type 1). Ed.
You CAN run a 486DX4-100 ODPR on a SOD. It's only a 3x
Not having a SOD Type 2 I can't test this, but I would expect the same limits to apply. So, you should be able to run a DX2-50, DX2-ODPR (@ 50Mhz), Cyrix/IBM 5x86 (@50Mhz) or AMD 586 (@ 75Mhz) in a SOD Type 2. The 'performance' of a Cyrix/IBM 5x86 @ 'x2 clocking' and the AMD 586 @ 'x3 clocking' are *roughly* equal, although I have a preference for the Cyrix/IBM chip.
ECA #0530 90-0K9/95-0KD with Complex P/N 84F9356
Steven Wachtel wrote:
These systems appear to have a memory
management problem. In my environment it was seen on a
Model 90 with 16 MB of RAM. The system would hang during
OS2 boot or during invocation of simple processes after
a basic install (such as the system editor ). Symptoms
at other OS2 sites would include excessive "random" trap
errors. Not using DOS on these systems, I would expect
the problem to surface as some indeterminate memory
related failure in the E/XMS region.
During initial setup of this
machine, the problem appeared as an inability to create
a usable backup reference disk ( if said disk was used
there were always errors ). On restart after the
failure the machine will request to exec its own
auto-reconfiguration and mark out the "bad"
regions. For my situation I had the IBM CE on-site
for ~6 days for two separate events. The CE
changed each memory chip and riser (for the M90)
multiple times and recombined them in every combination
Today (11/5/91) after following his instincts and direction of the higher level support reps, he contacted them again. They asked for the part number of the CPU board, upon which rests a Gate Array based custom memory controller. He was advised that there are *known* problems with the down-rev boards in my new machines. This problem exists(ed?) on the 0KD models of the M90 and M95, and possibly (as I do not have any to verify this ) the 0JD models. IBM's second level support is apparently aware of this potential problem, but has not disseminated this to the CE level or the purchasing customer.
Problem part identification and rectification:
Upgrade 486DX2 66 MHz (92F0145 / 52G9480, FCC ID ANOIBMB33)
192-178 IBM PS/2 486DX2-66 PROCESSOR UPGRADE OPTION
J4 Once you toggle
this jumper you will end up in a 0129 3000 error -
"EEPROM Jumper is in the wrong position" and no boot or
such. I'd reported that some time ago while testing
around with the 92F0145.
Note: Leave J4 jumper on the center and bottom pin - "R".
Upgrade 486DX2 66 MHz Back
CR2 Schottky Diode B54 (Flash Vpp)
U77, CR2, L1 (plus some other passives) are part of a local 12 V voltage generator. This additional "programming voltage" (Vpp) is required by the Flash memory to perform erase/write operations. Its general topology closely replicates the "Flash Memory VPP Generator" circuit from the LT1109 datasheet (page 1).
But the system permanently fails to boot
into this Type 1 reference partition. Once you reboot it
and press [ctrl]+[alt]+[ins] at CP 66 (cursor top /
right) the machine loads the operating system instead
jumping into reference.
The platform nicely takes the Kingston Turbochip *without* restoration of the system partition. Runs fine with it - right from the start.
Supports Non-IML Configurations
Dennis Smith found out that this complex can
successfully boot without an IML device at ID6. He
booted a SCSI drive at ID0 WITH NO IML track. I did it
here with my upgrade DX2-66.
His guess was this complex was designed
to support RAID Arrays, and the early RAID controller,
"Passplay" had no ability to boot from an array.
Upgrade 486DX 50 MHz (92F0048, FCC ID ANOIBM486A50)
U44 Complex BIOS
Stock version is 91F9812. This version does not fully
support the F/W SCSI [Corvette] and IML from up to
To get the most out of this complex, you need the 52G9509 "8590/95 Dual Booting
Capability EPROM" -AND- the SCSI adapter needs the 92F2244 and 92F2245 SCSI BIOS
Firmware. All three can
Tribbles, and all Fast/Wide SCSI
adapters come stock with the 44/45 SCSI BIOS pair.
Note: This complex
needs the 15 ns cache. The other Type 1 complexes use
The Upgrade 486DX-50 is a Type 1 with true 50MHz CPU on
the complex! All Type 1 complexes [except "G"] use
a 160 position 4x40 receptacle for the L2 Cache option.
Having the 486DX-50 on the complex PCB instead of a
daughtercard means that any upgrade CPU will NOT be
getting close to a Model 90 memory riser!
Note: On the
Upgrade 486DX-50, the CPU clock, OSC1, has been moved
from being under the left side of U16. It is visible
even with an L2 Cache option installed. OSC1 is a black
SMD, so if you don't see a shiny oscillator like you are
used to, look again.
Note: The Type 3
"M" complex is the only other true 486DX-50, but the
"M"'s DX-50 is on the daughtercard! [M is also called
Note: The Type 3
"M" complex is the "Enhanced 486/50" while the Type 1
486/50 is the "486/50 Processor Upgrade"
Identify Upgrade 486/50
I have noticed that sometimes, an older complex that was replaced is put into the box from the upgrade.
To positively identify the Upgrade 486/50, look at the back for the FCC ID sticker. It should say "FCC ID ANOIBM486A50".
What happens: A 486/33 "K" is replaced by a 486/50, the "K" is put into the box, and through no fault [it is almost 30 years old!] the complex is called a 486/50 because that's what is on the box... This happens with other adapters as well.
The 486/50 is easy to identify, the location of OS1 is to the left of other Type 1 complexes, OS1 is 50.0000 MHz, and OS1 is an SMD [black plastic]. All other Type 1 complex use metal canned oscillators.
Note: The yellow component just below OS1 is "A5C 334K".
So if you want the fastest Type 1 complex, remember that Black is Beautiful!
100 MHz Type 1 Upgrade (mod by Peter, article by Tam Pham)
How is this different to the other T1 boards and the T3 Enhanced complex?
It seems as if IBM wanted to offer an upgrade path to DX-50 *without* the ECC option - for those customers that have a -xKx machine already and for the Mod. 90 maybe, which does not cope with the "2 layers" DX-50 Type 3 platform very well. This board was not offered with any particular Mod. 90 / 95 right from the start. It has been an option only.
We, the god-Emperor:
To be klar about the improvement in the M complex:
Tom sums things up:
The Enhanced T3 50 complex, on the other hand, is a drastically different beast. It brings not only a higher CPU performance, but also better system throughput, thanks to its improved design and streaming capabilities. It also comes with a 32-bit DMA controller, ECC memory support, and more. All these enhancements were of course reflected by its development time and price tag.
So, clearly what we have here are two very different designs, with different capabilities, release dates, and price points. If your server needed some more CPU headroom and it needed it now (late 91/early 92), the T1 Upgrade 50 would have been the right choice for you. If you sought after higher overall performance, or some of the new features, the Enhanced T3 platform would give you that. For extra $$$...Lorenzo Mollicone
The Announcement Letter says "... an external 256KB level two cache is provided as standard on the processor complex" All of my boxed Upgrade 486DX-50 Processor Upgrade Options have the L2 Cache.
256 KB Cache Memory Option Kit 17 ns and 15 ns [Work in Progress!]
Note: In a
advertising/ tech nugget booklet, IBM ran tests with a
number of [then] current applications, and the best they
could do was 6%; that is, six percent. I bet they wanted
17 ns for "J" , "K"  and Upgrade 486DX2-66  complexes
The 256 KB cache is a 5.5 x 3.0 inch card that
connects to either the 25, 33 or 50 MHz complex.
The connector is 160 pins arranged in four columns
and 40 rows. The complex provides all the power
required to drive the 256 KB cache.
256 KB cache memory option three basic logic elements:
256 KB of Static Random Access Memory
["Data SRAM"]. This is two-way set associative,
which allows each index location in the cache to
store two pieces of information. This improves the
hit ratio, and decreases the number of times that
cache items must be removed to make room for new
of "TAG SRAM" stores some of the cache item's
address bits, used to store and locate the item,
and some bits used for validity checking.
"Cache Controller" coordinates access to the SRAM. On a cache-hit, the controller organizes the access of the data from the data SRAM using the TAG SRAM address. On a cache-miss, the controller places the new data into the cache, updating the TAG SRAM and data SRAM at the correct index location.
The controller is also responsible for
ensuring that the address being searched for is
actually a cacheable address. If not, no cache
search will be done.
Optional Cache Card Installation
256K Cache Not Visible under System programs?
256K 17 ns Cache Daughtercard (6451095 or 64F0199)
Huh, I noticed that U11 on the -15 ns version is close to the OPT [?] than all the other PLCCs. And here we have U11 with a 84F8257... I wonder if this chip has the presence ID bits akin to multi-card units...
Ed. The chips
change from module to module. Yours may be different. I
see no specific memory or cache controller chips [yet],
the AMD chips are GAL/PALs, and they probably aren't the
highest performance option...
Fil-Mag or Sprague 77Z14Annn Active TTL Delay Module
92F0050 / 10G3527 Front Side Thx to Lorenzo Mollicone
Huh, U11 is 10G3532. P/N is 10G3527. All the other PLCCs are 91F97nn.
92F0050 / 10G3527 Back Side Thx to Lorenzo Mollicone
Significant change from 17 ns version. The 64F0199 uses five Fil-Mag Delay Modules and the 15 ns uses ONE bel S423-0025-02.
Motorola MC88915FN55 Low Skew CMOS PLL Clock Driver 55 MHz; Datasheet
How Does System Know That Cache Installed if it Doesn't show Up?
On -17, U11 is 84F8257, different from most of the
PLCCs. If I could see a sticker on the 64F0199, I bet it
would be 84F82nn...
Example Multi-Card Adapter is the Image Adapter/A:
I'm not so sure that the L2 cache module has a "POSID" as such, but as you speculated, some of the ID pins on the interconnect are tested to "modify" the complex's configuration table during POST.
L2 Cache Performance
From Us, the god-Emperor of Microchannel:
From Tony Ingenoso:
From Charles Lasitter:
DX50's are strange -- they often outrun DX2-66 when main memory bandwidth or I/O is the constraint. When staying in L1, then the DX2-66 wins due to the multiplier. With a fast L2 and fairly scattered code/data a DX50 is going to do very well.
The 486DX2-33/66 showed 33 BogoMips, the
DX50 25 only ... same as the T3 DX50 while a DX2-50/100
(Intel DX4-100 in 2x mode) on a T3-platform runs at
-supposed- 50 Bogomips almost.
In the practical use the T1 DX50 wasn't
much slower than the T1 DX2 - the XF86 stuff paced at
the same rate on both. None of the machines "felt"
faster or slower. The DX4 T3 was a bit faster - but not
significantly. All 3 machines had the same XGA-2 card,
the same TR 16/4 network adapter, the same 32MB Parity
RAM and the same IBM 400MB HD with the Linux on it.
The T1 platforms had the "plug on" 256K
L2 cache (17ns on DX2, 15ns on DX50) and the T3 had its
own integrated cache. I did not write down all the
values ... maybe I should repeat that session again to
get some definite, comparable data.
ODP vs. ODPR
169 pin ODP - 487SX installed with 486SX
still in place, needs the "SX-disable" pin. Important on
boards with soldered CPU.
Support for >1 GB Disks as IML Drive
Type 1 complexes require the combination of BIOS 52G9509 and SCSI BIOS 92F2244/45 in order to handle IML drives >1GB (new limit is 3.94GB). The upgrade BIOS incorporates the "Enhanced IML" which supports IML from a drive >1GB and "Search IML" which allows IML from a drive other than ID6. The SCSI BIOS 44/45 pair supports drives well over 8GB. (Ed. You OS may have other ideas...)
More information HERE.
Some Other Thoughts
From Charles Lasitter:
With the 52G9509 in place, ID6 in bottom bay (Mod 95) at end of cable, ID5 in bay above on next spot on cable, I couldn't get the IML to go to ID6 to save my ass. It made a beeline for ID5 every time. Put in the old BIOS, and it goes straight for ID6.
Enhanced BIOS Effects
From Charles Lasitter:
This same feature is related to the IBM
controller's inability to do an actual format of the
drive if there has been an IML partition on the drive
before. The space at the end of the drive is never
released, because the IBM controller refuses for format
that area of the drive.
That's why I typically use the RAID
adapter when I REALLY want to nuke some drives.
Upgrade EPROM Additional Capabilities
Type 1 complexes (except DX2-66 Upgrade, 92F0145) need BIOS 52G9509 to handle IML drives of >1,023MB. (U36 in drawing)
Complex EPROM Speeds
The normal EPROM speed is 120 ns (or so).
Other than the fact that the second stage of POST is
contained on a mechanical device, how fast is stage 1
Am27C010 versus Am28F010
I was diddling about, looking to turn out some 52G5909
T1 Upgrade BIOS for Lorenzo. In my desire to be lazy, I
thought getting some EEPROMs would make my life easier,
no UV eraser needed, just "Blank Device"...
So I then pumped out five 28F010, and it is great! Blank 'em and program, no UV eraser needed... and then I ran into "Stuck bit Hell". I struggled through 20 28F010 in order to get ten good EEPROMs. I then sent my love children to Lorenzo, thinking, "Hey, they verified and have the same Czechsum, must be good" and I... was... wrong...
So, experience suggests that you stay with the same
device family or hilarity may ensue... I can't explain
in detail why, but I sure as heck can say it didn't work
for me. YMMD
Type 1 Complex Upgrade to "8590/95 Dual Booting Capability EPROM"
Complexes with the following EPROM part numbers may be upgraded:
It was called the "8590/95 Dual Booting Capability EPROM Package".
PART NUMBER 52G9509 (was 52G9750 - try this if other PN is not known)
Note: Use the latest refdisk and diags. See above...
You can see this on a number of Type 1 complexes, including the Upgrade 486DX2-66 and the Upgrade 486DX-50. What is CR1 for?
Apparently Lorenzo already tried this: