-x0x "0 Minus" 386DX 20 MHz, FRU: 64F0782, FCC ID: ANO386201A
	No L2 cache Supports 1, 2 MB 85 ns (80 ns?) 8 MB FPM max (?), 24-bit DMA

-x0x 386DX 20 MHz, FRU: 04G3884, FCC ID: ANO38620C1A
	64 KB 25 ns L2 cache Supports 1, 2 MB 85 ns (80 ns?) 8 MB FPM max (?), 24-bit DMA

-xGx 486SX 20 MHz, FRU: 64F0201, FCC ID: ANOIBM486A20
	No L2 cache connector 2, 4, 8 MB 70 ns FPM matched pairs 64 MB FPM max, 24-bit DMA Some with bad DMA controller

-xJx 486DX 25 MHz, FRU: 64F0201, 84F8036, FCC ID: ANOIBM486A25 -xKx 486DX 33 MHz, FRU: 64F0198, 84F9356, FCC ID: ANOIBM486A33
	2, 4, 8 MB FPM matched pairs 64 MB FPM max, 24-bit DMA Some with bad DMA controller Optional 256 KB 17 ns WT L2 cache (L2 board FRU: 6451095, 64F0199)

Upgrade DX-50 486DX 50 MHz, FRU: 92F0048, FCC ID: ANOIBM486A50
	2, 4, 8 MB FPM matched pairs 64 MB FPM max, 24-bit DMA Some with bad DMA controller Standard 256 KB 15 ns WT L2 cache (L2 board FRU: 92F0050)

Upgrade DX2-66 486DX2 66 MHz, FRU: 92F0145, FCC ID: ANOIBM486B33
	2, 4, 8 MB FPM matched pairs 64 MB FPM max Optional 256 KB 17 ns WT L2 cache (L2 board FRU: 6451095, 64F0199) Flash based, supports >1 GB IML

-xHx 486SX 25 MHz, FRU: 92F0079, FCC ID: ANOIBM486SXB25 (same as xLx)
	No L2 cache 2, 4, 8 MB 70 ns FPM SIMMs FPM single, matched, mixed pairs 64 MB FPM max, 24-bit DMA Some with bad DMA controller

-xLx 486DX2 50 MHz, FRU: 92F0161, FCC ID: ANOIBM486SXB25 (same as xHx)
	No L2 cache 2, 4, 8 MB 70 ns FPM SIMMs FPM single, matched, mixed pairs 64 MB FPM max, 24-bit DMA Some with bad DMA controller

-xMx 486DX 50 MHz, FRU: 82G2484, 57F1597, FCC ID: ANOIBM486B50
	Two board construction 256 KB L2 WT cache SIMMs in matched pairs 64 MB ECC -or- FPM max 32-bit DMA Some with bad streamer support

-xNx 486DX2 66 MHz, FRU: 61G2343, FCC ID: ANOIBM486C66
	128 KB L2 WB cache 169-pin Socket (LIF, 5 V) SIMMs matched pairs 64 MB FPM -or- 256 MB ECC max 32-bit DMA SynchroStream Controller

-xPx Pentium 60 MHz, FRU: 52G9362, 06H7324, FCC ID: ANOIBM586A60 -xQx Pentium 66 MHz, FRU: 92F0120, 06H7317, FCC ID: ANOIBM586A66
Revised board layout (xQx only?):	256 KB L2 WB cache Socket 4 (LIF, 273 pins, 5 V) SIMMs in matched pairs 64 MB FPM -or- 256 MB ECC max 32-bit DMA SynchroStream Controller

-xYx Pentium 90 MHz, FRU: 06H3739, 06H7095, FCC ID: ANO06H3729
	256 KB L2 WB cache Socket 5 (LIF, 320 pins, 3.3 V) SIMMs in matched pairs 64 MB FPM -or- 256 MB ECC max 32-bit DMA SynchroStream Controller

Complex photos by Jelte W. Roelfsema (JWR), Wolfgang Gehl, and from various other online sources.