Complex Identification (outlines)
Complex FCC ID, Release Dates, Announcement Letters
US5162979 Personal computer processor card interconnect system
Overview of Complex Features
Overview of Complex Features
Reason for the Processor Complex
In the first PS/2 models, most components were integrated
into the planar of the system. This severely limited upgrade options and
upgrade flexibility. While one component was upgraded, for example the
processor, the other components such as the I/O controller and the memory
controller were not. This created combinations of fast and slow components,
which created unbalanced systems. Unbalanced systems are not as efficient
as balanced systems where every components' performance is matched
against other components' performances.
The processor complex consists of the devices and features
in the computer that perform logical operations and calculations, control
access to memory, and manage data-transfer operations. The following devices
and features make up the processor complex:
If your computer contains a processor complex, it is connected
to the system board by two 164-pin, 82-position connectors, known as the
processor interface connection. The processor interface connection provides:
L1 or Processor Cache
There are two levels of cache. The cache incorporated into the main system processor is known as Level 1 (L1) cache. The 486 incorporates a single 8 KB cache (Overdrive chips can have 16 KB). Pentium CPUs have two 8 KB caches, one for instructions and one for data. These caches act as temporary storage places for instructions and data obtained from slower, main memory. When a system uses data, it will be likely to use it again, and getting it from an on-chip cache is much faster than getting it from main memory.
The external cache is called Level 2 (L2) cache and it provides additional high speed memory to the Level 1 cache. This additional cache memory works together with the cache memory native to the main processor (L1). If the processor cannot find what it needs in the processor cache (a first-level cache miss), it then looks in the additional cache memory. If it finds the code or data there (a second-level cache hit), the processor will use it, and continue. If the data is in neither of the caches, an access to planar memory must occur. (G, H, and L complexes do NOT have L2 cache, nor do they have a cache socket).
L2 cache can be accessed 5 to 10 times faster than standard memory. Cache memory uses Static Random Access Memory (SRAM) which is much faster than the Dynamic Random Access Memory (DRAM) used for system memory. SRAM is more expensive and requires more power, which is why it is not used for all memory.
Note: The J/K/UPG 66 complexes use 17 ns 256 KB cache daughtercard. The UPG 50 uses a 15 ns 256 KB cache daughtercard.
The memory controller is a device on the processor board that controls access to system memory by the microprocessor and I/O devices. Registers in the memory controller contain information about the amount and type of memory that is installed in the computer. During a system reset, the power-on self-test (POST) routine writes this information into the registers.
The functions of the memory controller vary among PS/2 models. They
Dual Path to Memory
When bus masters were implemented on Micro Channel servers, it was found that there was often contention for memory access between the processor and the bus masters, and that the processor was being delayed waiting for bus masters to release the path into memory. The new design of the processor complexes addresses these issues by providing a dual-path into memory, effectively providing two paths to system memory, one from the processor and one from the Micro Channel. These two separate paths to system memory allow overlapping of processor and bus master cycles. (M-Y complexes)
Note: Dual Path memory is also known as Dual Bus Interleave. Base 1 complexes also support this feature, but do not have buffers. Base 2 complexes do not support Dual Path Memory. Packet Data Transfers are used by the I/O buffer for writes to memory. This means that 16 bytes are written to memory in one processor cycle. In unbuffered systems, a write to memory is performed every four bytes.
Three kinds of overlapped cycles can occur:
CPU reads to L2 cache simultaneously with bus master I/O
CPU reads to L2 cache simultaneously with bus master memory access
CPU reads to memory simultaneously with bus master I/O
Both processor and Micro Channel cycles are buffered into
16 byte blocks, further alleviating the contention for memory by reducing
the frequency of the accesses. Implementing dual-path access to memory
and the buffering of cycles can give a system throughput of up to three
times that of a server without it.
Two-Way Interleaved Memory Banks
Another performance advantage is gained when the processor is accessing memory in burst mode. Memory is split into two banks, and data or code is stored sequentially across these banks; for example addresses 0 and 2 are held in bank 1, and addresses 1 and 3 are held in bank 2. The reason for this arrangement is that when a 486 burst mode request is made, the accesses to memory will be sequential. When the memory controller detects such a burst request from, for example, bank 0, it also pre-fetches the next 32 bits of data from bank 1. This way, the processor is not kept waiting while the information is being retrieved from memory.
DMA controllers are a dedicated unit with the ability to move data between system memory and a device on the Micro Channel.
More information about DMA and DMA Controllers HERE.
It's used by simple adapters, and also by the parallel and serial ports. Earlier versions of the Model 95 (G-L complexes) implemented a 24-bit DMA, limiting DMA memory transfers to below 16 MB (whereas the 486 processor was able to address up to 4GB of memory). On 32-bit systems with more than 16 MB of memory, this could cause problems if a DMA access was for memory above 16 MB. The operating system could work around the problem by ensuring that DMA buffers were always below 16 MB when a DMA transfer was done, but this imposes a performance penalty.
40 MB/s Data Streaming
The 40 MB/s data streaming transfer (M through Y complexes) offers considerably improved I/O performance. As in many cases, blocks transferred to and from memory are stored in sequential addresses, so repeatedly sending the address for each four bytes is unnecessary. With data streaming transfer the initial address is sent, then the blocks of data are sent and it is then assumed that the data requests are sequential.
Note: The M complex supports Streaming, but lacks SynchroStream Controller.
List of adapter that support this transfer mode can be found HERE.
Complexes work in all 8590 / 8595 / 9590 / 9595 / 500.
Any existing Model 90, Model 95, or PC Server 500 can be upgraded to a new Processor Complex. For example, Base 1 to Base 2 or Base 3 or Base 4; Base 2 to Base 4, etc.
However the T1/T2/T3 complexes will NOT work in the newer 95A (dual serial/dual parallel) planar. This is due to the fact that the older T1/T2/T3 BIOS and refdisks lack support for the revised 95A planar (different layout of the POS registers, different NVRAM implementation etc.).
Note: The power supply in the Model 90 case is supposedly a little small for the DX50, P60, P66, and P90 complexes. And in addition, the air baffle in the Model 90 may have to be removed if a processor with a big heat sink or heatsink / fan combination is installed. But I have to wonder, it's rated for 215 Watts. That's not THAT weak... Hell, the 9577 PS is only 194 Watts.
Difference Between Complex Types
Obviously not only the speed...
Mentions "optional 256K cache" - which makes clear that no other board than 64F0198 and 64F0210 is meant. The 486DX2-33/66 board 92F0145 is then a much later development out of the Non-SOD 64F0198 - intended to use Flash-BIOS, but not fully developed or supported. (That's the board with the odd bank-select jumper in the top/right corner)
(Ed. based on personal inspection of a 92F0048) - The 92F0048 appears to be also based on the Non-SOD 64F0198, with a DX50 CPU, a 50 MHz oscillator, and some decoding circuitry mounted in the area that on the SOD would go on. The matching 12nS cache module is 92F0050.
The smaller Type-1 platforms had been offered to form "entry models" - focused on the Mod. 90 (92F0065 - 486SX-20 and 92F0049 - 486DX-20). The 92F0065, which I call "Kiddies CPUs", is the only one which has a 487SX-presence" Jumper.
A totally different thread are the Type-2 platforms, which all base on the 92F0079. The Type-2 platforms have been developed to make memory selection a bit easier - for the cost of some performance as a cost-efficient solution.
The Type-3 platform of the -M- class has been intended for high-end servers: paired memory *and* ECC support. Only few Mod. 90 saw this platform as far as I know. Don't know if IBM ever offered it officially in the 90. I remember having seen 2 or 3 Mod. 9590-AMF at a customer - but they had the [PA]-sticker close to the Serial-number decal ... which identifies them as "upgraded machines".
The -M- platform even survived the change from the 8595 to the 9595 (with the old planar and LED-panel however) along with the 92F0161 486DX2-25/50 -L- platform. Strange enough.
The final stage of the 486-line was reached with the Type-4 -N- class board 61G2343 - which was the processor to the 5 V Pentium (P5) platform. This however is a totally new development, at a time when 486 processors were already a bit dusted.
The Type-4 platforms are all very similar with the integrated Intel Cache chipset. I think there has been a lot experience used from the -M- class DX-50 board. But this time everything fits on *one* PCB and make the funny shielded hi-density connectors obsolete for the "second floor" PCB.
> Are there any ECAs related to any specific FRUs?
When installed with the 486SX/25 Processor Upgrade Option, 16-bit bus masters (for example, PS/2 Micro Channel SCSI Adapter (#1005, 6451109)) that support 32-bits of addressing will cause system malfunction and/or potential loss of data when the user installs greater than 16 MB of system memory.
Can't See >16 MB Under W95
HIMEMUPD.EXE is the cure!