This document describes the function of the Brighton Split Bus/Dual ECC Memory Controller.
One bus is an Intel 80960CA interface; the
other is a CFE bus interface.
The purpose of this specification is to provide a
pinout, register description, functional description and
timing information.
All busses are listed with 0 being the Least Significant Bit (LSB).
Bus accesses are generally given in the form 3-1-1-1-0. The first number
(3 in this case) indicates the number of wait states between the address state
and the first data state. The second (and third and fourth) number indicate
the number of wait states between subsequent data states. The last number
(0 in this case) indicates the (minimum) number of wait states between
the last data state of a burst and the next address state. This is also
known as the recovery state.
The Brighton Split Bus/Dual ECC Memory Controller (Brighton) is a VLSI chip that provides the interface between
an Intel 80960CA,
a local CFE bus,
and two memories.
The highest performance will
be achieved when the 80960 executable code, data structures, etc. are
in instruction memory and the local bus masters are transferring data (communications packets)
to and from packet memory.
On the Intel 80960CA bus the chip will support
3-1-1-1-0 cycles
(36 MB/s)
to either memory. Up to four word bursts (quad word aligned) will be
supported. Brighton will also support 3-1-1-1-1 reads (2-1-1-1-1 writes)
from the local bus
to packet memory (4-1-1-1-1 to instruction memory).
However, the local bus may burst more than four words.
This translates to:
The following are the signals used to interface to the 80960CA:
P_A31:2
I
30-Bit Address--The 80960CA's address is received on these lines.
This address is word (4-byte) aligned.
-P_BE3:0
I
Byte Enables--For writes, these signals
tell Brighton which byte(s) to write at the selected address. If one or
more byte enables are inactive then Brighton will perform a
read-modify-write memory cycle.
For reads, these bits determine which bytes will be driven on the
data bus.
P_D31:0
I/O
32-Bit Data Bus--32-bit data is communicated between
Brighton and the 80690CA on this bus.
-P_READY
O
Ready--For 80960CA reads, this signal indicates that data
is valid on the rising edge of PCLK (PCLK is the output
clock of the 80960CA).
For 80960 writes, this signal indicates completion of the write cycle.
-P_ADS
I
Address Strobe--This signal indicates to Brighton that a new
address cycle is beginning.
P_W/-R
I
Write/Read--This signal indicates to Brighton whether a cycle is
a write or read access.
-P_BLAST
I
Burst Last--This signal indicates the last access of a burst
access. This signal must be valid at least one state before data is
ready. (This can be accomplished by programming the 80960 for 0 wait states
and always letting READY pace the cycle.)
See "80960 Region Programming".
-P_DMA
I
DMA--This signal is asserted during 80960 DMA accesses. Brighton uses
this signal to determine if the current 80960 access is by a task
(protection will be checked) or by 80960 DMA (no hardware protection).
The following are the signals used to interface to the local bus:
L_AD31:0
I/O
32-Bit Multiplexed Address/Data Bus--These lines will
contain address information during the address cycle, after which
they will be used for data.
When Brighton is the master, they will be driven during address and for
write data. When Brighton is the selected slave, it will drive these lines
with read data.
L_ADP3:0
I/O
Local Bus Parity Bits--When address or data is present on the AD bus, these
lines will contain the odd parity of each byte. L_ADP0 corresponds
to AD7:0, L_ADP1 to AD15:8, L_ADP2 to AD23:16
and L_ADP3 to AD31:24.
-L_BE3:0
I/O
Byte Enables--Brighton drives these as a master and latches them at
address time as a slave. For writes, these signals
select which byte(s) to write at the selected address.
For reads, these bits determine which bytes will be driven onto
data bus.
-L_READY
I/O
Ready--For reads, this signal indicates that data
is valid on the rising edge of PCLK.
For writes, this signal indicates completion of the write cycle.
Brighton drives this as a slave and monitors it as a master.
-L_ADS
I/O
Address Strobe--This signal indicates that a new
address cycle is beginning. Address is on the AD bus during this
cycle
(L_W/-R and -L_BE0:3 are also latched).
Brighton drives this as a master and monitors it as a slave.
L_W/-R
I/O
Write/Read--This signal indicates whether a cycle is
a write or read access.
Brighton drives this as a master and monitors it as a slave.
This signal is latched during the address phase.
-L_BLAST
I/O
Burst Last--This signal indicates the
last access of a burst
access.
Brighton drives this as a master and monitors it as a slave.
-LEXCPT
I/O
Local Bus Exception--Brighton will drive this line for two clocks
if
Brighton detects a local bus parity error as a slave,
a multi-bit ECC error occurs during a local bus access to memory,
or a local bus time-out occurs.
Brighton monitors this line and will terminate its local bus cycle if
this line goes active (must be held active for two clocks).
-L_REQ2:0
I
Local Bus Requests--These signals are used to indicate to
Brighton that another master is requesting the local bus.
See 5.0 , "Arbiter Function" for details on servicing priority.
-L_GRANT2:0
O
Local Bus Grants--These signals indicate to a local bus
master that they have been granted the bus.
See 5.0 , "Arbiter Function"
for more information.
These lines function as inputs when in Manufacturing Test Mode.
-BRREQ
O
Brighton Request--When this signal goes low it indicates that Brighton
wants to access the local bus.
See 5.4 , "Special Arbitration Modes"
for more information.
-BRGNT
I
Brighton Grant--When this signal goes low it indicates that Brighton
has been granted the local bus by an external arbiter.
This signal is
only monitored when bit 6 of the SPAR is a '1'.
See 5.4 , "Special Arbitration Modes" for more information.
The following are the signals used to interface to DRAM memories.
DD31:0/
ID31:0
I/O
32-Bit Packet Data Bus/32-Bit Instruction Data Bus--These
lines are used to transfer data to and from memory.
DCB6:0/
ICB6:0
I/O
Packet Memory Check Bits/Instruction Memory Check Bits--These
lines are used to transfer error detection/correction codes to and from memory.
DA11:0/
IA11:0
O
12-Bit Packet DRAM Address/12-Bit Instruction DRAM
Address--These lines are used to transfer the row
and column address to the DRAM.
-DRAS1:0/
-IRAS1:0
O
Packet RAS/Instruction RAS--These lines are used to strobe
the row address into DRAM. In one-bank memories, only RAS0 is used.
In two-bank
memories, RAS1 is used to access the second bank.
-DCAS1:0/
-ICAS1:0
O
Packet CAS/Instruction CAS--These lines are used to strobe
the column address into DRAM.
In one-bank memories, only CAS0 is used. In two-bank
memories, CAS1 is used to access the second bank.
-DW/
-IW
O
Packet Memory Write/Instruction Memory Write--This signal
controls whether a read or write is to be performed on memory.
The following are descriptions of all other Brighton signals.
TXDATA
O
Transmit Data--This is the data-out pin for the serial debug port.
RXDATA
I
Receive Data--This is the data-in pin for the serial debug port.
BRINT3:0
O
Four-Bit Encoded Interrupt--These lines will be used to
signal interrupts to the local interrupt controller.
See 9.0 , "Interrupt Function" for more details.
-ROSCS
O
ROS Chip Select--This line will be active when the 80960CA
is accessing an address in the 0-256MB or the 80960 boot record.
See Table 10..
PCLK
I
Clock Input--This is the clock input to the chip.
It will normally be driven by the PCLK output of the Intel 80960CA.
-PRESET
I
Power-On-Reset--This line causes all Brighton registers to assume
their reset values. All Brighton functions are reset and do not operate
until this line is released.
-MTST
I
Manufacturing Test--This pin will be used by manufacturing for testing
purposes. It is normally pulled high.
-DI_IN
I
Driver Inhibit Enable--Used for testing. This pin should be tied HIGH
during normal chip operation. If -DI is LOW AND RXDATA is LOW then
all off-chip drivers in Brighton are tri-stated. If -DI is LOW AND -POR
is LOW Brighton will be in Static-IDD-Test-Mode (used by chip manufacturer).
A_CLK
I
LSSD A Clock--Used for chip testing. This pin should be tied HIGH
during normal chip operation.
B_CLK
I
LSSD B Clock--Used for chip testing. This pin should be tied HIGH
during normal chip operation.
C_CLK
I
LSSD C Clock--Used for chip testing. This pin should be tied HIGH
during normal chip operation.
Table 4. Other Brighton Signals
COMP
NA
Driver Compensation Resistor. This pin should should be pulled-up
by a 909 ohm +/- 1% resistor to +5V.
VCC
NA
Power pins. All VCC pins must be connected to a +5 volt power plane.
GND
NA
Ground pins. All GND pins must be connected to a ground plane.
The memory locations of all registers addressable in Brighton
are shown
below.
The addresses are valid for both 80960CA and local bus accesses.
Detailed information is found in the
indicated section. Each register is 4 byte aligned in the address
space and should be accessed using 80960 'word' load (ld) and 'word'
store (st) instructions (except were noted). Not doing so may
cause unexpected results.
RESET values are
shown in the Reset Condition section for each register. For these
sections 'U' = Undefined, and 'S' = value is the SAME as it was prior
to the RESET being issued.
Each timer has a preset register which specifies the initial count value
for the timer.
Each timer is actually a down counter that starts counting when the
value of the TPR is loaded into the counter, and a start command is
issued.
A value of 'FFFF'h causes the maximum of 65,535 ticks
to occur before zero count.
A value of '0000'h is not allowed.
A value of '0001'h causes 1 tick to occur before zero count.
TMR 0,1,2,4 are 16-bit timers and TMR 3 is a 24-bit timer.
See 7.0 , "Brighton Timers" for 'tick' length.
This value is initially loaded by software and then can be reloaded
automatically depending on how the TCR is programmed.
Only bits 0-15 are active for TMR 0,1,2 and 4.
Each timer can be read to determine its present count value at any time.
This can be done without stopping the timer.
TPV 0,1,2,4 are 16-bit read only registers and TPV 3 is a 24-bit read
only value.
Each timer has a set of three defined commands to start, stop, and
preset individual timers.
Also, this register can be read to determine if the timer is currently
running.
The TxBUF is the port where data is loaded that is to be sent out the
serial port.
This port is actually a two-deep FIFO + shift register.
When the transmitter is empty, a write to this port sends data
immediately to the shift register where the shifting operation begins.
Bit 8 of this port can then be read to see if the transmit FIFO is full.
If not, another write can be performed to FIFO another byte of data.
When Bit 8 is set, it means the FIFO is full.
An interrupt will be generated to the 80960 when the FIFO again becomes
empty (the shift register still has data to shift out at this time).
When set, this bit indicates that the transmitter is currently
interrupting the processor.
When this bit is read as active the interrupt to the processor is
cleared.
Bits 14-9.
Reserved.
Bit 8.
Transmit FIFO buffer full. (read only)
When this bit is reset, the FIFO has at least one available byte for
data to be written.
When set, all FIFO bytes are now occupied with data.
Further writes to the transmit buffer will be ignored until one or
more bytes are transmitted.
Bits 7-0.
Transmitter buffer data port.
When read, this byte returns the last byte written to the Transmit FIFO.
The RxBUF is the port where data can be read that has been received.
This port is actually a two-deep FIFO + shift register.
Data that comes in from the serial link is accumulated in the shift
register and then sent to the first byte of the FIFO.
An interrupt is generated to the 80960 at this point.
If there is no available position in the FIFO for the the accumulated
byte to be moved, bit 9 of the RxBUF is set.
This is equivalent to an overrun condition.
When set, this bit indicates that the receiver is currently
interrupting the processor.
This bit is cleared when there are no bytes remaining in the FIFO to
be read.
Bits 14-12.
Reserved.
Bit 11.
Data Valid.
When set, indicates that data in the Receive Data register is
valid (has been received, but has not been read yet.)
Bit 10.
More Data Available.
When set, indicates that more data is in the receive FIFO.
Bit 9.
Data Overflow.
When set, indicates that data was received after the byte in the
Receive Data register, but was lost due to an overflow condition.
Bit 8.
Framing Error.
When set, indicates that a framing error occurred while the data byte
currently in the Receive Data register was received.
Bits 7-0.
Receiver buffer data port.
Once the data is read, if more data is available in the FIFO (or as more
data is collected) the byte in the data port will be replaced with new
valid data.
The status byte will also change when the data byte is read.
If the data in the status and data bytes are read by separate byte read
operations, the status byte will reflect the status of the byte
currently in the data byte.
When wrap mode is enabled, the external chip Rx input and Tx output are
disabled, and the output of the transmitter is connected to the input of
the receiver.
Bit 1.
Receiver enable. '1' = enabled, '0' = disabled.
When the receiver is enabled, it monitors the Rx input of Brighton (or
the transmitter output, if in 'wrap' mode) and collects data which is
then stored in the receiver FIFO buffer.
Disabling the receiver aborts any bytes in process and clears bytes
left in the FIFO.
Bit 0.
Transmitter enable. '1' = enabled, '0' = disabled.
When the transmitter is enabled, it collects bytes written to the
transmitter FIFO and outputs them on the Tx output of Brighton (or the
receiver input, if in 'wrap' mode).
Disabling the transmitter aborts any bytes in process, and clears
bytes left in the FIFO, and disables writes to the FIFO.
This register provides the capability to turn memory protection on and
off separately for the various regions in the memory map.
It also provides the capability to turn protection on and
off for tasks, Master1 and Master0 interfaces.
A kernel will normally execute without RAM/IO protection, and device
drivers and interrupt handlers would execute with or without protection
at their option. See 6.0 , "Memory Protection" for more information.
This register is NOT protected by the hardware.
When writing this register, the upper 16 bits serve as a mask for the
lower 16 bits. For example, if you wanted to turn on the 960 task protection
bit you would store the word x'00028002'.
This tells Brighton: write the register (bit 15=1),
write bit 1 (bit 17=1)
and set bit 1 to a 1 (bit 1=1).
The mask bits always read 0's.
Bit 15 must be a '1' to write this register.
This register can only be written using 32-bit writes (i.e. all bytes
enabled).
For protection to be enabled for a particular access, all bits/signals
relating to that access must be in the correct state. (i.e. For a DRAM read
from the 80960: 960TSK=1, ALLRD=1, RAMIO=1 and the -PDMA signal is HIGH.)
Bit 15 -- MPER write enable bit. This bit must be a '1' to
write this register. This bit always
reads 0.
Bit 14-8 -- Reserved. Set to 0.
Bit 7 -- RAM/IO protection (Bit 23 must be '1' to write this bit)
0--Accesses from 80960 to Brighton DRAM, or x'1FFxxxxx' are unprotected.
('Out-of-bounds' checking can still be on.)
1--Accesses to this region are protected.
Bit 6 -- Upper memory (2G-4G) protection (Bit 22 must be '1' to write this bit)
0--Accesses to this region are unprotected.
1--Accesses to this region cause a memory protection error.
Bit 5 -- All read protection (Bit 21 must be '1' to write this bit)
0--Turns off READ protection for packet and instruction memory,
and x'1FFx xxxx' area.
(useful for increasing
performance for non-debug memory protection users)
1--READs to protected areas are checked.
Bit 4 -- Determines whether Brighton will allow the 80960 to access the
local bus in the address from x'2000 0000' to x'7FFF FFFF' except where
packet and/or instruction memory are defined. (Bit 20 must be '1' to write this bit)
0--Local bus memory allowed, no protection.
1--Protection on. An attempt to access to this region will
cause a protection error.
Bit 3 -- Master0 accesses to local bus (Bit 19 must be '1' to write this bit)
0--Master0 accesses are unprotected
1--Master0 accesses are protected
Bit 2 -- Master1 accesses to local bus (Bit 18 must be '1' to write this bit)
0--Master1 accesses are unprotected
1--Master1 accesses are protected
Bit 1 -- 80960 accesses (Bit 17 must be '1' to write this bit)
0--80960 accesses are unprotected
1--80960 accesses are protected
Bit 0 -- Low memory (<511M) protection (Bit 16 must be '1' to write this bit)
This register (which is normally changed by supervisory level software at
task switch time) is a pointer to the starting address of a task's
page table.
Logic
interprets all writes to this register as a task switch, and invalidates
all entries in the task page-access-byte cache.
The six least significant bits of this register will always read '0'.
See 6.0 , "Memory Protection".
Task protection tables must be in instruction memory if it is installed.
This register (which is normally managed by the supervisory level software)
is a pointer to the starting address of the Master0 interface
page table.
A write to this register invalidates
all entries in the Master0 page-access-byte cache.
The six least significant bits of this register will always read '0'.
See 6.0 , "Memory Protection".
Master0 protection tables must be in packet memory.
This register (which is normally managed by the supervisory level software)
is a pointer to the starting address of the Master1
page table.
A write to this register invalidates
all entries in the Master1 page-access-byte cache.
The six least significant bits of this register will always read '0'.
See 6.0 , "Memory Protection".
Master1 protection tables must be in packet memory.
This register latches the address that caused a memory protection
violation by an 80960 task. An interrupt is generated. Once the register
has trapped an address it is locked and will not trap any subsequent
failures until the TPSTAT is read.
The data is valid until the TPSTAT is read.
Note: The TPATR register should be read BEFORE reading the TPSTAT.
This register latches the status associated with a memory protection
violation by an 80960 task.
An interrupt is generated. Once the register
has trapped status it is locked and will not trap any subsequent
failures until the TPSTAT is read.
Note: The TPSTAT register should be read AFTER reading the TPATR.
Bit 7 - When this bit is a '1' it indicates that the TPSTAT and
TPATR are locked and the interrupt is pending.
This bit and the interrupt are cleared
when the TPSTAT is read.
Bit 4 - '1' indicates a write operation was trapped. '0' indicates
a read.
Bits 3:0 - These bits indicate which byte enables were active when
the trap occurred (1=enabled).
This register latches the address that caused a
local bus (Master0 or Master1) memory protection
violation. An interrupt is generated. Once the register
has trapped an address it is locked and will not trap any subsequent
failures until BOTH local bus protection interrupts are cleared.
Bits in the LPSTAT indicate whether the address trapped is for
Master0 protection or Master1 protection.
The LPATR is valid until the LPSTAT is cleared.
This register latches the status associated with a local bus
(Master0 or Master1) protection violation.
An interrupt is generated. Once the register
has trapped status it is locked and will not trap any subsequent
failures until the LPSTAT is read.
This register is byte addressable. When clearing interrupts,
writes should be byte writes.
The LPSTAT register should be cleared AFTER reading the LPATR.
Bit 10 - Write/Read bit for Master1 protection.
'1' indicates a write operation was trapped. '0' indicates
a read. Valid only if bit 8 = '1'.
Bit 9 - '1' indicates the LPATR contains the violating address
for this interrupt. Valid only if bit 8 = '1'.
Bit 8 - When this bit is a '1' it indicates that an interrupt for
Master1 protection is pending and that the Master1 status bits and the
LPATR are locked. Write this bit (using byte operation) to clear interrupt.
Bit 2 - Write/Read bit for Master0 protection.
'1' indicates a write operation was trapped. '0' indicates
a read. Valid only if bit 0 = '1'.
Bit 1 - '1' indicates the LPATR contains the violating address
for this interrupt. Valid only if bit 0 = '1'.
Bit 0 - When this bit is a '1' it indicates that an interrupt for
Master0 protection is pending and that the Master0 status bits and the
LPATR are locked. Write this bit (using byte operation) to clear interrupt.
This register latches the address that caused a local bus exception
error (or parity error when Brighton is the master).
Once the register has trapped an address it is locked and will not trap
any subsequent failures until the LEXSTAT is
cleared (all three parts).
The address is only valid if the corresponding bits in the LEXSTAT are
valid
and until the LEXSTAT is cleared.
Note: When trapping the address for a data parity error (Brighton master),
the address trapped in the LEXATR will be the address of the error + 4h.
This register latches the status associated with a local bus exception
(or a parity error when Brighton is the master).
The register is divided into three parts, status for: LEXCPT seen
with Brighton master (MEX), Brighton detects a local bus parity error while doing
a read (MPE), and LEXCPT sourced by Brighton (EXS).
The three parts operate independently but share the LEXATR register.
Once a part
has trapped status it is locked and will not trap any subsequent
failures until the interrupt is cleared.
If none of the 'parts' were locked at the time of the error then
the address will also be trapped in the LEXATR.
Status bits are only valid if the corresponding pending (PND) bit
is set.
To clear pending interrupts and unlock a part,
write a '1' to the corresponding pending (PND) bit.
Byte writes are NOT supported.
The EXS part does NOT correspond to a Brighton interrupt. It is expected
that the master that received the exception sourced an interrupt to the
processor.
BIT 27 - If set, LEXATR contains address of MEX error
BIT 26 - 0=error on read, 1=error on write
BIT 25 - 0=error on regular 80960 access, 1=error on 80960 DMA access
BIT 24 - This interrupt is pending and these status bits
are valid and locked. Write a '1' to this bit to clear the interrupt
and re-enable trapping.
BITS 18:16 - MPE bits - Brighton detected local bus parity error on read
BIT 18 - If set, LEXATR contains address of MPE error
BIT 17 - 0=error on regular 80960 access, 1=error on 80960 DMA access
BIT 16 - This interrupt is pending and these status bits
are valid and locked. Write a '1' to this bit to clear the interrupt
and re-enable trapping.
BITS 14:0 - EXS bits - Brighton sourced LEXCPT
BIT 14 - indicates if Master 2 was the bus owner when the exception
occurred.
BIT 13 - indicates if Master 1 was the bus owner when the exception
occurred.
BIT 12 - indicates if Master 0 was the bus owner when the exception
occurred.
BIT 11 - indicates if 80960 DMA was the bus owner when the exception
occurred.
BIT 10 - indicates if 80960 (non-DMA) was the bus owner when the exception
occurred.
BIT 9 - 0=error on read, 1=error on write
BIT 8 - If set, LEXATR contains address of EXS error
BIT 7 - '1' = a local bus timeout occurred
BIT 4 - '1' = Brighton detected a parity error as a slave.
BIT 3 - '1' = Brighton detected a multi-bit ECC error as a slave.
BIT 1 - '1' = Brighton detected an address parity error.
BIT 0 - These status bits
are valid and locked. Write a '1' to this bit to re-enable trapping.
There is not Brighton interrupt associated with this bit. It is expected that
the master receiving the EXCEPTION sourced an interrupt.
This register latches the address that caused a single-bit ECC error
interrupt.
The contents of this register are locked and valid
until the interrupt is cleared.
This register is used to count the number of single-bit ECC errors
detected by Brighton.
The SBECCR holds an 8-bit value that is decremented each time
a single-bit ECC error is detected by Brighton. When the count reaches
zero an interrupt is generated. To clear the interrupt, write a
non-zero value to the SBECCR.
This register latches the address that caused the last multi-bit ECC error
caused by an 80960 or task protection access.
The register will be locked and valid until the
interrupt is cleared by reading the ECCSTAT.
This register latches the status associated with a multi-bit ECC error
during an 80960 or task protection access.
An interrupt is generated. Once the register
has trapped status for a multi-bit error
it is locked and will not trap any subsequent
failures until it is read.
This register tells Brighton the amount of packet
memory and/or instruction memory that is installed.
This register also selects where instruction memory resides in the
memory map and the input oscillator speed.
This register is used to determine whether Brighton is in regular
arbitration mode or 'special' arbitration mode. (See 5.4 , "Special Arbitration Modes"
for details on usage.)
It can also be used to determine the amount of instruction and/or packet
memory bandwidth allocated to the 80960.
If local bus masters are capable of long burst transfers, this register
allows the 80960 to 'sneak in' to memory while the local bus is held
'NOT READY'.
BIT 6--Set to 1 to allow 80960 to 'force' a local bus master
out of packet memory for one 80960 access (burst=1 access).
Setting disables internal Brighton arbiter and turns on external arbitration.
It also makes the 80960 higher priority to packet memory.
See 5.4 , "Special Arbitration Modes" for details.
BIT 13--Reserved, set to 0.
BIT 5:0--Number of cycles a local bus master may burst to packet
memory before 80960 may 'force' him out
(0=32 CYCLES)
BIT 12--Bad Address/Data Parity--determines whether BP bits affect
data (BAPAR=0) or address (BAPAR=1).
BIT 11-8--Force Bad Parity--Brighton will force
local bus parity errors on corresponding byte
when it is driving address (BAPAR=1) or when driving data
(BAPAR=0) (Brighton master write or slave read)
(i.e BP3=1 causes parity error on byte 3).
BIT 0--Parity check--Specifies whether Brighton will do parity checking (0=don't
check parity, 1=check parity).
This register is used by diagnostics to force bad ECC codes
to be written to memory. This register should be set
to all 0's for normal operation. A '1' in any of
the defined bits will cause the corresponding check bit
to be inverted (wrong) when a write occurs to memory.
For example, to force a single bit error for data bit 14 (db14) in
packet memory, set PCB(6:0)='1011000'. If you now write x'0000 0000'
to any location in packet memory, it will read back x'0000 4000'
(bit 14 has been 'corrected').
See Figure 4..
This register also allows you to turn off ECC --the check bits are
still written but are not checked on reads--
and to read the most recently read check bits.
Warning! Setting the PCB or ICB bits can be dangerous. Do not allow interrupts,
stack usage, DMA, etc. while these bits are set. Also, after clearing these bits
re-write the memory that was written while they were set.
Brighton supports up to two DRAM memories. These are known as packet memory
and instruction memory. The controllers for them are identical.
The memory organization supported is the same as the Austin
Workstation SIMM.
The two bank organization is shown below:
Each memory may be 0, 1, 2, 4, 8, 16 or 32 megabytes in size.
This is selected by programming the SZ bits in the
MCR (see 2.23 , "Memory Configuration Register (MCR)") to
the appropriate value.
The starting address for packet memory
is 512MB (2000 0000h). Instruction memory begins at 564MB or 576MB
(2200 0000h or 2400 0000h).
See 2.23 , "Memory Configuration Register (MCR)".
Not translated to local bus. Packet memory area. Address range
determined by size of memory (21FFFFFF for 32MB).
22000000 or
24000000
xxxxxxxx
960TSK
RAMIO
ALLRD
Not translated to local bus. Instruction memory area. Starting address
determined by MCR_IMLOC (2.23 , "Memory Configuration Register (MCR)").
Address range
determined by size of memory.
xxxxxxxx
7FFFFFFF
960TSK
LBMEM
ALLRD
Translated to local bus. Local bus memory area. Covers ALL addresses
from 20000000 to 7FFFFFFF except where packet and instruction memory are.
80000000
FFFFFFFF
960TSK
UPMEM
Not translated to local bus. From x'FFFFFF00' to x'FFFFFF2F' causes
a ROSCS.
The 80960 should be programmed to ignore READY from x'00000000' to x'0FFFFFFF'
and x'80000000' to x'FFFFFFFF' because Brighton does not drive READY for these
addresses. The other regions
must
be programmed
for zero wait states (all cases).
Region 1 (x'10000000' to x'1FFFFFFF') should be set to non-burst.
The Error Detection and Correction (EDC) code used is a basic
one-bit correct, two-bit detect scheme. If the data and check bits are
grouped as shown below, chip-kill-detection is achieved
(for memory using four-bit wide chips).
The all 0's and all 1's condition will also be detected
(SIMM-kill-detection).
For chip-kill-detection, the data and check bits should be grouped
as follows:
D2:0,CB0
D5:3,CB1
D8:6,CB2
D11:9,CB3
D14:12,CB4
D17:15,CB5
D20:18,CB6
D27:24
D31:28
D23:21,spare bit
The check bits are generated by 'XNOR'ing the indicated data bits
(similar to generating odd parity).
The data bits used to generate each check bit are shown in
Figure 5..
Note: An 'x' denotes that this data bit is part of the XNOR tree
for that check bit. Figure 5. Brighton Check-Bit Generation
The check bits are generated and written to memory at the same time
as the data. When the location is read, the data and check bits
flow through an XOR tree (same bits as generating logic plus the
check bit). This produces seven syndrome bits. These syndrome
bits are decoded to determine if and where an error has occurred.
For single-bit errors, Brighton will correct the data on the fly
(with no delay) going to the requesting device.
Single-bit errors are counted and an interrupt is generated at terminal
count (see 2.19 , "Single-Bit ECC Error Register (SBECCR)").
For multi-bit errors the data may be scrambled.
Multi-bit errors on 80960 accesses will cause an interrupt.
Hardware scrubbing will not be performed.
Brighton will request the local bus (unless prevented by protection)
when the 80960 accesses an address
from x'1000 0000' to x'7FFF FFFF' except for the areas
where Brighton registers (x'1FFB XXXX'), packet memory and instruction
memory are located.
The area from x'1000 0000' to x'1FFF FFFF' (except X'1FFB xxxx')
is called 'local bus IO'.
The area from x'2000 0000' to x'7FFF FFFF' (minus
packet and instruction memory) is called 'local bus memory'.
(See 2.8 , "Memory Protection Enable Register (MPER)" for register settings to allow
access to local bus memory and local bus IO.)
Brighton will also cause a local bus preempt
(but not do a cycle) if:
a local bus master has been granted the bus AND
the local bus master has not begun a cycle or has begun a cycle to
packet memory AND
the 80960 is attempting to access packet memory AND
the PEN bit of the SPAR is a '0'.
This will continue until the 80960 is granted the local bus at which
point it will access the local bus. The effect is to make the local
bus arbiter the arbiter for packet memory when multiple masters
need access to packet memory.
Only single word (or sub-word) accesses are supported.
The service order (in round-robin fashion) is
(assuming all are constantly requesting):
80960CA
REQ0
REQ1
REQ0
REQ2
REQ0
Note that an 80960CA request is actually the 80960 starting an
address cycle (HOLD and HOLDA are NOT used by Brighton).
All other requesters first request the bus, then are granted the
bus, then start their address cycle. Since the 80960CA is 'quickest'
to the bus, it is the default grantee if there are no other requesters.
A master will not be granted the bus twice in a row unless there are
no other requesters.
To maximize the bandwidth of the local bus, there is a mechanism for
notifying the bus owner that another master is requesting the bus. This
is accomplished by removing the GRANT signal from the local bus owner.
It is then the current owner's responsibility to finish his cycle and
remove his REQUEST. The amount of time the master may remain the bus
owner after being preempted is not defined.
This is illustrated
in the following picture. Two local bus masters are shown (1 and 2).
Master1 currently owns the bus.
Master2 requests the bus.
Brighton signals master1 that another master is requesting
the bus by removing GNT1.
Master1 is finishing his request (he is not REQUIRED to
finish). He releases REQ1 at the same time as asserting
BLAST.
READY is asserted for the current (last) data cycle. After
seeing READY Master1 may (and does) re-request the bus on the
next cycle. (cycle )
Master2 is granted the bus.
Master2 asserts ADS (required at this cycle to maximize
data bandwidth but may take longer).
GNT2 is deasserted the state after ADS is detected since another
master is requesting the bus.
If a local bus master is bursting to/from instruction memory,
the 80960 will be prevented from accessing it until the instruction
memory arbiter re-arbitrates for the memory. Assuming the local bus
is doing a very long burst, re-arbitration will not take place unless
a refresh cycle is necessary or the local bus burst crosses a page boundary.
The 80960 could be held off for 3 us. (3 us is the time it takes a master to
burst 512 words to Brighton memory.)
The SPAR may be used to reduce this
time. If enabled (IEN=1), Brighton will count the number of cycles a local
bus master has done since the 80960 requested instruction memory. When this
count equals the programmed value (ICNT), Brighton will force rearbitration
for instruction memory and the 80960 will receive access (80960 has higher
priority to instruction memory). During this time, the local bus master
will be held NOT READY.
The SPAR is used in very much the same way for packet memory with
the following exceptions:
When not enabled (PEN=0), an 80960 request for packet memory will cause
a local bus preempt under certain conditions (see 4.0 , "Local Bus Accesses by Brighton").
This allows the local bus arbiter (and, to some extent, the local bus masters)
to determine how often the 80960 gets packet memory.
When PEN=1, the Brighton local bus arbiter will be DISABLED and
Brighton will use -BRIREQ and -BRIGNT signals to arbitrate for the local bus.
Also, 80960 will have priority
over the local bus when arbitration for packet memory takes place.
Brighton contains timer circuitry that is intended to
prevent the local bus from hanging. Brighton counts clocks during local
bus cycles. The timer starts with an ADS or READY and is reset by
READY. If the 64 clocks are counted then Brighton causes a local bus
EXCEPTION. This function can be disabled (see LTO bit, 2.24 , "Special Arbitration Register (SPAR)").
Brighton will provide memory protection hardware external to the 80960
that allows for 80960 processes (tasks) and local bus devices.
For tasks, the protection covers IO (x'1FFx xxxx'), packet memory and
instruction memory. Master0 protection and Master1 protection cover
instruction and packet memory.
Associated with each executable task are memory resident structures
called page tables.
Pages are defined to be 4KB in length.
The access bits are checked
by hardware on each protected access and an interrupt
is generated and the violating address latched if a violation is detected.
(see 2.12 , "Task Protection Address Trap Register (TPATR)" or 2.14 , "Local Bus Protection Address Trap Register (LPATR)").
Also, in the case of a write
violation, the write to memory will be blocked by the hardware.
On 80960 accesses to the local bus,
Brighton will prevent the
local bus cycle unless the access is allowed by
protection.
Page table length is based on the amount of memory installed.
Page tables must start on a 64 byte boundary in memory.
Page table entries are 32-bits wide and cover 16-4KB pages.
Examples of a task page table and local bus page table are
shown in Figure 8..
Figure 8. Sample Page Tables
The task table shows a 4KB read-only area starting at x'1FF80000' and an
8KB read/write area starting at x'20002000'.
The Master0 table shows a 16KB read-only area starting at x'20053000' and a
16KB write-only area starting at x'20069000'.
Remember, task tables begin with x'1FF00000' and local masters
start with x'20000000'.
The rest of the entries cover
to the top of installed memory.
Local bus memory is not protected by these tables.
In order to limit the number of memory references that the hardware must
make to check a page table entry, three separate caches are maintained in
the Brighton chip. An 8 entry full-way associative cache is maintained
for task page entries. This can cover a total of 512KB in 64KB pieces.
If the cache is full and another entry needs to be cached, Brighton will discard
the least-recently-used entry to make room for the new one.
A 1 entry cache is maintained for Master1
device accesses. A 2 entry cache is maintained for
the Master 0 interface. For the Master 0 interface one entry
is cached for "writes", and one
is cached for "reads", however, accesses are checked
against BOTH entries.
This write causes all
task page access bytes presently in the cache to be invalidated.
Similarly, a write to the AM_PTBR invalidates its page access byte
and a write to the MC_PTBR invalidates the Master 0 slave page access
byte cache. Brighton does not check writes to memory to
determine if they are cache entries. In order to be sure a change to the
tables will
be seen by Brighton, the PTBR must be written after the change.
Protection cache misses will cause accesses to be delayed
up to ten extra clocks.
For Master0 and Master1 burst accesses, only the initial address
is checked for protection.
Since the 80960CA prefetches instructions - and can do so across
page boundaries - care must be taken to avoid unwanted protection errors
If code extends to near the highest
address in a page and the next page is
protected, the 80960CA may fetch from the next page, causing a
protection error.
The Brighton module provides timer support through its integrated timer
subsystem.
Five hardware interval timers are provided (TMR0-4).
Four of the timers (TMR0,1,2,4) have a 1 ms interval and have 16-bit
resolution to allow for timing events from 1 ms to 65 seconds.
One of the timers (TMR3) is a 24-bit timer that uses a 333 ns
(actually 1/3 micro second)
timing interval to allow for timing events from 333 ns
to 6 seconds.
Each timer's function can be set up by programming the timer control
register
(see 2.1 , "Timer Control Register (TCR0-4)")
and by issuing timer specific commands.
Each of the five timers can generate an interrupt to the 80960 when a
zero count has been reached.
Each of the timers interrupt with a separate fixed encoded interrupt.
The Brighton module provides a fixed function UART built into the chip to
eliminate the need for a chip of this type during adapter code debug.
This is not intended to be used in an operational system environment,
but rather only as a tool in a lab environment during the debug phase of
code development.
The features of this port are described below.
The serial debug port has two fixed value interrupts assigned to
it.
An interrupt is generated when a receiver byte has been accumulated and
is available to be read.
This interrupt will remain pending as long as there is more data
available to be read.
Also, an interrupt is generated when the transmitter FIFO is empty.
These are listed from highest priority to lowest (internal to Brighton).
A simple priority encoder is used to output the highest pending
interrupt. The output will remain until the interrupt is cleared or a
higher interrupt is generated. These outputs are synchronized with
the clock.
The test begins with all the inputs set to '1'. Then, starting with IN1
(then IN2, IN3...INn)
they are changed to '0' (they are not changed back to '1').
Each time a signal is changed the
output should toggle.
Listed in Table 16. are
the input and output signals for the seven NAND trees in
Brighton. Also, the state the output is in when all its corresponding inputs
are '1's.
Part 2 tests the RASs, CASs, -PREADY and -ROSCS. It uses the scan chains
in Brighton in a flush-thru mode to toggle these signals.
To enable the mode make sure:
-DI is HIGH
-MTEST is HIGH
A_CLK is LOW
B_CLK is HIGH
C_CLK is LOW
PCLK is HIGH
Table 17. shows which inputs toggle which outputs.
INPUT SIGNAL
OUTPUTS OF SAME POLARITY AS INPUT
OUTPUTS OF OPPOSITE POLARITY AS INPUT
P_W/-R
-IRAS1
-ROSCS, -P_READY
-P_BE2
-ICAS0, -ICAS1
-IRAS0
PA(5)
(none)
-DRAS1
PA(2)
(none)
-DRAS0, -DCAS0, -DCAS1
Table 17. Scan-chain flush-thru signal correspondence
The setup for part 3 is a bit more complicated. The vectors that
should be applied to Brighton to setup this test are
shown in Table 18..
-DI should be HIGH during the entire test. Also, note that the first vector
is easily attained from part 2.
VECTOR #
A_CLK
B_CLK
C_CLK
POR
PCLK
-MTEST
P_W/-R
-P_BE2
P_A(5)
P_A(2)
1
L
H
L
X
H
H
L
H
L
L
2
H
L
L
X
H
H
L
H
L
L
3
H
L
H
L
L
L
X
X
X
X
4
H
L
L
L
L
L
X
X
X
X
5
H
H
L
L
H
L
X
X
X
X
H = HIGH, L = LOW, X = DON'T CARE
Table 18. Vectors for Manufacturing Test Part 3
After applying these five vectors the tester can now toggle certain P_A inputs
and observe a corresponding change on the DA or IA outputs. The exact
correlation is shown in Table 19..
This section documents the CFE local bus timings. All local bus
signal timings (outputs) are based on a capacitance of 55pf except
-L_GNT (30 pf) and -BRIREQ (20 pf). The MAX timings can be approximated
for lower capacitances (down to 30pf) by subtracting 0.25 ns per pf.
(e.g. at 35pf subtract (55pf-35pf)*.25 ns/pf = 5 ns from max timing.)
All timings are referenced to the rising edge of the PCLK.
Table 20. Brighton CFE local bus timings, outputs
Symbol
Description
Min (ns)
Max (ns)
Notes
Tov, Toh
-L_ADS
8
29
Tov, Toh
L_AD, L_ADP (address)
8
22
Tov, Toh
-L_BLAST
7
20
Tov, Toh
-L_BE, L_W/-R
8
22
1
Tov, Toh
L_AD, L_ADP (data from memory)
11
19
2
Tov, Toh
L_AD, L_ADP (data from Brighton register or master write)
8
29
Tov, Toh
-L_EXCPT
9
29
Tov, Toh
-L_READY
7
20
Tov, Toh
-L_GNT
9
28
Tov, Toh
-BRIREQ
8
25
Notes:
The CFE spec shows these signals as valid only during the
address state, however, Brighton (as a master) holds these through BLAST.
This timing is based on capacitances and memory speed shown
in 10.3 , "Memory Timing". The setup time appears large because the
data must be setup based on zero wait state timings.
This section documents the Processor interface timings.
Signal timings (outputs) are based on the following capacitances:
Table 22. Capacitance values used for timings
Signal Description
Min (pf)
Max (pf)
P_D
20
40
-P_READY
20
25
-ROSCS
20
25
INT
20
30
The MAX timings can be approximated
for different capacitances (20 to 50pf) by adding 0.25 ns per pf.
(e.g. -P_READY with 50 pf, add (50pf - 25pf)*.25 ns/pf = 6.25 ns to max timing.)
All timings are referenced to the rising edge of the PCLK.
This section lists several timings associated with the memory controller
portion of Brighton. Please take the following into consideration when viewing
these:
ADS, READY and BLAST are shown for reference only
The read and write timing figures shown show two-word bursts.
Longer bursts continue with the same timing as the second word.
RAS precharge is 2 clocks
For refresh cycles, RAS will be low for three clocks
For reference these are some timing parameters of the Austin Workstation
SIMM. Using a memory meeting these timings and capacitances as stated in
this spec should ensure correct operation. (Note: tCAC here is
the most critical timing, i.e. use memory with faster tCAC if possible)
C
CFE Common Front End
CMOS Complementary MOS
D
DMA Direct Memory Access
DRAM Dynamic Random Access Memory
E
ECC Error Checking and Correction
I
I/O Input/Output
K
KB Kilobyte
L
LSSD Level Sensitive Scan Design
M
MB Megabyte
MC or MCA Micro Channel or Micro Channel Architecture
MMIO Memory Mapped I/O
N
NMI Non-maskable interrupt
R
RAM Random Access Memory
ROS Read Only Storage
S
SIMM Single In-line Memory Module
SRAM Static Random Access Memory
T
TBD To be determined
V
VLSI Very-Large-Scale Integration
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Louis Ohland, Peter Wendt, William Walsh, David Beem, Tatsuo Sunagawa, Jim Shorney, Tim Clarke, Kevin Bowling, Tomáš Slavotínek, and many others.