Multiport/2 Adapter
X.25 /2 Adapter

@EFF0.ADF Realtime Interface Co-processor Multiport/2 or X.25 /2 Adapter

m82g5769.exe ARTIC Multiport/2 and X.25 Options Disk

IBM ARTIC Product Support (Radisys site, archived)
IBM ARTIC Legacy Downloads (Radisys site, archived)
Quadron ARTIC Software (Quadron site, archived)
Technical details about IBM ARTIC cards (Quadron site, archived)
MCA Cards - ARTIC Multiport/2 (go-ARTIC site, archived)

Software
ARTIC186 Documentation
Multiport/2 Base Card
4-port RS-232 EIB
8-port RS-232 EIB
Components
ADF Sections


Software

csp1031.exe Realtime Interface Co-Processor C Language Support README

Microcode

rcm153.exe OS/2 and DOS Realtime Control Microcode (RCM) V1.53 README
rcm153a.tar.z (dead) AIX Realtime Control Microcode (RCM) V1.53 README
rcm204a.tar.z (dead) AIX Realtime Control Microcode (RCM) V2.04 README
rcm204d.exe DOS Realtime Control Microcode (RCM) V2.04 README
rcm204o.exe OS/2 Realtime Control Microcode (RCM) V2.04 README


ARTIC186 Documentation

Hardware

ARTIC Multiport/2 Hardware Technical Reference, 2nd Ed., Oct 1987
ARTIC Multiport Model 2 & Portmaster EIB Developer's Guide, 2nd Ed., Aug 1996
ARTIC X.25 Interface Co-Processor/2 Technical Reference, v1.01, Sep 1996

Software

ARTIC AIX Support User's Guide, 5th Ed., Dec 1998
ARTIC C Language Support User's Guide, v1.03.01, Aug 1996
   Volume I - System Unit
   Volume II - Co-Processor Adapter
ARTIC DOS Support User's Guide, v1.04, Jun 1996
ARTIC Extended Services User's Guide, 3rd Ed., Aug 1996
ARTIC Firmware Technical Reference, 2nd Ed., Jul 1990
   Volume 1 - System Interfaces and Functions
   Volume 2 - Functions
   Volume 3 - Data Structures
ARTIC OS/2 Support User's Guide, v1.03.5, Jun 1996
ARTIC Support for Windows NT and Windows 98 User's Guide, 2nd Ed., Mar 1999
X.25 Co-Processor Supt Program: Programmer's Reference Manual, 4th Ed., Jun 1996
X.25 Co-Processor Support Program: User's Guide, 4th Ed., Jun 1996


Multiport/2 Base Card P/N 16F2200

A Intel A80186
B,D Zilog Z0803606VSC Z-CIO
C,E Zilog Z0803008VSC Z-SCC
CR LED
F 09F1877ESD SSIC
JP1 Jumper Pack
K1,2 60-pin socket
SIP1 Dual 30-pin SIMM socket
U8 BIOS 16F2201
U9 BIOS 16F2203
Y1 14.7456 MHz osc
Y2 25.0 MHz osc

Sorry, but the alpha IDs are made up. I can't see any markings by the chips...

Z0803606VSC Z-CIO datasheet
Z0803008VSC Z-SCC datasheet

Each ARTIC Multiport/2 is configured with an Intel 80C186 processor, 512 KB to 1 MB of memory, and the ability to expand the number and type of communications ports using a variety of electrical interface boards (EIBs) and cables. Any single port can operate up to 38.4 Kbps, and, when expanded with an eight-port EIB, all ports can communicate at 9600 bps.


4-ports RS-232 EIB

K1B, K2B 60-pin Header
P1 78-pin female Port
U1,2 Zilog Z80C3008PSC

Note: K1B is the outermost header.

Do you know what this interface card is? Tell Us! It came on a Multiport/2 with 512K.


8-port RS-232 EIB

K0 30-pin header
K1,2 60-pin dual header
P1 ?? pin port
U1,2 SCN26562C4A52
U37 33F5251

Components

# 6247 ... ARTIC Multiport/2 1 MB
# 6263 ... ARTIC Multiport/2 512 KB

# 6265 ... 8-ports RS-232 EIB
# 6326 ... 8-ports RS-422 EIB
# 6267 ... 4-ports RS-232 EIB
# 6266 ... 4-ports RS-232 & 4-ports RS-422 EIB
# 6327 ... 6-ports RS-232 Sync EIB

# 6246 ... 8-port cable
# 2028 ... 6-port cable
# 7423 ... 8-port Direct Attach Modem cable


30-pin SIMMs

My sneaky suspicion, these are the same rare chips used by the SCSI w/cache:

512K - Mitsubishi MH25609BJ-12
1MB - IBM 37F2016D 50F8938

LED Indicator

A light-emitting diode (LED) indicator provides a visual status of the watchdog timer status and error status. The LED turns on when the watchdog timer expires or a hardware error is detected by microcode on the co-processor adapter. The LED also turns on when power is applied initially to the co-processor adapter; it turns off after a successful power-on self-test (POST).

Co-processor adapter PROM

Two 27C256 chips (200-nS access time) provide the 64KB of co-processor adapter PROM.

8030 Serial Communications Controllers (SSC)

The primary function of the four SCCs is to provide controller logic for eight independent serial communications ports.

After initial configuring of the 8030s by the Realtime Control Microcode, a major portion of the serial communications workload is relieved from the 80186 processor and is performed by the 8030s.

8036 Counter/Timer and Parallel I/O Unit (CIO)

The CIO provides peripheral I/O support through an integrated chip containing three independent 16-bit counters or timers, two independent 8-bit double-buffered I/O ports, and a special purpose 4-bit I/O port.

One timer and the 4-bit I/O port are used by the on-board watchdog timer to provide interrupt notification of a run-away CPU or a run-away operation. Two timers and two ports are used in peripheral I/O control of data through the co-processor adapter's electrical interface boards.

The Realtime Control Microcode is the on-board multitasking supervisory control program (Task 0) for the co-processor adapter. The program can be found on the Realtime Interface Co-Processor Diagnostics and Realtime Control Microcode diskette that came with your co-processor adapter.

Realtime Control Microcode (RCM)

The RCM supports the co-processor adapters through two versions. Version 1.x is named ICAAIM.COM. It provides support for the Realtime Interface Co-processor Adapter, the Multiport Adapter, and the Multiport/2 Adapter. Version 2.x is named ICARCM.COM. It provides support for the Portmaster Adapter/A and the Multiport Adapter, Model 2.

Watchdog Timer

A watchdog timer has been incorporated on the co-processor adapter card. This timer, once activated, must continually be strobed by software so that it will not time out. If the 80C186 processor ever has a fatal error, this timer will reach its terminal count. The terminal count will activate an LED indicator on the co-processor adapter card.

One timer and one 4-bit I/O port are used by the on-board watchdog timer to provide interrupt notification of a runaway CPU.

Shared Storage Interface Chip

The SSIC provides a convenient and flexible way of passing data and control bytes between the 80186 bus and the system unit bus. This is accomplished through an IBM CMOS gate array called the Shared Storage Interface Chip, an array of 10,000 gates. The chip adapts to both 8-bit and 16-bit data buses on the system unit bus. The VLSI gate array's basic purpose is to provide a high performance interface between the co-processor adapter and the system unit. All data communications between the system unit and the co-processor adapter are done through this interface. This is accomplished through the following functions performed by the Shared Storage Interface Chip.

Direct Memory Access

The co-processor adapter card has 16 DMA channels dedicated to the transmit and the receive function of each of eight ports. In addition, two DMA channels are assigned to on-card memory-to-memory transfers.


@EFF0H IBM Realtime Interface Co-processor Multiport/2 or X.25 /2

Physical Card Number
   The IBM Realtime Interface Co-processor Multiport/2 or X.25 Interface Co-processor/2 supports up to 16 different adapters in various RAM/ROM locations, utilizing 7 different interrupt levels and various clocking options.

The Physical Card Designation will be automatically configured with the following rules:

1. I/O address (Physical Card Designation) is the lowest possible interrupt level.

The I/O address defines the physical card designation of the IBM Realtime Interface Co-processor Multiport/2 or X.25 Interface Co-processor/2. This is actually a RANGE of addresses, 8 bytes wide. The preferred address range is the lowest available.
     <"Physical Card 0; 02A0H-02A7H">, Physical Card 1; 06A0-06A7, Physical Card 2; 0AA0-0AA7, Physical Card 3; 0EA0-0EA7, Physical Card 4; 12A0-12A7, Physical Card 5; 16A0-16A7, Physical Card 6; 1AA0-1AA7, Physical Card 7; 1EA0-1EA7, Physical Card 8; 22A0-22A7, Physical Card 9; 26A0-26A7, Physical Card A; 2AA0-26A7, Physical Card B; 2EA0-2EA7, Physical Card C; 32A0-32A7, Physical Card D; 36A0-36A7, Physical Card E; 3AA0-3AA7", Physical Card F; 3EA0-3EA7"

Shared Storage Window Location & Size
   The IBM Realtime Interface Co-processor Multiport/2 or X.25 /2 supports up to 16 different adapters in various RAM/ROM locations utilizing 7 different interrupt levels and various clocking options. The Memory Location will be automatically configured with the following rules:

1. Memory address is the lowest possible and the Shared Storage Window size is 8KB.

The Shared Storage Window is an unused ROM or RAM address range that is used as a window into the RAM on the IBM Realtime Interface Co-processor Multiport/2 or X.25 /2. The preferred choice is the window at the lowest address with a size of 8K. The 8K window size is compatible with the IBM Realtime Interface Co-processor and the IBM Realtime Interface Co-processor/Multiport.
<1MB Window Options
     <"C0000H-C1FFFH (8K Window)">, C2000-C3FFF, C4000-C5FFF, C6000-C7FFF, C8000-C9FFF, CA000-CBFFF, CC000-CDFFF, CE000-CFFFF, D0000-D1FFF, D2000-D3FFF, D4000-D5FFF, D6000-D7FFF, D8000-D9FFF, DA000-DBFFF, DC000-DDFFF, DE000-DFFFF
     <"C0000H-C3FFFH (16K Window)">, C4000-C7FFF, C8000-CBFFF, CC000-CFFFF, D0000-D3FFF, D4000-D7FFF, D8000-DBFFF,DC000-DFFFF
     <"C0000H-C7FFFH (32K Window)">, C8000-CFFFF, D0000-D7FFF, D8000-DFFFF
     <"C0000H-CFFFFH (64K Window)">, D0000-DFFFF
>1MB Window Options
     <"FC0000H-FC1FFFH (8K Window)">, FC2000-FC3FFF, FC4000-FC5FFF, FC8000-FC9FFF, FCA000-FCBFFF, FCC000-FCDFFF, FCE000-FCFFFF, FD0000-FD1FFF, FD2000-FD3FFF, FD4000-FD5FFF, FD6000-FD7FFF, FD8000-FD9FFF, FDA000-FDBFFF, FDC000-FDDFFF, FDE000H-FDFFFF
     <FC0000H-FC3FFFH (16K Window)">, FC4000-FC7FFF, FC8000-FCBFFF, FCC000-FCFFFF, FD0000-FD3FFF, FD4000-FD7FFF, FD8000-FDBFFF, FDC000-FDFFFF
     <"FC0000H-FC7FFFH (32K Window)">, FC8000-FCFFFF, FD0000-FD7FFF, FD8000-FDFFFF
     <"FC0000H-FCFFFFH (64K Window)">, FD0000-FDFFFF

Interrupt Level
   The IBM Realtime Interface Co-processor Multiport/2 or X.25 /2 supports up to 16 different adapters in various RAM/ROM locations, utilizing 7 different interrupt levels and various clocking options. The Interrupt Level will be automatically configured with the following rules:

1. Interrupt Level 7 is requested.
2. Interrupt Levels are then requested for subsequent cards in ascending order.

The interrupt level is the prioritized interrupt request line on which the IBM Realtime Interface Co-processor Multiport 2 or X.25 /2 will interrupt the Personal System 2. The interrupt priorities are as follows (greatest priority first): 9, 10, 11, 12, 3, 4, 7. The preferred interrupt level is 7.
     <"Interrupt Level 7">, 3, 4, 9, 10, 11, 12

Port 0 Transmit Clock Source
   The IBM Realtime Interface Co-processor Multiport/2 or X.25 /2 supports up to 16 different adapters in various RAM/ROM locations, utilizing 7 different interrupt levels and various clocking options. The Port 0 Transmit Clock Source will be automatically configured to provide DCE sourced transmit clocking.

The Co-processor can be configured to provide Data Terminal Equipment (DTE) sourced transmit clocking (i.e. the clock is sourced by the Co-processor) or Data Computer Equipment (DCE) sourced transmit clocking (e.g. a modem).
     <"DCE sourced clocking">, DTE sourced clocking

Port 0 Receive Clock Source
   The IBM Realtime Interface Co-processor Multiport/2 or X.25 /2 supports up to 16 different adapters in various RAM/ROM locations, utilizing 7 different interrupt levels and various clocking options. The Port 0 Receive Clock Source will be automatically configured as REMOTE. The Co-processor Receive (RX) clock can be either LOCAL or REMOTE, depending on whether or not a remote clock is used (e.g. from a modem or other DCE). The LOCAL clock has a Digital Phase Locked Loop (DPLL), optionally defined as divided by 16 or divided by 32, depending on the application clocking scheme.
     <"DCE Sourced Remote Clocking">, DPLL Clk/16 Local Clocking, DPLL Clk/32 Local Clocking

Port 1 Transmit Clock Source
   The IBM Realtime Interface Co-processor Multiport/2 or X.25 /2 supports up to 16 different adapters in various RAM/ROM locations, utilizing 7 different interrupt levels and various clocking options. The Port 1 Transmit Clock Source will be automatically configured to provide DCE sourced transmit clocking.

The Co-processor can be configured to provide Data Terminal Equipment (DTE) sourced transmit clocking (i.e. the clock is sourced by the Co-processor) or Data Computer Equipment (DCE) sourced transmit clocking (e.g. a modem).
     <"DCE sourced clocking">, DTE sourced clocking

Port 1 Receive Clock Source
   The IBM Realtime Interface Co-processor Multiport/2 or X.15 /2 supports up to 16 different adapters in various RAM/ROM locations, utilizing 7 different interrupt levels and various clocking options. The Port 1 Receive Clock Source will be automatically configured as REMOTE. The Co-processor Receive (RX) clock can be either LOCAL or REMOTE, depending on whether or not a remote clock is used (e.g. from a modem or other DCE). The LOCAL clock has a Digital Phase Locked Loop (DPLL), optionally defined as divided by 16 or divided by 32, depending on the application clocking scheme.
     <"DCE Sourced Remote Clocking">, DPLL Clk/16 Local Clocking, DPLL Clk/32 Local Clocking

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